1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
8 * Marvell Semiconductor <www.marvell.com>
17 * GPIO Register map for Marvell SOCs
20 u32 gplr; /* Pin Level Register - 0x0000 */
22 u32 gpdr; /* Pin Direction Register - 0x000C */
24 u32 gpsr; /* Pin Output Set Register - 0x0018 */
26 u32 gpcr; /* Pin Output Clear Register - 0x0024 */
28 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
30 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
32 u32 gedr; /* Edge Detect Status Register - 0x0048 */
34 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
36 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
38 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
41 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
44 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
47 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
50 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
53 #endif /* __MVGPIO_H__ */