3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
7 * Marvell Semiconductor <www.marvell.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
33 #ifdef CONFIG_SHEEVA_88SV331xV5
35 * GPIO Register map for SHEEVA 88SV331xV5
38 u32 gplr; /* Pin Level Register - 0x0000 */
40 u32 gpdr; /* Pin Direction Register - 0x000C */
42 u32 gpsr; /* Pin Output Set Register - 0x0018 */
44 u32 gpcr; /* Pin Output Clear Register - 0x0024 */
46 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
48 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
50 u32 gedr; /* Edge Detect Status Register - 0x0048 */
52 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
54 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
56 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
59 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
62 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
65 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
68 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
71 #error "CPU core subversion not defined"
74 #endif /* __MVGPIO_H__ */