1 // SPDX-License-Identifier: GPL-2.0+
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
6 * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
8 * Copyright 2010 eXMeritus, A Boeing Company
17 #include <dm/of_access.h>
29 struct mpc8xxx_gpio_data {
30 /* The bank's register base in memory */
31 struct ccsr_gpio __iomem *base;
32 /* The address of the registers; used to identify the bank */
34 /* The GPIO count of the bank */
36 /* The GPDAT register cannot be used to determine the value of output
37 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
50 inline u32 gpio_mask(uint gpio)
52 return (1U << (31 - (gpio)));
55 static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask)
57 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
59 if (data->little_endian)
60 return in_le32(&data->base->gpdat) & mask;
62 return in_be32(&data->base->gpdat) & mask;
65 static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask)
67 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
69 if (data->little_endian)
70 return in_le32(&data->base->gpdir) & mask;
72 return in_be32(&data->base->gpdir) & mask;
75 static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask)
77 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
79 if (data->little_endian)
80 return in_le32(&data->base->gpodr) & mask;
82 return in_be32(&data->base->gpodr) & mask;
85 static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32
88 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
89 /* GPODR register 1 -> open drain on */
90 if (data->little_endian)
91 setbits_le32(&data->base->gpodr, gpios);
93 setbits_be32(&data->base->gpodr, gpios);
96 static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev,
99 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
100 /* GPODR register 0 -> open drain off (actively driven) */
101 if (data->little_endian)
102 clrbits_le32(&data->base->gpodr, gpios);
104 clrbits_be32(&data->base->gpodr, gpios);
107 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
109 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
110 u32 mask = gpio_mask(gpio);
112 /* GPDIR register 0 -> input */
113 if (data->little_endian)
114 clrbits_le32(&data->base->gpdir, mask);
116 clrbits_be32(&data->base->gpdir, mask);
121 static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
123 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
124 struct ccsr_gpio *base = data->base;
125 u32 mask = gpio_mask(gpio);
129 data->dat_shadow |= mask;
131 data->dat_shadow &= ~mask;
134 if (data->little_endian)
135 gpdir = in_le32(&base->gpdir);
137 gpdir = in_be32(&base->gpdir);
139 gpdir |= gpio_mask(gpio);
141 if (data->little_endian) {
142 out_le32(&base->gpdat, gpdir & data->dat_shadow);
143 out_le32(&base->gpdir, gpdir);
145 out_be32(&base->gpdat, gpdir & data->dat_shadow);
146 out_be32(&base->gpdir, gpdir);
152 static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
155 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
157 /* GPIO 28..31 are input only on MPC5121 */
158 if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
161 return mpc8xxx_gpio_set_value(dev, gpio, value);
164 static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
166 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
168 if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) {
169 /* Output -> use shadowed value */
170 return !!(data->dat_shadow & gpio_mask(gpio));
173 /* Input -> read value from GPDAT register */
174 return !!mpc8xxx_gpio_get_val(dev, gpio_mask(gpio));
177 static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
181 dir = !!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio));
182 return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
185 #if CONFIG_IS_ENABLED(OF_CONTROL)
186 static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
188 struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
189 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
194 if (ofnode_read_bool(dev_ofnode(dev), "little-endian"))
195 data->little_endian = true;
197 if (data->little_endian)
198 dev_read_u32_array(dev, "reg", reg, 4);
200 dev_read_u32_array(dev, "reg", reg, 2);
202 if (data->little_endian) {
203 for (i = 0; i < 2; i++)
204 reg[i] = be32_to_cpu(reg[i]);
207 addr = dev_translate_address(dev, reg);
211 if (data->little_endian)
216 plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
222 static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev)
224 struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
225 struct mpc8xxx_gpio_plat *plat = dev_get_plat(dev);
226 unsigned long size = plat->size;
227 ulong driver_data = dev_get_driver_data(dev);
232 priv->addr = plat->addr;
233 priv->base = map_sysmem(plat->addr, size);
238 priv->gpio_count = plat->ngpios;
239 priv->dat_shadow = 0;
241 priv->type = driver_data;
246 static int mpc8xxx_gpio_probe(struct udevice *dev)
248 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
249 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
252 mpc8xxx_gpio_plat_to_priv(dev);
254 snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
260 if (ofnode_device_is_compatible(dev_ofnode(dev), "fsl,qoriq-gpio")) {
261 unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio)
264 out_be32((unsigned int *)gpibe, 0xffffffff);
267 uc_priv->bank_name = str;
268 uc_priv->gpio_count = data->gpio_count;
273 static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
274 .direction_input = mpc8xxx_gpio_direction_input,
275 .direction_output = mpc8xxx_gpio_direction_output,
276 .get_value = mpc8xxx_gpio_get_value,
277 .set_value = mpc8xxx_gpio_set_value,
278 .get_function = mpc8xxx_gpio_get_function,
281 static const struct udevice_id mpc8xxx_gpio_ids[] = {
282 { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
283 { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
284 { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
285 { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
286 { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
287 { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
288 { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
292 U_BOOT_DRIVER(gpio_mpc8xxx) = {
293 .name = "gpio_mpc8xxx",
295 .ops = &gpio_mpc8xxx_ops,
296 #if CONFIG_IS_ENABLED(OF_CONTROL)
297 .of_to_plat = mpc8xxx_gpio_of_to_plat,
298 .plat_auto = sizeof(struct mpc8xxx_gpio_plat),
299 .of_match = mpc8xxx_gpio_ids,
301 .probe = mpc8xxx_gpio_probe,
302 .priv_auto = sizeof(struct mpc8xxx_gpio_data),