2 * Copyright (C) 2016-2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
12 #include <linux/sizes.h>
13 #include <linux/errno.h>
14 #include <asm/global_data.h>
17 #define UNIPHIER_GPIO_LINES_PER_BANK 8
19 #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
20 #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
21 #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
23 struct uniphier_gpio_priv {
27 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
34 * Unfortunately, the GPIO port registers are not contiguous because
35 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
37 if (reg >= UNIPHIER_GPIO_IRQ_EN)
43 static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
44 unsigned int *bank, u32 *mask)
46 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
47 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
50 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
51 unsigned int reg, u32 mask, u32 val)
55 tmp = readl(priv->regs + reg);
58 writel(tmp, priv->regs + reg);
61 static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
62 unsigned int reg, u32 mask, u32 val)
64 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
69 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
73 static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
74 unsigned int reg, int val)
79 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
81 uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
84 static int uniphier_gpio_offset_read(struct udevice *dev,
85 unsigned int offset, unsigned int reg)
87 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
88 unsigned int bank, reg_offset;
91 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
92 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
94 return !!(readl(priv->regs + reg_offset) & mask);
97 static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
99 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
100 GPIOF_INPUT : GPIOF_OUTPUT;
103 static int uniphier_gpio_direction_input(struct udevice *dev,
106 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
111 static int uniphier_gpio_direction_output(struct udevice *dev,
112 unsigned int offset, int value)
114 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
115 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
120 static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
122 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
125 static int uniphier_gpio_set_value(struct udevice *dev,
126 unsigned int offset, int value)
128 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
133 static const struct dm_gpio_ops uniphier_gpio_ops = {
134 .direction_input = uniphier_gpio_direction_input,
135 .direction_output = uniphier_gpio_direction_output,
136 .get_value = uniphier_gpio_get_value,
137 .set_value = uniphier_gpio_set_value,
138 .get_function = uniphier_gpio_get_function,
141 static int uniphier_gpio_probe(struct udevice *dev)
143 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
144 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
147 addr = devfdt_get_addr(dev);
148 if (addr == FDT_ADDR_T_NONE)
151 priv->regs = devm_ioremap(dev, addr, SZ_512);
155 uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
161 static const struct udevice_id uniphier_gpio_match[] = {
162 { .compatible = "socionext,uniphier-gpio" },
166 U_BOOT_DRIVER(uniphier_gpio) = {
167 .name = "uniphier-gpio",
169 .of_match = uniphier_gpio_match,
170 .probe = uniphier_gpio_probe,
171 .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
172 .ops = &uniphier_gpio_ops,