2 * Toumaz Xenif TZ1090 GPIO handling.
4 * Copyright (C) 2008-2013 Imagination Technologies Ltd.
6 * Based on ARM PXA code and others.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/export.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <asm/global_lock.h>
28 /* Register offsets from bank base address */
29 #define REG_GPIO_DIR 0x00
30 #define REG_GPIO_IRQ_PLRT 0x20
31 #define REG_GPIO_IRQ_TYPE 0x30
32 #define REG_GPIO_IRQ_EN 0x40
33 #define REG_GPIO_IRQ_STS 0x50
34 #define REG_GPIO_BIT_EN 0x60
35 #define REG_GPIO_DIN 0x70
36 #define REG_GPIO_DOUT 0x80
38 /* REG_GPIO_IRQ_PLRT */
39 #define REG_GPIO_IRQ_PLRT_LOW 0
40 #define REG_GPIO_IRQ_PLRT_HIGH 1
42 /* REG_GPIO_IRQ_TYPE */
43 #define REG_GPIO_IRQ_TYPE_LEVEL 0
44 #define REG_GPIO_IRQ_TYPE_EDGE 1
47 * struct tz1090_gpio_bank - GPIO bank private data
48 * @chip: Generic GPIO chip for GPIO bank
49 * @domain: IRQ domain for GPIO bank (may be NULL)
50 * @reg: Base of registers, offset for this GPIO bank
51 * @irq: IRQ number for GPIO bank
52 * @label: Debug GPIO bank label, used for storage of chip->label
54 * This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
55 * and the callbacks for the gpio_chip can access the private data with the
56 * to_bank() macro below.
58 struct tz1090_gpio_bank {
59 struct gpio_chip chip;
60 struct irq_domain *domain;
65 #define to_bank(c) container_of(c, struct tz1090_gpio_bank, chip)
68 * struct tz1090_gpio - Overall GPIO device private data
69 * @dev: Device (from platform device)
70 * @reg: Base of GPIO registers
72 * Represents the overall GPIO device. This structure is actually only
73 * temporary, and used during init.
81 * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
82 * @priv: Overall GPIO device private data
83 * @node: Device tree node specific to this GPIO bank
84 * @index: Index of bank in range 0-2
86 struct tz1090_gpio_bank_info {
87 struct tz1090_gpio *priv;
88 struct device_node *node;
92 /* Convenience register accessors */
93 static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
94 unsigned int reg_offs, u32 data)
96 iowrite32(data, bank->reg + reg_offs);
99 static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
100 unsigned int reg_offs)
102 return ioread32(bank->reg + reg_offs);
105 /* caller must hold LOCK2 */
106 static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
107 unsigned int reg_offs,
112 value = tz1090_gpio_read(bank, reg_offs);
113 value &= ~BIT(offset);
114 tz1090_gpio_write(bank, reg_offs, value);
117 static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
118 unsigned int reg_offs,
123 __global_lock2(lstat);
124 _tz1090_gpio_clear_bit(bank, reg_offs, offset);
125 __global_unlock2(lstat);
128 /* caller must hold LOCK2 */
129 static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
130 unsigned int reg_offs,
135 value = tz1090_gpio_read(bank, reg_offs);
136 value |= BIT(offset);
137 tz1090_gpio_write(bank, reg_offs, value);
140 static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
141 unsigned int reg_offs,
146 __global_lock2(lstat);
147 _tz1090_gpio_set_bit(bank, reg_offs, offset);
148 __global_unlock2(lstat);
151 /* caller must hold LOCK2 */
152 static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
153 unsigned int reg_offs,
159 value = tz1090_gpio_read(bank, reg_offs);
160 value &= ~BIT(offset);
162 value |= BIT(offset);
163 tz1090_gpio_write(bank, reg_offs, value);
166 static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
167 unsigned int reg_offs,
173 __global_lock2(lstat);
174 _tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
175 __global_unlock2(lstat);
178 static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
179 unsigned int reg_offs,
182 return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
185 /* GPIO chip callbacks */
187 static int tz1090_gpio_direction_input(struct gpio_chip *chip,
190 struct tz1090_gpio_bank *bank = to_bank(chip);
191 tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
196 static int tz1090_gpio_direction_output(struct gpio_chip *chip,
197 unsigned int offset, int output_value)
199 struct tz1090_gpio_bank *bank = to_bank(chip);
202 __global_lock2(lstat);
203 _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
204 _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
205 __global_unlock2(lstat);
213 static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
215 struct tz1090_gpio_bank *bank = to_bank(chip);
217 return tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
221 * Set output GPIO level
223 static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
226 struct tz1090_gpio_bank *bank = to_bank(chip);
228 tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
231 static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
233 struct tz1090_gpio_bank *bank = to_bank(chip);
236 ret = pinctrl_request_gpio(chip->base + offset);
240 tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
241 tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);
246 static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
248 struct tz1090_gpio_bank *bank = to_bank(chip);
250 pinctrl_free_gpio(chip->base + offset);
252 tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
255 static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
257 struct tz1090_gpio_bank *bank = to_bank(chip);
262 return irq_create_mapping(bank->domain, offset);
265 /* IRQ chip handlers */
267 /* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
268 static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
270 return (struct tz1090_gpio_bank *)data->domain->host_data;
273 static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank,
276 tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset);
279 static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank,
280 unsigned int offset, bool enable)
282 tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable);
285 static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
286 unsigned int offset, unsigned int polarity)
288 tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
291 static int tz1090_gpio_valid_handler(struct irq_desc *desc)
293 return desc->handle_irq == handle_level_irq ||
294 desc->handle_irq == handle_edge_irq;
297 static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
298 unsigned int offset, unsigned int type)
300 tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
303 /* set polarity to trigger on next edge, whether rising or falling */
304 static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
307 unsigned int value_p, value_i;
311 * Set the GPIO's interrupt polarity to the opposite of the current
312 * input value so that the next edge triggers an interrupt.
314 __global_lock2(lstat);
315 value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
316 value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
317 value_p &= ~BIT(offset);
318 value_p |= value_i & BIT(offset);
319 tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
320 __global_unlock2(lstat);
323 static void gpio_ack_irq(struct irq_data *data)
325 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
327 tz1090_gpio_irq_clear(bank, data->hwirq);
330 static void gpio_mask_irq(struct irq_data *data)
332 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
334 tz1090_gpio_irq_enable(bank, data->hwirq, false);
337 static void gpio_unmask_irq(struct irq_data *data)
339 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
341 tz1090_gpio_irq_enable(bank, data->hwirq, true);
344 static unsigned int gpio_startup_irq(struct irq_data *data)
346 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
347 irq_hw_number_t hw = data->hwirq;
348 struct irq_desc *desc = irq_to_desc(data->irq);
351 * This warning indicates that the type of the irq hasn't been set
352 * before enabling the irq. This would normally be done by passing some
353 * trigger flags to request_irq().
355 WARN(!tz1090_gpio_valid_handler(desc),
356 "irq type not set before enabling gpio irq %d", data->irq);
358 tz1090_gpio_irq_clear(bank, hw);
359 tz1090_gpio_irq_enable(bank, hw, true);
363 static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
365 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
367 unsigned int polarity;
370 case IRQ_TYPE_EDGE_BOTH:
371 type = REG_GPIO_IRQ_TYPE_EDGE;
372 polarity = REG_GPIO_IRQ_PLRT_LOW;
374 case IRQ_TYPE_EDGE_RISING:
375 type = REG_GPIO_IRQ_TYPE_EDGE;
376 polarity = REG_GPIO_IRQ_PLRT_HIGH;
378 case IRQ_TYPE_EDGE_FALLING:
379 type = REG_GPIO_IRQ_TYPE_EDGE;
380 polarity = REG_GPIO_IRQ_PLRT_LOW;
382 case IRQ_TYPE_LEVEL_HIGH:
383 type = REG_GPIO_IRQ_TYPE_LEVEL;
384 polarity = REG_GPIO_IRQ_PLRT_HIGH;
386 case IRQ_TYPE_LEVEL_LOW:
387 type = REG_GPIO_IRQ_TYPE_LEVEL;
388 polarity = REG_GPIO_IRQ_PLRT_LOW;
394 tz1090_gpio_irq_type(bank, data->hwirq, type);
395 if (type == REG_GPIO_IRQ_TYPE_LEVEL)
396 __irq_set_handler_locked(data->irq, handle_level_irq);
398 __irq_set_handler_locked(data->irq, handle_edge_irq);
400 if (flow_type == IRQ_TYPE_EDGE_BOTH)
401 tz1090_gpio_irq_next_edge(bank, data->hwirq);
403 tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);
408 #ifdef CONFIG_SUSPEND
409 static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
411 struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
413 #ifdef CONFIG_PM_DEBUG
414 pr_info("irq_wake irq%d state:%d\n", data->irq, on);
417 /* wake on gpio block interrupt */
418 return irq_set_irq_wake(bank->irq, on);
421 #define gpio_set_irq_wake NULL
424 /* gpio virtual interrupt functions */
425 static struct irq_chip gpio_irq_chip = {
426 .irq_startup = gpio_startup_irq,
427 .irq_ack = gpio_ack_irq,
428 .irq_mask = gpio_mask_irq,
429 .irq_unmask = gpio_unmask_irq,
430 .irq_set_type = gpio_set_irq_type,
431 .irq_set_wake = gpio_set_irq_wake,
432 .flags = IRQCHIP_MASK_ON_SUSPEND,
435 static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
438 unsigned int irq_stat, irq_no;
439 struct tz1090_gpio_bank *bank;
440 struct irq_desc *child_desc;
442 bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
443 irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
444 tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
445 tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
446 0x3FFFFFFF; /* 30 bits only */
448 for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
452 irq_no = irq_linear_revmap(bank->domain, hw);
453 child_desc = irq_to_desc(irq_no);
455 /* Toggle edge for pin with both edges triggering enabled */
456 if (irqd_get_trigger_type(&child_desc->irq_data)
457 == IRQ_TYPE_EDGE_BOTH)
458 tz1090_gpio_irq_next_edge(bank, hw);
460 BUG_ON(!tz1090_gpio_valid_handler(child_desc));
461 generic_handle_irq_desc(irq_no, child_desc);
465 static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq,
468 irq_set_chip(irq, &gpio_irq_chip);
472 static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = {
473 .map = tz1090_gpio_irq_map,
474 .xlate = irq_domain_xlate_twocell,
477 static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
479 struct device_node *np = info->node;
480 struct device *dev = info->priv->dev;
481 struct tz1090_gpio_bank *bank;
483 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
485 dev_err(dev, "unable to allocate driver data\n");
489 /* Offset the main registers to the first register in this bank */
490 bank->reg = info->priv->reg + info->index * 4;
492 /* Set up GPIO chip */
493 snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
495 bank->chip.label = bank->label;
496 bank->chip.dev = dev;
497 bank->chip.direction_input = tz1090_gpio_direction_input;
498 bank->chip.direction_output = tz1090_gpio_direction_output;
499 bank->chip.get = tz1090_gpio_get;
500 bank->chip.set = tz1090_gpio_set;
501 bank->chip.free = tz1090_gpio_free;
502 bank->chip.request = tz1090_gpio_request;
503 bank->chip.to_irq = tz1090_gpio_to_irq;
504 bank->chip.of_node = np;
506 /* GPIO numbering from 0 */
507 bank->chip.base = info->index * 30;
508 bank->chip.ngpio = 30;
510 /* Add the GPIO bank */
511 gpiochip_add(&bank->chip);
513 /* Get the GPIO bank IRQ if provided */
514 bank->irq = irq_of_parse_and_map(np, 0);
516 /* The interrupt is optional (it may be used by another core on chip) */
518 dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
523 dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
527 * Initialise all interrupts to disabled so we don't get
528 * spurious ones on a dirty boot and hit the BUG_ON in the
531 tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
533 /* Add a virtual IRQ for each GPIO */
534 bank->domain = irq_domain_add_linear(np,
536 &tz1090_gpio_irq_domain_ops,
539 /* Setup chained handler for this GPIO bank */
540 irq_set_handler_data(bank->irq, bank);
541 irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
546 static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
548 struct device_node *np = priv->dev->of_node;
549 struct device_node *node;
551 for_each_available_child_of_node(np, node) {
552 struct tz1090_gpio_bank_info info;
556 ret = of_property_read_u32(node, "reg", &addr);
558 dev_err(priv->dev, "invalid reg on %s\n",
563 dev_err(priv->dev, "index %u in %s out of range\n",
564 addr, node->full_name);
569 info.node = of_node_get(node);
572 ret = tz1090_gpio_bank_probe(&info);
574 dev_err(priv->dev, "failure registering %s\n",
582 static int tz1090_gpio_probe(struct platform_device *pdev)
584 struct device_node *np = pdev->dev.of_node;
585 struct resource *res_regs;
586 struct tz1090_gpio priv;
589 dev_err(&pdev->dev, "must be instantiated via devicetree\n");
593 res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 dev_err(&pdev->dev, "cannot find registers resource\n");
599 priv.dev = &pdev->dev;
601 /* Ioremap the registers */
602 priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
603 res_regs->end - res_regs->start);
605 dev_err(&pdev->dev, "unable to ioremap registers\n");
610 tz1090_gpio_register_banks(&priv);
615 static struct of_device_id tz1090_gpio_of_match[] = {
616 { .compatible = "img,tz1090-gpio" },
620 static struct platform_driver tz1090_gpio_driver = {
622 .name = "tz1090-gpio",
623 .owner = THIS_MODULE,
624 .of_match_table = tz1090_gpio_of_match,
626 .probe = tz1090_gpio_probe,
629 static int __init tz1090_gpio_init(void)
631 return platform_driver_register(&tz1090_gpio_driver);
633 subsys_initcall(tz1090_gpio_init);