2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-gpio.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
42 #include <plat/gpio-fns.h>
46 #define gpio_dbg(x...) do { } while (0)
48 #define gpio_dbg(x...) printk(KERN_DEBUG x)
51 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
52 unsigned int off, samsung_gpio_pull_t pull)
54 void __iomem *reg = chip->base + 0x08;
58 pup = __raw_readl(reg);
61 __raw_writel(pup, reg);
66 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
69 void __iomem *reg = chip->base + 0x08;
71 u32 pup = __raw_readl(reg);
76 return (__force samsung_gpio_pull_t)pup;
79 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
80 unsigned int off, samsung_gpio_pull_t pull)
83 case S3C_GPIO_PULL_NONE:
86 case S3C_GPIO_PULL_UP:
89 case S3C_GPIO_PULL_DOWN:
93 return samsung_gpio_setpull_updown(chip, off, pull);
96 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
99 samsung_gpio_pull_t pull;
101 pull = samsung_gpio_getpull_updown(chip, off);
105 pull = S3C_GPIO_PULL_UP;
109 pull = S3C_GPIO_PULL_NONE;
112 pull = S3C_GPIO_PULL_DOWN;
119 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
120 unsigned int off, samsung_gpio_pull_t pull,
121 samsung_gpio_pull_t updown)
123 void __iomem *reg = chip->base + 0x08;
124 u32 pup = __raw_readl(reg);
128 else if (pull == S3C_GPIO_PULL_NONE)
133 __raw_writel(pup, reg);
137 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
139 samsung_gpio_pull_t updown)
141 void __iomem *reg = chip->base + 0x08;
142 u32 pup = __raw_readl(reg);
145 return pup ? S3C_GPIO_PULL_NONE : updown;
148 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
151 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
154 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
155 unsigned int off, samsung_gpio_pull_t pull)
157 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
160 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
163 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
166 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
172 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
173 unsigned int off, samsung_gpio_pull_t pull)
175 if (pull == S3C_GPIO_PULL_UP)
178 return samsung_gpio_setpull_updown(chip, off, pull);
181 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
184 samsung_gpio_pull_t pull;
186 pull = samsung_gpio_getpull_updown(chip, off);
189 pull = S3C_GPIO_PULL_UP;
195 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
196 * @chip: The gpio chip that is being configured.
197 * @off: The offset for the GPIO being configured.
198 * @cfg: The configuration value to set.
200 * This helper deal with the GPIO cases where the control register
201 * has two bits of configuration per gpio, which have the following
205 * 1x = special function
208 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
209 unsigned int off, unsigned int cfg)
211 void __iomem *reg = chip->base;
212 unsigned int shift = off * 2;
215 if (samsung_gpio_is_cfg_special(cfg)) {
223 con = __raw_readl(reg);
224 con &= ~(0x3 << shift);
226 __raw_writel(con, reg);
232 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
233 * @chip: The gpio chip that is being configured.
234 * @off: The offset for the GPIO being configured.
236 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
237 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
238 * S3C_GPIO_SPECIAL() macro.
241 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
246 con = __raw_readl(chip->base);
250 /* this conversion works for IN and OUT as well as special mode */
251 return S3C_GPIO_SPECIAL(con);
255 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
256 * @chip: The gpio chip that is being configured.
257 * @off: The offset for the GPIO being configured.
258 * @cfg: The configuration value to set.
260 * This helper deal with the GPIO cases where the control register has 4 bits
261 * of control per GPIO, generally in the form of:
264 * others = Special functions (dependent on bank)
266 * Note, since the code to deal with the case where there are two control
267 * registers instead of one, we do not have a separate set of functions for
271 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
272 unsigned int off, unsigned int cfg)
274 void __iomem *reg = chip->base;
275 unsigned int shift = (off & 7) * 4;
278 if (off < 8 && chip->chip.ngpio > 8)
281 if (samsung_gpio_is_cfg_special(cfg)) {
286 con = __raw_readl(reg);
287 con &= ~(0xf << shift);
289 __raw_writel(con, reg);
295 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
296 * @chip: The gpio chip that is being configured.
297 * @off: The offset for the GPIO being configured.
299 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
300 * register setting into a value the software can use, such as could be passed
301 * to samsung_gpio_setcfg_4bit().
303 * @sa samsung_gpio_getcfg_2bit
306 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
309 void __iomem *reg = chip->base;
310 unsigned int shift = (off & 7) * 4;
313 if (off < 8 && chip->chip.ngpio > 8)
316 con = __raw_readl(reg);
320 /* this conversion works for IN and OUT as well as special mode */
321 return S3C_GPIO_SPECIAL(con);
324 #ifdef CONFIG_PLAT_S3C24XX
326 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
327 * @chip: The gpio chip that is being configured.
328 * @off: The offset for the GPIO being configured.
329 * @cfg: The configuration value to set.
331 * This helper deal with the GPIO cases where the control register
332 * has one bit of configuration for the gpio, where setting the bit
333 * means the pin is in special function mode and unset means output.
336 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
337 unsigned int off, unsigned int cfg)
339 void __iomem *reg = chip->base;
340 unsigned int shift = off;
343 if (samsung_gpio_is_cfg_special(cfg)) {
346 /* Map output to 0, and SFN2 to 1 */
354 con = __raw_readl(reg);
355 con &= ~(0x1 << shift);
357 __raw_writel(con, reg);
363 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
364 * @chip: The gpio chip that is being configured.
365 * @off: The offset for the GPIO being configured.
367 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
368 * GPIO configuration value.
370 * @sa samsung_gpio_getcfg_2bit
371 * @sa samsung_gpio_getcfg_4bit
374 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
379 con = __raw_readl(chip->base);
384 return S3C_GPIO_SFN(con);
388 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
389 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
390 unsigned int off, unsigned int cfg)
392 void __iomem *reg = chip->base;
403 shift = (off & 7) * 4;
407 shift = ((off + 1) & 7) * 4;
410 shift = ((off + 1) & 7) * 4;
414 if (samsung_gpio_is_cfg_special(cfg)) {
419 con = __raw_readl(reg);
420 con &= ~(0xf << shift);
422 __raw_writel(con, reg);
428 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
431 for (; nr_chips > 0; nr_chips--, chipcfg++) {
432 if (!chipcfg->set_config)
433 chipcfg->set_config = samsung_gpio_setcfg_4bit;
434 if (!chipcfg->get_config)
435 chipcfg->get_config = samsung_gpio_getcfg_4bit;
436 if (!chipcfg->set_pull)
437 chipcfg->set_pull = samsung_gpio_setpull_updown;
438 if (!chipcfg->get_pull)
439 chipcfg->get_pull = samsung_gpio_getpull_updown;
443 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
444 .set_config = samsung_gpio_setcfg_2bit,
445 .get_config = samsung_gpio_getcfg_2bit,
448 #ifdef CONFIG_PLAT_S3C24XX
449 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
450 .set_config = s3c24xx_gpio_setcfg_abank,
451 .get_config = s3c24xx_gpio_getcfg_abank,
455 static struct samsung_gpio_cfg exynos_gpio_cfg = {
456 .set_pull = exynos_gpio_setpull,
457 .get_pull = exynos_gpio_getpull,
458 .set_config = samsung_gpio_setcfg_4bit,
459 .get_config = samsung_gpio_getcfg_4bit,
462 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
463 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
465 .set_config = s5p64x0_gpio_setcfg_rbank,
466 .get_config = samsung_gpio_getcfg_4bit,
467 .set_pull = samsung_gpio_setpull_updown,
468 .get_pull = samsung_gpio_getpull_updown,
472 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
487 .set_config = samsung_gpio_setcfg_2bit,
488 .get_config = samsung_gpio_getcfg_2bit,
492 .set_config = samsung_gpio_setcfg_2bit,
493 .get_config = samsung_gpio_getcfg_2bit,
497 .set_config = samsung_gpio_setcfg_2bit,
498 .get_config = samsung_gpio_getcfg_2bit,
501 .set_config = samsung_gpio_setcfg_2bit,
502 .get_config = samsung_gpio_getcfg_2bit,
505 .set_pull = exynos_gpio_setpull,
506 .get_pull = exynos_gpio_getpull,
510 .set_pull = exynos_gpio_setpull,
511 .get_pull = exynos_gpio_getpull,
516 * Default routines for controlling GPIO, based on the original S3C24XX
517 * GPIO functions which deal with the case where each gpio bank of the
518 * chip is as following:
520 * base + 0x00: Control register, 2 bits per gpio
521 * gpio n: 2 bits starting at (2*n)
522 * 00 = input, 01 = output, others mean special-function
523 * base + 0x04: Data register, 1 bit per gpio
527 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
529 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
530 void __iomem *base = ourchip->base;
534 samsung_gpio_lock(ourchip, flags);
536 con = __raw_readl(base + 0x00);
537 con &= ~(3 << (offset * 2));
539 __raw_writel(con, base + 0x00);
541 samsung_gpio_unlock(ourchip, flags);
545 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
546 unsigned offset, int value)
548 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
549 void __iomem *base = ourchip->base;
554 samsung_gpio_lock(ourchip, flags);
556 dat = __raw_readl(base + 0x04);
557 dat &= ~(1 << offset);
560 __raw_writel(dat, base + 0x04);
562 con = __raw_readl(base + 0x00);
563 con &= ~(3 << (offset * 2));
564 con |= 1 << (offset * 2);
566 __raw_writel(con, base + 0x00);
567 __raw_writel(dat, base + 0x04);
569 samsung_gpio_unlock(ourchip, flags);
574 * The samsung_gpiolib_4bit routines are to control the gpio banks where
575 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
578 * base + 0x00: Control register, 4 bits per gpio
579 * gpio n: 4 bits starting at (4*n)
580 * 0000 = input, 0001 = output, others mean special-function
581 * base + 0x04: Data register, 1 bit per gpio
584 * Note, since the data register is one bit per gpio and is at base + 0x4
585 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
586 * state of the output.
589 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
592 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
593 void __iomem *base = ourchip->base;
596 con = __raw_readl(base + GPIOCON_OFF);
597 con &= ~(0xf << con_4bit_shift(offset));
598 __raw_writel(con, base + GPIOCON_OFF);
600 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
605 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
606 unsigned int offset, int value)
608 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
609 void __iomem *base = ourchip->base;
613 con = __raw_readl(base + GPIOCON_OFF);
614 con &= ~(0xf << con_4bit_shift(offset));
615 con |= 0x1 << con_4bit_shift(offset);
617 dat = __raw_readl(base + GPIODAT_OFF);
622 dat &= ~(1 << offset);
624 __raw_writel(dat, base + GPIODAT_OFF);
625 __raw_writel(con, base + GPIOCON_OFF);
626 __raw_writel(dat, base + GPIODAT_OFF);
628 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
634 * The next set of routines are for the case where the GPIO configuration
635 * registers are 4 bits per GPIO but there is more than one register (the
636 * bank has more than 8 GPIOs.
638 * This case is the similar to the 4 bit case, but the registers are as
641 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
645 * gpio n: 4 bits starting at (4*n)
646 * 0000 = input, 0001 = output, others mean special-function
647 * base + 0x08: Data register, 1 bit per gpio
650 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
651 * routines we store the 'base + 0x4' address so that these routines see
652 * the data register at ourchip->base + 0x04.
655 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
658 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
659 void __iomem *base = ourchip->base;
660 void __iomem *regcon = base;
668 con = __raw_readl(regcon);
669 con &= ~(0xf << con_4bit_shift(offset));
670 __raw_writel(con, regcon);
672 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
677 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
678 unsigned int offset, int value)
680 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
681 void __iomem *base = ourchip->base;
682 void __iomem *regcon = base;
685 unsigned con_offset = offset;
692 con = __raw_readl(regcon);
693 con &= ~(0xf << con_4bit_shift(con_offset));
694 con |= 0x1 << con_4bit_shift(con_offset);
696 dat = __raw_readl(base + GPIODAT_OFF);
701 dat &= ~(1 << offset);
703 __raw_writel(dat, base + GPIODAT_OFF);
704 __raw_writel(con, regcon);
705 __raw_writel(dat, base + GPIODAT_OFF);
707 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
712 #ifdef CONFIG_PLAT_S3C24XX
713 /* The next set of routines are for the case of s3c24xx bank a */
715 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
720 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
721 unsigned offset, int value)
723 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
724 void __iomem *base = ourchip->base;
729 local_irq_save(flags);
731 con = __raw_readl(base + 0x00);
732 dat = __raw_readl(base + 0x04);
734 dat &= ~(1 << offset);
738 __raw_writel(dat, base + 0x04);
740 con &= ~(1 << offset);
742 __raw_writel(con, base + 0x00);
743 __raw_writel(dat, base + 0x04);
745 local_irq_restore(flags);
750 /* The next set of routines are for the case of s5p64x0 bank r */
752 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
755 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
756 void __iomem *base = ourchip->base;
757 void __iomem *regcon = base;
777 samsung_gpio_lock(ourchip, flags);
779 con = __raw_readl(regcon);
780 con &= ~(0xf << con_4bit_shift(offset));
781 __raw_writel(con, regcon);
783 samsung_gpio_unlock(ourchip, flags);
788 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
789 unsigned int offset, int value)
791 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
792 void __iomem *base = ourchip->base;
793 void __iomem *regcon = base;
797 unsigned con_offset = offset;
799 switch (con_offset) {
815 samsung_gpio_lock(ourchip, flags);
817 con = __raw_readl(regcon);
818 con &= ~(0xf << con_4bit_shift(con_offset));
819 con |= 0x1 << con_4bit_shift(con_offset);
821 dat = __raw_readl(base + GPIODAT_OFF);
825 dat &= ~(1 << offset);
827 __raw_writel(con, regcon);
828 __raw_writel(dat, base + GPIODAT_OFF);
830 samsung_gpio_unlock(ourchip, flags);
835 static void samsung_gpiolib_set(struct gpio_chip *chip,
836 unsigned offset, int value)
838 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
839 void __iomem *base = ourchip->base;
843 samsung_gpio_lock(ourchip, flags);
845 dat = __raw_readl(base + 0x04);
846 dat &= ~(1 << offset);
849 __raw_writel(dat, base + 0x04);
851 samsung_gpio_unlock(ourchip, flags);
854 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
856 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
859 val = __raw_readl(ourchip->base + 0x04);
867 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
868 * for use with the configuration calls, and other parts of the s3c gpiolib
871 * Not all s3c support code will need this, as some configurations of cpu
872 * may only support one or two different configuration options and have an
873 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
874 * the machine support file should provide its own samsung_gpiolib_getchip()
875 * and any other necessary functions.
878 #ifdef CONFIG_S3C_GPIO_TRACK
879 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
881 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
886 gpn = chip->chip.base;
887 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
888 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
889 s3c_gpios[gpn] = chip;
892 #endif /* CONFIG_S3C_GPIO_TRACK */
895 * samsung_gpiolib_add() - add the Samsung gpio_chip.
896 * @chip: The chip to register
898 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
899 * information and makes the necessary alterations for the platform and
900 * notes the information for use with the configuration systems and any
901 * other parts of the system.
904 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
906 struct gpio_chip *gc = &chip->chip;
913 spin_lock_init(&chip->lock);
915 if (!gc->direction_input)
916 gc->direction_input = samsung_gpiolib_2bit_input;
917 if (!gc->direction_output)
918 gc->direction_output = samsung_gpiolib_2bit_output;
920 gc->set = samsung_gpiolib_set;
922 gc->get = samsung_gpiolib_get;
925 if (chip->pm != NULL) {
926 if (!chip->pm->save || !chip->pm->resume)
927 printk(KERN_ERR "gpio: %s has missing PM functions\n",
930 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
933 /* gpiochip_add() prints own failure message on error. */
934 ret = gpiochip_add(gc);
936 s3c_gpiolib_track(chip);
939 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
940 int nr_chips, void __iomem *base)
943 struct gpio_chip *gc = &chip->chip;
945 for (i = 0 ; i < nr_chips; i++, chip++) {
946 /* skip banks not present on SoC */
947 if (chip->chip.base >= S3C_GPIO_END)
951 chip->config = &s3c24xx_gpiocfg_default;
953 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
954 if ((base != NULL) && (chip->base == NULL))
955 chip->base = base + ((i) * 0x10);
957 if (!gc->direction_input)
958 gc->direction_input = samsung_gpiolib_2bit_input;
959 if (!gc->direction_output)
960 gc->direction_output = samsung_gpiolib_2bit_output;
962 samsung_gpiolib_add(chip);
966 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
967 int nr_chips, void __iomem *base,
972 for (i = 0 ; i < nr_chips; i++, chip++) {
973 chip->chip.direction_input = samsung_gpiolib_2bit_input;
974 chip->chip.direction_output = samsung_gpiolib_2bit_output;
977 chip->config = &samsung_gpio_cfgs[7];
979 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
980 if ((base != NULL) && (chip->base == NULL))
981 chip->base = base + ((i) * offset);
983 samsung_gpiolib_add(chip);
988 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
989 * @chip: The gpio chip that is being configured.
990 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
992 * This helper deal with the GPIO cases where the control register has 4 bits
993 * of control per GPIO, generally in the form of:
996 * others = Special functions (dependent on bank)
998 * Note, since the code to deal with the case where there are two control
999 * registers instead of one, we do not have a separate set of function
1000 * (samsung_gpiolib_add_4bit2_chips)for each case.
1003 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1004 int nr_chips, void __iomem *base)
1008 for (i = 0 ; i < nr_chips; i++, chip++) {
1009 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1010 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1013 chip->config = &samsung_gpio_cfgs[2];
1015 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1016 if ((base != NULL) && (chip->base == NULL))
1017 chip->base = base + ((i) * 0x20);
1019 samsung_gpiolib_add(chip);
1023 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1026 for (; nr_chips > 0; nr_chips--, chip++) {
1027 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1028 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1031 chip->config = &samsung_gpio_cfgs[2];
1033 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1035 samsung_gpiolib_add(chip);
1039 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1042 for (; nr_chips > 0; nr_chips--, chip++) {
1043 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1044 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1047 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1049 samsung_gpiolib_add(chip);
1053 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1055 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1057 return samsung_chip->irq_base + offset;
1060 #ifdef CONFIG_PLAT_S3C24XX
1061 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1064 return IRQ_EINT0 + offset;
1067 return IRQ_EINT4 + offset - 4;
1073 #ifdef CONFIG_PLAT_S3C64XX
1074 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1076 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1079 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1081 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1085 struct samsung_gpio_chip s3c24xx_gpios[] = {
1086 #ifdef CONFIG_PLAT_S3C24XX
1088 .config = &s3c24xx_gpiocfg_banka,
1090 .base = S3C2410_GPA(0),
1091 .owner = THIS_MODULE,
1094 .direction_input = s3c24xx_gpiolib_banka_input,
1095 .direction_output = s3c24xx_gpiolib_banka_output,
1099 .base = S3C2410_GPB(0),
1100 .owner = THIS_MODULE,
1106 .base = S3C2410_GPC(0),
1107 .owner = THIS_MODULE,
1113 .base = S3C2410_GPD(0),
1114 .owner = THIS_MODULE,
1120 .base = S3C2410_GPE(0),
1122 .owner = THIS_MODULE,
1127 .base = S3C2410_GPF(0),
1128 .owner = THIS_MODULE,
1131 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1134 .irq_base = IRQ_EINT8,
1136 .base = S3C2410_GPG(0),
1137 .owner = THIS_MODULE,
1140 .to_irq = samsung_gpiolib_to_irq,
1144 .base = S3C2410_GPH(0),
1145 .owner = THIS_MODULE,
1150 /* GPIOS for the S3C2443 and later devices. */
1152 .base = S3C2440_GPJCON,
1154 .base = S3C2410_GPJ(0),
1155 .owner = THIS_MODULE,
1160 .base = S3C2443_GPKCON,
1162 .base = S3C2410_GPK(0),
1163 .owner = THIS_MODULE,
1168 .base = S3C2443_GPLCON,
1170 .base = S3C2410_GPL(0),
1171 .owner = THIS_MODULE,
1176 .base = S3C2443_GPMCON,
1178 .base = S3C2410_GPM(0),
1179 .owner = THIS_MODULE,
1188 * GPIO bank summary:
1190 * Bank GPIOs Style SlpCon ExtInt Group
1196 * F 16 2Bit Yes 4 [1]
1198 * H 10 4Bit[2] Yes 6
1199 * I 16 2Bit Yes None
1200 * J 12 2Bit Yes None
1201 * K 16 4Bit[2] No None
1202 * L 15 4Bit[2] No None
1203 * M 6 4Bit No IRQ_EINT
1204 * N 16 2Bit No IRQ_EINT
1209 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1210 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1213 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1214 #ifdef CONFIG_PLAT_S3C64XX
1217 .base = S3C64XX_GPA(0),
1218 .ngpio = S3C64XX_GPIO_A_NR,
1223 .base = S3C64XX_GPB(0),
1224 .ngpio = S3C64XX_GPIO_B_NR,
1229 .base = S3C64XX_GPC(0),
1230 .ngpio = S3C64XX_GPIO_C_NR,
1235 .base = S3C64XX_GPD(0),
1236 .ngpio = S3C64XX_GPIO_D_NR,
1240 .config = &samsung_gpio_cfgs[0],
1242 .base = S3C64XX_GPE(0),
1243 .ngpio = S3C64XX_GPIO_E_NR,
1247 .base = S3C64XX_GPG_BASE,
1249 .base = S3C64XX_GPG(0),
1250 .ngpio = S3C64XX_GPIO_G_NR,
1254 .base = S3C64XX_GPM_BASE,
1255 .config = &samsung_gpio_cfgs[1],
1257 .base = S3C64XX_GPM(0),
1258 .ngpio = S3C64XX_GPIO_M_NR,
1260 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1266 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1267 #ifdef CONFIG_PLAT_S3C64XX
1269 .base = S3C64XX_GPH_BASE + 0x4,
1271 .base = S3C64XX_GPH(0),
1272 .ngpio = S3C64XX_GPIO_H_NR,
1276 .base = S3C64XX_GPK_BASE + 0x4,
1277 .config = &samsung_gpio_cfgs[0],
1279 .base = S3C64XX_GPK(0),
1280 .ngpio = S3C64XX_GPIO_K_NR,
1284 .base = S3C64XX_GPL_BASE + 0x4,
1285 .config = &samsung_gpio_cfgs[1],
1287 .base = S3C64XX_GPL(0),
1288 .ngpio = S3C64XX_GPIO_L_NR,
1290 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1296 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1297 #ifdef CONFIG_PLAT_S3C64XX
1299 .base = S3C64XX_GPF_BASE,
1300 .config = &samsung_gpio_cfgs[6],
1302 .base = S3C64XX_GPF(0),
1303 .ngpio = S3C64XX_GPIO_F_NR,
1307 .config = &samsung_gpio_cfgs[7],
1309 .base = S3C64XX_GPI(0),
1310 .ngpio = S3C64XX_GPIO_I_NR,
1314 .config = &samsung_gpio_cfgs[7],
1316 .base = S3C64XX_GPJ(0),
1317 .ngpio = S3C64XX_GPIO_J_NR,
1321 .config = &samsung_gpio_cfgs[6],
1323 .base = S3C64XX_GPO(0),
1324 .ngpio = S3C64XX_GPIO_O_NR,
1328 .config = &samsung_gpio_cfgs[6],
1330 .base = S3C64XX_GPP(0),
1331 .ngpio = S3C64XX_GPIO_P_NR,
1335 .config = &samsung_gpio_cfgs[6],
1337 .base = S3C64XX_GPQ(0),
1338 .ngpio = S3C64XX_GPIO_Q_NR,
1342 .base = S3C64XX_GPN_BASE,
1343 .irq_base = IRQ_EINT(0),
1344 .config = &samsung_gpio_cfgs[5],
1346 .base = S3C64XX_GPN(0),
1347 .ngpio = S3C64XX_GPIO_N_NR,
1349 .to_irq = samsung_gpiolib_to_irq,
1356 * S5P6440 GPIO bank summary:
1358 * Bank GPIOs Style SlpCon ExtInt Group
1362 * F 2 2Bit Yes 4 [1]
1364 * H 10 4Bit[2] Yes 6
1365 * I 16 2Bit Yes None
1366 * J 12 2Bit Yes None
1367 * N 16 2Bit No IRQ_EINT
1369 * R 15 4Bit[2] Yes 8
1372 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1373 #ifdef CONFIG_CPU_S5P6440
1376 .base = S5P6440_GPA(0),
1377 .ngpio = S5P6440_GPIO_A_NR,
1382 .base = S5P6440_GPB(0),
1383 .ngpio = S5P6440_GPIO_B_NR,
1388 .base = S5P6440_GPC(0),
1389 .ngpio = S5P6440_GPIO_C_NR,
1393 .base = S5P64X0_GPG_BASE,
1395 .base = S5P6440_GPG(0),
1396 .ngpio = S5P6440_GPIO_G_NR,
1403 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1404 #ifdef CONFIG_CPU_S5P6440
1406 .base = S5P64X0_GPH_BASE + 0x4,
1408 .base = S5P6440_GPH(0),
1409 .ngpio = S5P6440_GPIO_H_NR,
1416 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1417 #ifdef CONFIG_CPU_S5P6440
1419 .base = S5P64X0_GPR_BASE + 0x4,
1420 .config = &s5p64x0_gpio_cfg_rbank,
1422 .base = S5P6440_GPR(0),
1423 .ngpio = S5P6440_GPIO_R_NR,
1430 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1431 #ifdef CONFIG_CPU_S5P6440
1433 .base = S5P64X0_GPF_BASE,
1434 .config = &samsung_gpio_cfgs[6],
1436 .base = S5P6440_GPF(0),
1437 .ngpio = S5P6440_GPIO_F_NR,
1441 .base = S5P64X0_GPI_BASE,
1442 .config = &samsung_gpio_cfgs[4],
1444 .base = S5P6440_GPI(0),
1445 .ngpio = S5P6440_GPIO_I_NR,
1449 .base = S5P64X0_GPJ_BASE,
1450 .config = &samsung_gpio_cfgs[4],
1452 .base = S5P6440_GPJ(0),
1453 .ngpio = S5P6440_GPIO_J_NR,
1457 .base = S5P64X0_GPN_BASE,
1458 .config = &samsung_gpio_cfgs[5],
1460 .base = S5P6440_GPN(0),
1461 .ngpio = S5P6440_GPIO_N_NR,
1465 .base = S5P64X0_GPP_BASE,
1466 .config = &samsung_gpio_cfgs[6],
1468 .base = S5P6440_GPP(0),
1469 .ngpio = S5P6440_GPIO_P_NR,
1477 * S5P6450 GPIO bank summary:
1479 * Bank GPIOs Style SlpCon ExtInt Group
1485 * G 14 4Bit[2] Yes 5
1486 * H 10 4Bit[2] Yes 6
1487 * I 16 2Bit Yes None
1488 * J 12 2Bit Yes None
1490 * N 16 2Bit No IRQ_EINT
1492 * Q 14 2Bit Yes None
1493 * R 15 4Bit[2] Yes None
1496 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1497 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1500 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1501 #ifdef CONFIG_CPU_S5P6450
1504 .base = S5P6450_GPA(0),
1505 .ngpio = S5P6450_GPIO_A_NR,
1510 .base = S5P6450_GPB(0),
1511 .ngpio = S5P6450_GPIO_B_NR,
1516 .base = S5P6450_GPC(0),
1517 .ngpio = S5P6450_GPIO_C_NR,
1522 .base = S5P6450_GPD(0),
1523 .ngpio = S5P6450_GPIO_D_NR,
1527 .base = S5P6450_GPK_BASE,
1529 .base = S5P6450_GPK(0),
1530 .ngpio = S5P6450_GPIO_K_NR,
1537 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1538 #ifdef CONFIG_CPU_S5P6450
1540 .base = S5P64X0_GPG_BASE + 0x4,
1542 .base = S5P6450_GPG(0),
1543 .ngpio = S5P6450_GPIO_G_NR,
1547 .base = S5P64X0_GPH_BASE + 0x4,
1549 .base = S5P6450_GPH(0),
1550 .ngpio = S5P6450_GPIO_H_NR,
1557 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1558 #ifdef CONFIG_CPU_S5P6450
1560 .base = S5P64X0_GPR_BASE + 0x4,
1561 .config = &s5p64x0_gpio_cfg_rbank,
1563 .base = S5P6450_GPR(0),
1564 .ngpio = S5P6450_GPIO_R_NR,
1571 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1572 #ifdef CONFIG_CPU_S5P6450
1574 .base = S5P64X0_GPF_BASE,
1575 .config = &samsung_gpio_cfgs[6],
1577 .base = S5P6450_GPF(0),
1578 .ngpio = S5P6450_GPIO_F_NR,
1582 .base = S5P64X0_GPI_BASE,
1583 .config = &samsung_gpio_cfgs[4],
1585 .base = S5P6450_GPI(0),
1586 .ngpio = S5P6450_GPIO_I_NR,
1590 .base = S5P64X0_GPJ_BASE,
1591 .config = &samsung_gpio_cfgs[4],
1593 .base = S5P6450_GPJ(0),
1594 .ngpio = S5P6450_GPIO_J_NR,
1598 .base = S5P64X0_GPN_BASE,
1599 .config = &samsung_gpio_cfgs[5],
1601 .base = S5P6450_GPN(0),
1602 .ngpio = S5P6450_GPIO_N_NR,
1606 .base = S5P64X0_GPP_BASE,
1607 .config = &samsung_gpio_cfgs[6],
1609 .base = S5P6450_GPP(0),
1610 .ngpio = S5P6450_GPIO_P_NR,
1614 .base = S5P6450_GPQ_BASE,
1615 .config = &samsung_gpio_cfgs[5],
1617 .base = S5P6450_GPQ(0),
1618 .ngpio = S5P6450_GPIO_Q_NR,
1622 .base = S5P6450_GPS_BASE,
1623 .config = &samsung_gpio_cfgs[6],
1625 .base = S5P6450_GPS(0),
1626 .ngpio = S5P6450_GPIO_S_NR,
1634 * S5PC100 GPIO bank summary:
1636 * Bank GPIOs Style INT Type
1637 * A0 8 4Bit GPIO_INT0
1638 * A1 5 4Bit GPIO_INT1
1639 * B 8 4Bit GPIO_INT2
1640 * C 5 4Bit GPIO_INT3
1641 * D 7 4Bit GPIO_INT4
1642 * E0 8 4Bit GPIO_INT5
1643 * E1 6 4Bit GPIO_INT6
1644 * F0 8 4Bit GPIO_INT7
1645 * F1 8 4Bit GPIO_INT8
1646 * F2 8 4Bit GPIO_INT9
1647 * F3 4 4Bit GPIO_INT10
1648 * G0 8 4Bit GPIO_INT11
1649 * G1 3 4Bit GPIO_INT12
1650 * G2 7 4Bit GPIO_INT13
1651 * G3 7 4Bit GPIO_INT14
1652 * H0 8 4Bit WKUP_INT
1653 * H1 8 4Bit WKUP_INT
1654 * H2 8 4Bit WKUP_INT
1655 * H3 8 4Bit WKUP_INT
1656 * I 8 4Bit GPIO_INT15
1657 * J0 8 4Bit GPIO_INT16
1658 * J1 5 4Bit GPIO_INT17
1659 * J2 8 4Bit GPIO_INT18
1660 * J3 8 4Bit GPIO_INT19
1661 * J4 4 4Bit GPIO_INT20
1672 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1673 #ifdef CONFIG_CPU_S5PC100
1676 .base = S5PC100_GPA0(0),
1677 .ngpio = S5PC100_GPIO_A0_NR,
1682 .base = S5PC100_GPA1(0),
1683 .ngpio = S5PC100_GPIO_A1_NR,
1688 .base = S5PC100_GPB(0),
1689 .ngpio = S5PC100_GPIO_B_NR,
1694 .base = S5PC100_GPC(0),
1695 .ngpio = S5PC100_GPIO_C_NR,
1700 .base = S5PC100_GPD(0),
1701 .ngpio = S5PC100_GPIO_D_NR,
1706 .base = S5PC100_GPE0(0),
1707 .ngpio = S5PC100_GPIO_E0_NR,
1712 .base = S5PC100_GPE1(0),
1713 .ngpio = S5PC100_GPIO_E1_NR,
1718 .base = S5PC100_GPF0(0),
1719 .ngpio = S5PC100_GPIO_F0_NR,
1724 .base = S5PC100_GPF1(0),
1725 .ngpio = S5PC100_GPIO_F1_NR,
1730 .base = S5PC100_GPF2(0),
1731 .ngpio = S5PC100_GPIO_F2_NR,
1736 .base = S5PC100_GPF3(0),
1737 .ngpio = S5PC100_GPIO_F3_NR,
1742 .base = S5PC100_GPG0(0),
1743 .ngpio = S5PC100_GPIO_G0_NR,
1748 .base = S5PC100_GPG1(0),
1749 .ngpio = S5PC100_GPIO_G1_NR,
1754 .base = S5PC100_GPG2(0),
1755 .ngpio = S5PC100_GPIO_G2_NR,
1760 .base = S5PC100_GPG3(0),
1761 .ngpio = S5PC100_GPIO_G3_NR,
1766 .base = S5PC100_GPI(0),
1767 .ngpio = S5PC100_GPIO_I_NR,
1772 .base = S5PC100_GPJ0(0),
1773 .ngpio = S5PC100_GPIO_J0_NR,
1778 .base = S5PC100_GPJ1(0),
1779 .ngpio = S5PC100_GPIO_J1_NR,
1784 .base = S5PC100_GPJ2(0),
1785 .ngpio = S5PC100_GPIO_J2_NR,
1790 .base = S5PC100_GPJ3(0),
1791 .ngpio = S5PC100_GPIO_J3_NR,
1796 .base = S5PC100_GPJ4(0),
1797 .ngpio = S5PC100_GPIO_J4_NR,
1802 .base = S5PC100_GPK0(0),
1803 .ngpio = S5PC100_GPIO_K0_NR,
1808 .base = S5PC100_GPK1(0),
1809 .ngpio = S5PC100_GPIO_K1_NR,
1814 .base = S5PC100_GPK2(0),
1815 .ngpio = S5PC100_GPIO_K2_NR,
1820 .base = S5PC100_GPK3(0),
1821 .ngpio = S5PC100_GPIO_K3_NR,
1826 .base = S5PC100_GPL0(0),
1827 .ngpio = S5PC100_GPIO_L0_NR,
1832 .base = S5PC100_GPL1(0),
1833 .ngpio = S5PC100_GPIO_L1_NR,
1838 .base = S5PC100_GPL2(0),
1839 .ngpio = S5PC100_GPIO_L2_NR,
1844 .base = S5PC100_GPL3(0),
1845 .ngpio = S5PC100_GPIO_L3_NR,
1850 .base = S5PC100_GPL4(0),
1851 .ngpio = S5PC100_GPIO_L4_NR,
1855 .base = (S5P_VA_GPIO + 0xC00),
1856 .irq_base = IRQ_EINT(0),
1858 .base = S5PC100_GPH0(0),
1859 .ngpio = S5PC100_GPIO_H0_NR,
1861 .to_irq = samsung_gpiolib_to_irq,
1864 .base = (S5P_VA_GPIO + 0xC20),
1865 .irq_base = IRQ_EINT(8),
1867 .base = S5PC100_GPH1(0),
1868 .ngpio = S5PC100_GPIO_H1_NR,
1870 .to_irq = samsung_gpiolib_to_irq,
1873 .base = (S5P_VA_GPIO + 0xC40),
1874 .irq_base = IRQ_EINT(16),
1876 .base = S5PC100_GPH2(0),
1877 .ngpio = S5PC100_GPIO_H2_NR,
1879 .to_irq = samsung_gpiolib_to_irq,
1882 .base = (S5P_VA_GPIO + 0xC60),
1883 .irq_base = IRQ_EINT(24),
1885 .base = S5PC100_GPH3(0),
1886 .ngpio = S5PC100_GPIO_H3_NR,
1888 .to_irq = samsung_gpiolib_to_irq,
1895 * Followings are the gpio banks in S5PV210/S5PC110
1897 * The 'config' member when left to NULL, is initialized to the default
1898 * structure samsung_gpio_cfgs[3] in the init function below.
1900 * The 'base' member is also initialized in the init function below.
1901 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1902 * uses the above macro and depends on the banks being listed in order here.
1905 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1906 #ifdef CONFIG_CPU_S5PV210
1909 .base = S5PV210_GPA0(0),
1910 .ngpio = S5PV210_GPIO_A0_NR,
1915 .base = S5PV210_GPA1(0),
1916 .ngpio = S5PV210_GPIO_A1_NR,
1921 .base = S5PV210_GPB(0),
1922 .ngpio = S5PV210_GPIO_B_NR,
1927 .base = S5PV210_GPC0(0),
1928 .ngpio = S5PV210_GPIO_C0_NR,
1933 .base = S5PV210_GPC1(0),
1934 .ngpio = S5PV210_GPIO_C1_NR,
1939 .base = S5PV210_GPD0(0),
1940 .ngpio = S5PV210_GPIO_D0_NR,
1945 .base = S5PV210_GPD1(0),
1946 .ngpio = S5PV210_GPIO_D1_NR,
1951 .base = S5PV210_GPE0(0),
1952 .ngpio = S5PV210_GPIO_E0_NR,
1957 .base = S5PV210_GPE1(0),
1958 .ngpio = S5PV210_GPIO_E1_NR,
1963 .base = S5PV210_GPF0(0),
1964 .ngpio = S5PV210_GPIO_F0_NR,
1969 .base = S5PV210_GPF1(0),
1970 .ngpio = S5PV210_GPIO_F1_NR,
1975 .base = S5PV210_GPF2(0),
1976 .ngpio = S5PV210_GPIO_F2_NR,
1981 .base = S5PV210_GPF3(0),
1982 .ngpio = S5PV210_GPIO_F3_NR,
1987 .base = S5PV210_GPG0(0),
1988 .ngpio = S5PV210_GPIO_G0_NR,
1993 .base = S5PV210_GPG1(0),
1994 .ngpio = S5PV210_GPIO_G1_NR,
1999 .base = S5PV210_GPG2(0),
2000 .ngpio = S5PV210_GPIO_G2_NR,
2005 .base = S5PV210_GPG3(0),
2006 .ngpio = S5PV210_GPIO_G3_NR,
2011 .base = S5PV210_GPI(0),
2012 .ngpio = S5PV210_GPIO_I_NR,
2017 .base = S5PV210_GPJ0(0),
2018 .ngpio = S5PV210_GPIO_J0_NR,
2023 .base = S5PV210_GPJ1(0),
2024 .ngpio = S5PV210_GPIO_J1_NR,
2029 .base = S5PV210_GPJ2(0),
2030 .ngpio = S5PV210_GPIO_J2_NR,
2035 .base = S5PV210_GPJ3(0),
2036 .ngpio = S5PV210_GPIO_J3_NR,
2041 .base = S5PV210_GPJ4(0),
2042 .ngpio = S5PV210_GPIO_J4_NR,
2047 .base = S5PV210_MP01(0),
2048 .ngpio = S5PV210_GPIO_MP01_NR,
2053 .base = S5PV210_MP02(0),
2054 .ngpio = S5PV210_GPIO_MP02_NR,
2059 .base = S5PV210_MP03(0),
2060 .ngpio = S5PV210_GPIO_MP03_NR,
2065 .base = S5PV210_MP04(0),
2066 .ngpio = S5PV210_GPIO_MP04_NR,
2071 .base = S5PV210_MP05(0),
2072 .ngpio = S5PV210_GPIO_MP05_NR,
2076 .base = (S5P_VA_GPIO + 0xC00),
2077 .irq_base = IRQ_EINT(0),
2079 .base = S5PV210_GPH0(0),
2080 .ngpio = S5PV210_GPIO_H0_NR,
2082 .to_irq = samsung_gpiolib_to_irq,
2085 .base = (S5P_VA_GPIO + 0xC20),
2086 .irq_base = IRQ_EINT(8),
2088 .base = S5PV210_GPH1(0),
2089 .ngpio = S5PV210_GPIO_H1_NR,
2091 .to_irq = samsung_gpiolib_to_irq,
2094 .base = (S5P_VA_GPIO + 0xC40),
2095 .irq_base = IRQ_EINT(16),
2097 .base = S5PV210_GPH2(0),
2098 .ngpio = S5PV210_GPIO_H2_NR,
2100 .to_irq = samsung_gpiolib_to_irq,
2103 .base = (S5P_VA_GPIO + 0xC60),
2104 .irq_base = IRQ_EINT(24),
2106 .base = S5PV210_GPH3(0),
2107 .ngpio = S5PV210_GPIO_H3_NR,
2109 .to_irq = samsung_gpiolib_to_irq,
2116 * Followings are the gpio banks in EXYNOS SoCs
2118 * The 'config' member when left to NULL, is initialized to the default
2119 * structure exynos_gpio_cfg in the init function below.
2121 * The 'base' member is also initialized in the init function below.
2122 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2123 * uses the above macro and depends on the banks being listed in order here.
2126 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2127 #ifdef CONFIG_ARCH_EXYNOS4
2130 .base = EXYNOS4_GPA0(0),
2131 .ngpio = EXYNOS4_GPIO_A0_NR,
2136 .base = EXYNOS4_GPA1(0),
2137 .ngpio = EXYNOS4_GPIO_A1_NR,
2142 .base = EXYNOS4_GPB(0),
2143 .ngpio = EXYNOS4_GPIO_B_NR,
2148 .base = EXYNOS4_GPC0(0),
2149 .ngpio = EXYNOS4_GPIO_C0_NR,
2154 .base = EXYNOS4_GPC1(0),
2155 .ngpio = EXYNOS4_GPIO_C1_NR,
2160 .base = EXYNOS4_GPD0(0),
2161 .ngpio = EXYNOS4_GPIO_D0_NR,
2166 .base = EXYNOS4_GPD1(0),
2167 .ngpio = EXYNOS4_GPIO_D1_NR,
2172 .base = EXYNOS4_GPE0(0),
2173 .ngpio = EXYNOS4_GPIO_E0_NR,
2178 .base = EXYNOS4_GPE1(0),
2179 .ngpio = EXYNOS4_GPIO_E1_NR,
2184 .base = EXYNOS4_GPE2(0),
2185 .ngpio = EXYNOS4_GPIO_E2_NR,
2190 .base = EXYNOS4_GPE3(0),
2191 .ngpio = EXYNOS4_GPIO_E3_NR,
2196 .base = EXYNOS4_GPE4(0),
2197 .ngpio = EXYNOS4_GPIO_E4_NR,
2202 .base = EXYNOS4_GPF0(0),
2203 .ngpio = EXYNOS4_GPIO_F0_NR,
2208 .base = EXYNOS4_GPF1(0),
2209 .ngpio = EXYNOS4_GPIO_F1_NR,
2214 .base = EXYNOS4_GPF2(0),
2215 .ngpio = EXYNOS4_GPIO_F2_NR,
2220 .base = EXYNOS4_GPF3(0),
2221 .ngpio = EXYNOS4_GPIO_F3_NR,
2228 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2229 #ifdef CONFIG_ARCH_EXYNOS4
2232 .base = EXYNOS4_GPJ0(0),
2233 .ngpio = EXYNOS4_GPIO_J0_NR,
2238 .base = EXYNOS4_GPJ1(0),
2239 .ngpio = EXYNOS4_GPIO_J1_NR,
2244 .base = EXYNOS4_GPK0(0),
2245 .ngpio = EXYNOS4_GPIO_K0_NR,
2250 .base = EXYNOS4_GPK1(0),
2251 .ngpio = EXYNOS4_GPIO_K1_NR,
2256 .base = EXYNOS4_GPK2(0),
2257 .ngpio = EXYNOS4_GPIO_K2_NR,
2262 .base = EXYNOS4_GPK3(0),
2263 .ngpio = EXYNOS4_GPIO_K3_NR,
2268 .base = EXYNOS4_GPL0(0),
2269 .ngpio = EXYNOS4_GPIO_L0_NR,
2274 .base = EXYNOS4_GPL1(0),
2275 .ngpio = EXYNOS4_GPIO_L1_NR,
2280 .base = EXYNOS4_GPL2(0),
2281 .ngpio = EXYNOS4_GPIO_L2_NR,
2285 .config = &samsung_gpio_cfgs[8],
2287 .base = EXYNOS4_GPY0(0),
2288 .ngpio = EXYNOS4_GPIO_Y0_NR,
2292 .config = &samsung_gpio_cfgs[8],
2294 .base = EXYNOS4_GPY1(0),
2295 .ngpio = EXYNOS4_GPIO_Y1_NR,
2299 .config = &samsung_gpio_cfgs[8],
2301 .base = EXYNOS4_GPY2(0),
2302 .ngpio = EXYNOS4_GPIO_Y2_NR,
2306 .config = &samsung_gpio_cfgs[8],
2308 .base = EXYNOS4_GPY3(0),
2309 .ngpio = EXYNOS4_GPIO_Y3_NR,
2313 .config = &samsung_gpio_cfgs[8],
2315 .base = EXYNOS4_GPY4(0),
2316 .ngpio = EXYNOS4_GPIO_Y4_NR,
2320 .config = &samsung_gpio_cfgs[8],
2322 .base = EXYNOS4_GPY5(0),
2323 .ngpio = EXYNOS4_GPIO_Y5_NR,
2327 .config = &samsung_gpio_cfgs[8],
2329 .base = EXYNOS4_GPY6(0),
2330 .ngpio = EXYNOS4_GPIO_Y6_NR,
2334 .config = &samsung_gpio_cfgs[9],
2335 .irq_base = IRQ_EINT(0),
2337 .base = EXYNOS4_GPX0(0),
2338 .ngpio = EXYNOS4_GPIO_X0_NR,
2340 .to_irq = samsung_gpiolib_to_irq,
2343 .config = &samsung_gpio_cfgs[9],
2344 .irq_base = IRQ_EINT(8),
2346 .base = EXYNOS4_GPX1(0),
2347 .ngpio = EXYNOS4_GPIO_X1_NR,
2349 .to_irq = samsung_gpiolib_to_irq,
2352 .config = &samsung_gpio_cfgs[9],
2353 .irq_base = IRQ_EINT(16),
2355 .base = EXYNOS4_GPX2(0),
2356 .ngpio = EXYNOS4_GPIO_X2_NR,
2358 .to_irq = samsung_gpiolib_to_irq,
2361 .config = &samsung_gpio_cfgs[9],
2362 .irq_base = IRQ_EINT(24),
2364 .base = EXYNOS4_GPX3(0),
2365 .ngpio = EXYNOS4_GPIO_X3_NR,
2367 .to_irq = samsung_gpiolib_to_irq,
2373 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2374 #ifdef CONFIG_ARCH_EXYNOS4
2377 .base = EXYNOS4_GPZ(0),
2378 .ngpio = EXYNOS4_GPIO_Z_NR,
2385 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2386 #ifdef CONFIG_ARCH_EXYNOS5
2389 .base = EXYNOS5_GPA0(0),
2390 .ngpio = EXYNOS5_GPIO_A0_NR,
2395 .base = EXYNOS5_GPA1(0),
2396 .ngpio = EXYNOS5_GPIO_A1_NR,
2401 .base = EXYNOS5_GPA2(0),
2402 .ngpio = EXYNOS5_GPIO_A2_NR,
2407 .base = EXYNOS5_GPB0(0),
2408 .ngpio = EXYNOS5_GPIO_B0_NR,
2413 .base = EXYNOS5_GPB1(0),
2414 .ngpio = EXYNOS5_GPIO_B1_NR,
2419 .base = EXYNOS5_GPB2(0),
2420 .ngpio = EXYNOS5_GPIO_B2_NR,
2425 .base = EXYNOS5_GPB3(0),
2426 .ngpio = EXYNOS5_GPIO_B3_NR,
2431 .base = EXYNOS5_GPC0(0),
2432 .ngpio = EXYNOS5_GPIO_C0_NR,
2437 .base = EXYNOS5_GPC1(0),
2438 .ngpio = EXYNOS5_GPIO_C1_NR,
2443 .base = EXYNOS5_GPC2(0),
2444 .ngpio = EXYNOS5_GPIO_C2_NR,
2449 .base = EXYNOS5_GPC3(0),
2450 .ngpio = EXYNOS5_GPIO_C3_NR,
2455 .base = EXYNOS5_GPD0(0),
2456 .ngpio = EXYNOS5_GPIO_D0_NR,
2461 .base = EXYNOS5_GPD1(0),
2462 .ngpio = EXYNOS5_GPIO_D1_NR,
2467 .base = EXYNOS5_GPY0(0),
2468 .ngpio = EXYNOS5_GPIO_Y0_NR,
2473 .base = EXYNOS5_GPY1(0),
2474 .ngpio = EXYNOS5_GPIO_Y1_NR,
2479 .base = EXYNOS5_GPY2(0),
2480 .ngpio = EXYNOS5_GPIO_Y2_NR,
2485 .base = EXYNOS5_GPY3(0),
2486 .ngpio = EXYNOS5_GPIO_Y3_NR,
2491 .base = EXYNOS5_GPY4(0),
2492 .ngpio = EXYNOS5_GPIO_Y4_NR,
2497 .base = EXYNOS5_GPY5(0),
2498 .ngpio = EXYNOS5_GPIO_Y5_NR,
2503 .base = EXYNOS5_GPY6(0),
2504 .ngpio = EXYNOS5_GPIO_Y6_NR,
2508 .config = &samsung_gpio_cfgs[9],
2509 .irq_base = IRQ_EINT(0),
2511 .base = EXYNOS5_GPX0(0),
2512 .ngpio = EXYNOS5_GPIO_X0_NR,
2514 .to_irq = samsung_gpiolib_to_irq,
2517 .config = &samsung_gpio_cfgs[9],
2518 .irq_base = IRQ_EINT(8),
2520 .base = EXYNOS5_GPX1(0),
2521 .ngpio = EXYNOS5_GPIO_X1_NR,
2523 .to_irq = samsung_gpiolib_to_irq,
2526 .config = &samsung_gpio_cfgs[9],
2527 .irq_base = IRQ_EINT(16),
2529 .base = EXYNOS5_GPX2(0),
2530 .ngpio = EXYNOS5_GPIO_X2_NR,
2532 .to_irq = samsung_gpiolib_to_irq,
2535 .config = &samsung_gpio_cfgs[9],
2536 .irq_base = IRQ_EINT(24),
2538 .base = EXYNOS5_GPX3(0),
2539 .ngpio = EXYNOS5_GPIO_X3_NR,
2541 .to_irq = samsung_gpiolib_to_irq,
2547 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2548 #ifdef CONFIG_ARCH_EXYNOS5
2551 .base = EXYNOS5_GPE0(0),
2552 .ngpio = EXYNOS5_GPIO_E0_NR,
2557 .base = EXYNOS5_GPE1(0),
2558 .ngpio = EXYNOS5_GPIO_E1_NR,
2563 .base = EXYNOS5_GPF0(0),
2564 .ngpio = EXYNOS5_GPIO_F0_NR,
2569 .base = EXYNOS5_GPF1(0),
2570 .ngpio = EXYNOS5_GPIO_F1_NR,
2575 .base = EXYNOS5_GPG0(0),
2576 .ngpio = EXYNOS5_GPIO_G0_NR,
2581 .base = EXYNOS5_GPG1(0),
2582 .ngpio = EXYNOS5_GPIO_G1_NR,
2587 .base = EXYNOS5_GPG2(0),
2588 .ngpio = EXYNOS5_GPIO_G2_NR,
2593 .base = EXYNOS5_GPH0(0),
2594 .ngpio = EXYNOS5_GPIO_H0_NR,
2599 .base = EXYNOS5_GPH1(0),
2600 .ngpio = EXYNOS5_GPIO_H1_NR,
2608 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2609 #ifdef CONFIG_ARCH_EXYNOS5
2612 .base = EXYNOS5_GPV0(0),
2613 .ngpio = EXYNOS5_GPIO_V0_NR,
2618 .base = EXYNOS5_GPV1(0),
2619 .ngpio = EXYNOS5_GPIO_V1_NR,
2624 .base = EXYNOS5_GPV2(0),
2625 .ngpio = EXYNOS5_GPIO_V2_NR,
2630 .base = EXYNOS5_GPV3(0),
2631 .ngpio = EXYNOS5_GPIO_V3_NR,
2636 .base = EXYNOS5_GPV4(0),
2637 .ngpio = EXYNOS5_GPIO_V4_NR,
2644 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2645 #ifdef CONFIG_ARCH_EXYNOS5
2648 .base = EXYNOS5_GPZ(0),
2649 .ngpio = EXYNOS5_GPIO_Z_NR,
2657 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2658 static int exynos_gpio_xlate(struct gpio_chip *gc,
2659 const struct of_phandle_args *gpiospec, u32 *flags)
2663 if (WARN_ON(gc->of_gpio_n_cells < 4))
2666 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2669 if (gpiospec->args[0] > gc->ngpio)
2672 pin = gc->base + gpiospec->args[0];
2674 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2675 pr_warn("gpio_xlate: failed to set pin function\n");
2676 if (s3c_gpio_setpull(pin, gpiospec->args[2]))
2677 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2678 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2679 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2681 return gpiospec->args[0];
2684 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2685 { .compatible = "samsung,exynos4-gpio", },
2689 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2690 u64 base, u64 offset)
2692 struct gpio_chip *gc = &chip->chip;
2695 if (!of_have_populated_dt())
2698 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2699 gc->of_node = of_find_matching_node_by_address(NULL,
2700 exynos_gpio_dt_match, address);
2702 pr_info("gpio: device tree node not found for gpio controller"
2703 " with base address %08llx\n", address);
2706 gc->of_gpio_n_cells = 4;
2707 gc->of_xlate = exynos_gpio_xlate;
2709 #elif defined(CONFIG_ARCH_EXYNOS)
2710 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2711 u64 base, u64 offset)
2715 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2717 /* TODO: cleanup soc_is_* */
2718 static __init int samsung_gpiolib_init(void)
2720 struct samsung_gpio_chip *chip;
2722 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2725 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2727 if (soc_is_s3c24xx()) {
2728 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2729 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2730 } else if (soc_is_s3c64xx()) {
2731 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2732 ARRAY_SIZE(s3c64xx_gpios_2bit),
2733 S3C64XX_VA_GPIO + 0xE0, 0x20);
2734 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2735 ARRAY_SIZE(s3c64xx_gpios_4bit),
2737 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2738 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2739 } else if (soc_is_s5p6440()) {
2740 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2741 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2742 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2743 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2744 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2745 ARRAY_SIZE(s5p6440_gpios_4bit2));
2746 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2747 ARRAY_SIZE(s5p6440_gpios_rbank));
2748 } else if (soc_is_s5p6450()) {
2749 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2750 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2751 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2752 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2753 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2754 ARRAY_SIZE(s5p6450_gpios_4bit2));
2755 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2756 ARRAY_SIZE(s5p6450_gpios_rbank));
2757 } else if (soc_is_s5pc100()) {
2759 chip = s5pc100_gpios_4bit;
2760 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2762 for (i = 0; i < nr_chips; i++, chip++) {
2763 if (!chip->config) {
2764 chip->config = &samsung_gpio_cfgs[3];
2765 chip->group = group++;
2768 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2769 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2770 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2772 } else if (soc_is_s5pv210()) {
2774 chip = s5pv210_gpios_4bit;
2775 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2777 for (i = 0; i < nr_chips; i++, chip++) {
2778 if (!chip->config) {
2779 chip->config = &samsung_gpio_cfgs[3];
2780 chip->group = group++;
2783 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2784 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2785 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2787 } else if (soc_is_exynos4210()) {
2788 #ifdef CONFIG_CPU_EXYNOS4210
2789 void __iomem *gpx_base;
2792 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2793 if (gpio_base1 == NULL) {
2794 pr_err("unable to ioremap for gpio_base1\n");
2798 chip = exynos4_gpios_1;
2799 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2801 for (i = 0; i < nr_chips; i++, chip++) {
2802 if (!chip->config) {
2803 chip->config = &exynos_gpio_cfg;
2804 chip->group = group++;
2806 exynos_gpiolib_attach_ofnode(chip,
2807 EXYNOS4_PA_GPIO1, i * 0x20);
2809 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2810 nr_chips, gpio_base1);
2813 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2814 if (gpio_base2 == NULL) {
2815 pr_err("unable to ioremap for gpio_base2\n");
2819 /* need to set base address for gpx */
2820 chip = &exynos4_gpios_2[16];
2821 gpx_base = gpio_base2 + 0xC00;
2822 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2823 chip->base = gpx_base;
2825 chip = exynos4_gpios_2;
2826 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2828 for (i = 0; i < nr_chips; i++, chip++) {
2829 if (!chip->config) {
2830 chip->config = &exynos_gpio_cfg;
2831 chip->group = group++;
2833 exynos_gpiolib_attach_ofnode(chip,
2834 EXYNOS4_PA_GPIO2, i * 0x20);
2836 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2837 nr_chips, gpio_base2);
2840 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2841 if (gpio_base3 == NULL) {
2842 pr_err("unable to ioremap for gpio_base3\n");
2846 chip = exynos4_gpios_3;
2847 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2849 for (i = 0; i < nr_chips; i++, chip++) {
2850 if (!chip->config) {
2851 chip->config = &exynos_gpio_cfg;
2852 chip->group = group++;
2854 exynos_gpiolib_attach_ofnode(chip,
2855 EXYNOS4_PA_GPIO3, i * 0x20);
2857 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2858 nr_chips, gpio_base3);
2860 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2861 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2862 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2865 #endif /* CONFIG_CPU_EXYNOS4210 */
2866 } else if (soc_is_exynos5250()) {
2867 #ifdef CONFIG_SOC_EXYNOS5250
2868 void __iomem *gpx_base;
2871 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2872 if (gpio_base1 == NULL) {
2873 pr_err("unable to ioremap for gpio_base1\n");
2877 /* need to set base address for gpx */
2878 chip = &exynos5_gpios_1[20];
2879 gpx_base = gpio_base1 + 0xC00;
2880 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2881 chip->base = gpx_base;
2883 chip = exynos5_gpios_1;
2884 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2886 for (i = 0; i < nr_chips; i++, chip++) {
2887 if (!chip->config) {
2888 chip->config = &exynos_gpio_cfg;
2889 chip->group = group++;
2891 exynos_gpiolib_attach_ofnode(chip,
2892 EXYNOS5_PA_GPIO1, i * 0x20);
2894 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2895 nr_chips, gpio_base1);
2898 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2899 if (gpio_base2 == NULL) {
2900 pr_err("unable to ioremap for gpio_base2\n");
2904 chip = exynos5_gpios_2;
2905 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2907 for (i = 0; i < nr_chips; i++, chip++) {
2908 if (!chip->config) {
2909 chip->config = &exynos_gpio_cfg;
2910 chip->group = group++;
2912 exynos_gpiolib_attach_ofnode(chip,
2913 EXYNOS5_PA_GPIO2, i * 0x20);
2915 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2916 nr_chips, gpio_base2);
2919 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2920 if (gpio_base3 == NULL) {
2921 pr_err("unable to ioremap for gpio_base3\n");
2925 /* need to set base address for gpv */
2926 exynos5_gpios_3[0].base = gpio_base3;
2927 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2928 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2929 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2930 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2932 chip = exynos5_gpios_3;
2933 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2935 for (i = 0; i < nr_chips; i++, chip++) {
2936 if (!chip->config) {
2937 chip->config = &exynos_gpio_cfg;
2938 chip->group = group++;
2940 exynos_gpiolib_attach_ofnode(chip,
2941 EXYNOS5_PA_GPIO3, i * 0x20);
2943 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2944 nr_chips, gpio_base3);
2947 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2948 if (gpio_base4 == NULL) {
2949 pr_err("unable to ioremap for gpio_base4\n");
2953 chip = exynos5_gpios_4;
2954 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2956 for (i = 0; i < nr_chips; i++, chip++) {
2957 if (!chip->config) {
2958 chip->config = &exynos_gpio_cfg;
2959 chip->group = group++;
2961 exynos_gpiolib_attach_ofnode(chip,
2962 EXYNOS5_PA_GPIO4, i * 0x20);
2964 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2965 nr_chips, gpio_base4);
2966 #endif /* CONFIG_SOC_EXYNOS5250 */
2968 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2975 iounmap(gpio_base3);
2977 iounmap(gpio_base2);
2979 iounmap(gpio_base1);
2983 core_initcall(samsung_gpiolib_init);
2985 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2987 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2988 unsigned long flags;
2995 offset = pin - chip->chip.base;
2997 samsung_gpio_lock(chip, flags);
2998 ret = samsung_gpio_do_setcfg(chip, offset, config);
2999 samsung_gpio_unlock(chip, flags);
3003 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3005 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3010 for (; nr > 0; nr--, start++) {
3011 ret = s3c_gpio_cfgpin(start, cfg);
3018 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3020 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3021 unsigned int cfg, samsung_gpio_pull_t pull)
3025 for (; nr > 0; nr--, start++) {
3026 s3c_gpio_setpull(start, pull);
3027 ret = s3c_gpio_cfgpin(start, cfg);
3034 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3036 unsigned s3c_gpio_getcfg(unsigned int pin)
3038 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3039 unsigned long flags;
3044 offset = pin - chip->chip.base;
3046 samsung_gpio_lock(chip, flags);
3047 ret = samsung_gpio_do_getcfg(chip, offset);
3048 samsung_gpio_unlock(chip, flags);
3053 EXPORT_SYMBOL(s3c_gpio_getcfg);
3055 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3057 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3058 unsigned long flags;
3064 offset = pin - chip->chip.base;
3066 samsung_gpio_lock(chip, flags);
3067 ret = samsung_gpio_do_setpull(chip, offset, pull);
3068 samsung_gpio_unlock(chip, flags);
3072 EXPORT_SYMBOL(s3c_gpio_setpull);
3074 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3076 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3077 unsigned long flags;
3082 offset = pin - chip->chip.base;
3084 samsung_gpio_lock(chip, flags);
3085 pup = samsung_gpio_do_getpull(chip, offset);
3086 samsung_gpio_unlock(chip, flags);
3089 return (__force samsung_gpio_pull_t)pup;
3091 EXPORT_SYMBOL(s3c_gpio_getpull);
3093 /* gpiolib wrappers until these are totally eliminated */
3095 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
3099 WARN_ON(to); /* should be none of these left */
3102 /* if pull is enabled, try first with up, and if that
3103 * fails, try using down */
3105 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
3107 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
3109 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
3112 EXPORT_SYMBOL(s3c2410_gpio_pullup);
3114 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
3116 /* do this via gpiolib until all users removed */
3118 gpio_request(pin, "temporary");
3119 gpio_set_value(pin, to);
3122 EXPORT_SYMBOL(s3c2410_gpio_setpin);
3124 unsigned int s3c2410_gpio_getpin(unsigned int pin)
3126 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3127 unsigned long offs = pin - chip->chip.base;
3129 return __raw_readl(chip->base + 0x04) & (1 << offs);
3131 EXPORT_SYMBOL(s3c2410_gpio_getpin);
3133 #ifdef CONFIG_S5P_GPIO_DRVSTR
3134 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3136 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3145 off = pin - chip->chip.base;
3147 reg = chip->base + 0x0C;
3149 drvstr = __raw_readl(reg);
3150 drvstr = drvstr >> shift;
3153 return (__force s5p_gpio_drvstr_t)drvstr;
3155 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3157 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3159 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3168 off = pin - chip->chip.base;
3170 reg = chip->base + 0x0C;
3172 tmp = __raw_readl(reg);
3173 tmp &= ~(0x3 << shift);
3174 tmp |= drvstr << shift;
3176 __raw_writel(tmp, reg);
3180 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3181 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3183 #ifdef CONFIG_PLAT_S3C24XX
3184 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3186 unsigned long flags;
3187 unsigned long misccr;
3189 local_irq_save(flags);
3190 misccr = __raw_readl(S3C24XX_MISCCR);
3193 __raw_writel(misccr, S3C24XX_MISCCR);
3194 local_irq_restore(flags);
3198 EXPORT_SYMBOL(s3c2410_modify_misccr);