1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/gpio/driver.h>
4 #include <linux/cpumask.h>
6 #include <linux/minmax.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/property.h>
13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
14 * An optional second bank, with ports E, F, G, and H, may be present, starting
15 * at register offset 0x1C.
19 * Pin select: (0) "normal", (1) "dedicate peripheral"
20 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits
21 * in the peripheral registers.
23 #define REALTEK_GPIO_REG_CNR 0x00
24 /* Clear bit (0) for input, set bit (1) for output */
25 #define REALTEK_GPIO_REG_DIR 0x08
26 #define REALTEK_GPIO_REG_DATA 0x0C
27 /* Read bit for IRQ status, write 1 to clear IRQ */
28 #define REALTEK_GPIO_REG_ISR 0x10
29 /* Two bits per GPIO in IMR registers */
30 #define REALTEK_GPIO_REG_IMR 0x14
31 #define REALTEK_GPIO_REG_IMR_AB 0x14
32 #define REALTEK_GPIO_REG_IMR_CD 0x18
33 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0)
34 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1
35 #define REALTEK_GPIO_IRQ_EDGE_RISING 2
36 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3
38 #define REALTEK_GPIO_MAX 32
39 #define REALTEK_GPIO_PORTS_PER_BANK 4
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
44 * @gc: Associated gpio_chip instance
45 * @base: Base address of the register block for a GPIO bank
46 * @lock: Lock for accessing the IRQ registers and values
47 * @intr_mask: Mask for interrupts lines
48 * @intr_type: Interrupt type selection
50 * Because the interrupt mask register (IMR) combines the function of IRQ type
51 * selection and masking, two extra values are stored. @intr_mask is used to
52 * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store
53 * the selected interrupt types. The logical AND of these values is written to
56 struct realtek_gpio_ctrl {
59 void __iomem *cpumask_base;
60 struct cpumask cpu_irq_maskable;
62 u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
63 u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
64 unsigned int (*port_offset_u8)(unsigned int port);
65 unsigned int (*port_offset_u16)(unsigned int port);
68 /* Expand with more flags as devices with other quirks are added */
69 enum realtek_gpio_flags {
71 * Allow disabling interrupts, for cases where the port order is
72 * unknown. This may result in a port mismatch between ISR and IMR.
73 * An interrupt would appear to come from a different line than the
74 * line the IRQ handler was assigned to, causing uncaught interrupts.
76 GPIO_INTERRUPTS_DISABLED = BIT(0),
78 * Port order is reversed, meaning DCBA register layout for 1-bit
79 * fields, and [BA, DC] for 2-bit fields.
81 GPIO_PORTS_REVERSED = BIT(1),
83 * Interrupts can be enabled per cpu. This requires a secondary IO
84 * range, where the per-cpu enable masks are located.
86 GPIO_INTERRUPTS_PER_CPU = BIT(2),
89 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
91 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
93 return container_of(gc, struct realtek_gpio_ctrl, gc);
97 * Normal port order register access
99 * Port information is stored with the first port at offset 0, followed by the
100 * second, etc. Most registers store one bit per GPIO and use a u8 value per
101 * port. The two interrupt mask registers store two bits per GPIO, so use u16
104 static unsigned int realtek_gpio_port_offset_u8(unsigned int port)
109 static unsigned int realtek_gpio_port_offset_u16(unsigned int port)
115 * Reversed port order register access
117 * For registers with one bit per GPIO, all ports are stored as u8-s in one
118 * register in reversed order. The two interrupt mask registers store two bits
119 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the
120 * second ports 3 and 2.
122 static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port)
127 static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port)
129 return 2 * (port ^ 1);
132 static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,
133 unsigned int port, u16 irq_type, u16 irq_mask)
135 iowrite16(irq_type & irq_mask,
136 ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port));
139 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,
140 unsigned int port, u8 mask)
142 iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));
145 static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)
147 return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));
150 /* Set the rising and falling edge mask bits for a GPIO port pin */
151 static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value)
153 return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin;
156 static void realtek_gpio_irq_ack(struct irq_data *data)
158 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
159 irq_hw_number_t line = irqd_to_hwirq(data);
160 unsigned int port = line / 8;
161 unsigned int port_pin = line % 8;
163 realtek_gpio_clear_isr(ctrl, port, BIT(port_pin));
166 static void realtek_gpio_irq_unmask(struct irq_data *data)
168 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
169 unsigned int line = irqd_to_hwirq(data);
170 unsigned int port = line / 8;
171 unsigned int port_pin = line % 8;
175 gpiochip_enable_irq(&ctrl->gc, line);
177 raw_spin_lock_irqsave(&ctrl->lock, flags);
178 m = ctrl->intr_mask[port];
179 m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
180 ctrl->intr_mask[port] = m;
181 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
182 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
185 static void realtek_gpio_irq_mask(struct irq_data *data)
187 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
188 unsigned int line = irqd_to_hwirq(data);
189 unsigned int port = line / 8;
190 unsigned int port_pin = line % 8;
194 raw_spin_lock_irqsave(&ctrl->lock, flags);
195 m = ctrl->intr_mask[port];
196 m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
197 ctrl->intr_mask[port] = m;
198 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);
199 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
201 gpiochip_disable_irq(&ctrl->gc, line);
204 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
206 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
207 unsigned int line = irqd_to_hwirq(data);
208 unsigned int port = line / 8;
209 unsigned int port_pin = line % 8;
213 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
214 case IRQ_TYPE_EDGE_FALLING:
215 type = REALTEK_GPIO_IRQ_EDGE_FALLING;
217 case IRQ_TYPE_EDGE_RISING:
218 type = REALTEK_GPIO_IRQ_EDGE_RISING;
220 case IRQ_TYPE_EDGE_BOTH:
221 type = REALTEK_GPIO_IRQ_EDGE_BOTH;
227 irq_set_handler_locked(data, handle_edge_irq);
229 raw_spin_lock_irqsave(&ctrl->lock, flags);
230 t = ctrl->intr_type[port];
231 t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);
232 t |= realtek_gpio_imr_bits(port_pin, type);
233 ctrl->intr_type[port] = t;
234 realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]);
235 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
240 static void realtek_gpio_irq_handler(struct irq_desc *desc)
242 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
243 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
244 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
245 unsigned int lines_done;
246 unsigned int port_pin_count;
247 unsigned long status;
250 chained_irq_enter(irq_chip, desc);
252 for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {
253 status = realtek_gpio_read_isr(ctrl, lines_done / 8);
254 port_pin_count = min(gc->ngpio - lines_done, 8U);
255 for_each_set_bit(offset, &status, port_pin_count)
256 generic_handle_domain_irq(gc->irq.domain, offset + lines_done);
259 chained_irq_exit(irq_chip, desc);
262 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl,
263 unsigned int port, int cpu)
265 return ctrl->cpumask_base + ctrl->port_offset_u8(port) +
266 REALTEK_GPIO_PORTS_PER_BANK * cpu;
269 static int realtek_gpio_irq_set_affinity(struct irq_data *data,
270 const struct cpumask *dest, bool force)
272 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
273 unsigned int line = irqd_to_hwirq(data);
274 unsigned int port = line / 8;
275 unsigned int port_pin = line % 8;
276 void __iomem *irq_cpu_mask;
281 if (!ctrl->cpumask_base)
284 raw_spin_lock_irqsave(&ctrl->lock, flags);
286 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
287 irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu);
288 v = ioread8(irq_cpu_mask);
290 if (cpumask_test_cpu(cpu, dest))
295 iowrite8(v, irq_cpu_mask);
298 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
300 irq_data_update_effective_affinity(data, dest);
305 static int realtek_gpio_irq_init(struct gpio_chip *gc)
307 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
311 for (port = 0; (port * 8) < gc->ngpio; port++) {
312 realtek_gpio_write_imr(ctrl, port, 0, 0);
313 realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
315 for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
316 iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu));
322 static const struct irq_chip realtek_gpio_irq_chip = {
323 .name = "realtek-otto-gpio",
324 .irq_ack = realtek_gpio_irq_ack,
325 .irq_mask = realtek_gpio_irq_mask,
326 .irq_unmask = realtek_gpio_irq_unmask,
327 .irq_set_type = realtek_gpio_irq_set_type,
328 .irq_set_affinity = realtek_gpio_irq_set_affinity,
329 .flags = IRQCHIP_IMMUTABLE,
330 GPIOCHIP_IRQ_RESOURCE_HELPERS,
333 static const struct of_device_id realtek_gpio_of_match[] = {
335 .compatible = "realtek,otto-gpio",
336 .data = (void *)GPIO_INTERRUPTS_DISABLED,
339 .compatible = "realtek,rtl8380-gpio",
342 .compatible = "realtek,rtl8390-gpio",
345 .compatible = "realtek,rtl9300-gpio",
346 .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)
349 .compatible = "realtek,rtl9310-gpio",
353 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);
355 static int realtek_gpio_probe(struct platform_device *pdev)
357 struct device *dev = &pdev->dev;
358 unsigned long bgpio_flags;
359 unsigned int dev_flags;
360 struct gpio_irq_chip *girq;
361 struct realtek_gpio_ctrl *ctrl;
362 struct resource *res;
364 unsigned int nr_cpus;
367 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
371 dev_flags = (unsigned int) device_get_match_data(dev);
373 ngpios = REALTEK_GPIO_MAX;
374 device_property_read_u32(dev, "ngpios", &ngpios);
376 if (ngpios > REALTEK_GPIO_MAX) {
377 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",
382 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
383 if (IS_ERR(ctrl->base))
384 return PTR_ERR(ctrl->base);
386 raw_spin_lock_init(&ctrl->lock);
388 if (dev_flags & GPIO_PORTS_REVERSED) {
390 ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev;
391 ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev;
393 bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
394 ctrl->port_offset_u8 = realtek_gpio_port_offset_u8;
395 ctrl->port_offset_u16 = realtek_gpio_port_offset_u16;
398 err = bgpio_init(&ctrl->gc, dev, 4,
399 ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,
400 ctrl->base + REALTEK_GPIO_REG_DIR, NULL,
403 dev_err(dev, "unable to init generic GPIO");
407 ctrl->gc.ngpio = ngpios;
408 ctrl->gc.owner = THIS_MODULE;
410 irq = platform_get_irq_optional(pdev, 0);
411 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {
412 girq = &ctrl->gc.irq;
413 gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip);
414 girq->default_type = IRQ_TYPE_NONE;
415 girq->handler = handle_bad_irq;
416 girq->parent_handler = realtek_gpio_irq_handler;
417 girq->num_parents = 1;
418 girq->parents = devm_kcalloc(dev, girq->num_parents,
419 sizeof(*girq->parents), GFP_KERNEL);
422 girq->parents[0] = irq;
423 girq->init_hw = realtek_gpio_irq_init;
426 cpumask_clear(&ctrl->cpu_irq_maskable);
428 if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
429 ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
430 if (IS_ERR(ctrl->cpumask_base))
431 return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
432 "missing CPU IRQ mask registers");
434 nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
435 nr_cpus = min(nr_cpus, num_present_cpus());
437 for (cpu = 0; cpu < nr_cpus; cpu++)
438 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
441 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
444 static struct platform_driver realtek_gpio_driver = {
446 .name = "realtek-otto-gpio",
447 .of_match_table = realtek_gpio_of_match,
449 .probe = realtek_gpio_probe,
451 module_platform_driver(realtek_gpio_driver);
453 MODULE_DESCRIPTION("Realtek Otto GPIO support");
454 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
455 MODULE_LICENSE("GPL v2");