2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
50 struct gpio_chip chip;
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
61 struct omap_gpio_reg_offs *regs;
64 #ifdef CONFIG_ARCH_OMAP3
65 struct omap3_gpio_regs {
78 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
85 static struct gpio_bank *gpio_bank;
87 /* TODO: Analyze removing gpio_bank_count usage from driver code */
90 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
93 static inline int gpio_valid(int gpio)
97 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
98 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
102 if (cpu_is_omap15xx() && gpio < 16)
104 if ((cpu_is_omap16xx()) && gpio < 64)
106 if (cpu_is_omap7xx() && gpio < 192)
108 if (cpu_is_omap2420() && gpio < 128)
110 if (cpu_is_omap2430() && gpio < 160)
112 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
117 static int check_gpio(int gpio)
119 if (unlikely(gpio_valid(gpio) < 0)) {
120 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
127 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
129 void __iomem *reg = bank->base;
132 reg += bank->regs->direction;
133 l = __raw_readl(reg);
138 __raw_writel(l, reg);
142 /* set data out value using dedicate set/clear register */
143 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
145 void __iomem *reg = bank->base;
146 u32 l = GPIO_BIT(bank, gpio);
149 reg += bank->regs->set_dataout;
151 reg += bank->regs->clr_dataout;
153 __raw_writel(l, reg);
156 /* set data out value using mask register */
157 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
159 void __iomem *reg = bank->base + bank->regs->dataout;
160 u32 gpio_bit = GPIO_BIT(bank, gpio);
163 l = __raw_readl(reg);
168 __raw_writel(l, reg);
171 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
173 void __iomem *reg = bank->base + bank->regs->datain;
175 if (check_gpio(gpio) < 0)
178 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
181 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
183 void __iomem *reg = bank->base + bank->regs->dataout;
185 if (check_gpio(gpio) < 0)
188 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
191 #define MOD_REG_BIT(reg, bit_mask, set) \
193 int l = __raw_readl(base + reg); \
194 if (set) l |= bit_mask; \
195 else l &= ~bit_mask; \
196 __raw_writel(l, base + reg); \
200 * _set_gpio_debounce - low level gpio debounce time
201 * @bank: the gpio bank we're acting upon
202 * @gpio: the gpio number on this @gpio
203 * @debounce: debounce time to use
205 * OMAP's debounce time is in 31us steps so we need
206 * to convert and round up to the closest unit.
208 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
211 void __iomem *reg = bank->base;
215 if (!bank->dbck_flag)
220 else if (debounce > 7936)
223 debounce = (debounce / 0x1f) - 1;
225 l = GPIO_BIT(bank, gpio);
227 if (bank->method == METHOD_GPIO_44XX)
228 reg += OMAP4_GPIO_DEBOUNCINGTIME;
230 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
232 __raw_writel(debounce, reg);
235 if (bank->method == METHOD_GPIO_44XX)
236 reg += OMAP4_GPIO_DEBOUNCENABLE;
238 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
240 val = __raw_readl(reg);
244 clk_enable(bank->dbck);
247 clk_disable(bank->dbck);
249 bank->dbck_enable_mask = val;
251 __raw_writel(val, reg);
254 #ifdef CONFIG_ARCH_OMAP2PLUS
255 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
258 void __iomem *base = bank->base;
259 u32 gpio_bit = 1 << gpio;
261 if (cpu_is_omap44xx()) {
262 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
263 trigger & IRQ_TYPE_LEVEL_LOW);
264 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
265 trigger & IRQ_TYPE_LEVEL_HIGH);
266 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
267 trigger & IRQ_TYPE_EDGE_RISING);
268 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
269 trigger & IRQ_TYPE_EDGE_FALLING);
271 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
272 trigger & IRQ_TYPE_LEVEL_LOW);
273 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
274 trigger & IRQ_TYPE_LEVEL_HIGH);
275 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
276 trigger & IRQ_TYPE_EDGE_RISING);
277 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
278 trigger & IRQ_TYPE_EDGE_FALLING);
280 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
281 if (cpu_is_omap44xx()) {
282 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
286 * GPIO wakeup request can only be generated on edge
289 if (trigger & IRQ_TYPE_EDGE_BOTH)
290 __raw_writel(1 << gpio, bank->base
291 + OMAP24XX_GPIO_SETWKUENA);
293 __raw_writel(1 << gpio, bank->base
294 + OMAP24XX_GPIO_CLEARWKUENA);
297 /* This part needs to be executed always for OMAP34xx */
298 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
300 * Log the edge gpio and manually trigger the IRQ
301 * after resume if the input level changes
302 * to avoid irq lost during PER RET/OFF mode
303 * Applies for omap2 non-wakeup gpio and all omap3 gpios
305 if (trigger & IRQ_TYPE_EDGE_BOTH)
306 bank->enabled_non_wakeup_gpios |= gpio_bit;
308 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
311 if (cpu_is_omap44xx()) {
313 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
314 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
317 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
318 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
323 #ifdef CONFIG_ARCH_OMAP1
325 * This only applies to chips that can't do both rising and falling edge
326 * detection at once. For all other chips, this function is a noop.
328 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
330 void __iomem *reg = bank->base;
333 switch (bank->method) {
335 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
337 #ifdef CONFIG_ARCH_OMAP15XX
338 case METHOD_GPIO_1510:
339 reg += OMAP1510_GPIO_INT_CONTROL;
342 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
343 case METHOD_GPIO_7XX:
344 reg += OMAP7XX_GPIO_INT_CONTROL;
351 l = __raw_readl(reg);
357 __raw_writel(l, reg);
361 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
363 void __iomem *reg = bank->base;
366 switch (bank->method) {
367 #ifdef CONFIG_ARCH_OMAP1
369 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
370 l = __raw_readl(reg);
371 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
372 bank->toggle_mask |= 1 << gpio;
373 if (trigger & IRQ_TYPE_EDGE_RISING)
375 else if (trigger & IRQ_TYPE_EDGE_FALLING)
381 #ifdef CONFIG_ARCH_OMAP15XX
382 case METHOD_GPIO_1510:
383 reg += OMAP1510_GPIO_INT_CONTROL;
384 l = __raw_readl(reg);
385 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
386 bank->toggle_mask |= 1 << gpio;
387 if (trigger & IRQ_TYPE_EDGE_RISING)
389 else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 #ifdef CONFIG_ARCH_OMAP16XX
396 case METHOD_GPIO_1610:
398 reg += OMAP1610_GPIO_EDGE_CTRL2;
400 reg += OMAP1610_GPIO_EDGE_CTRL1;
402 l = __raw_readl(reg);
403 l &= ~(3 << (gpio << 1));
404 if (trigger & IRQ_TYPE_EDGE_RISING)
405 l |= 2 << (gpio << 1);
406 if (trigger & IRQ_TYPE_EDGE_FALLING)
407 l |= 1 << (gpio << 1);
409 /* Enable wake-up during idle for dynamic tick */
410 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
412 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
415 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
416 case METHOD_GPIO_7XX:
417 reg += OMAP7XX_GPIO_INT_CONTROL;
418 l = __raw_readl(reg);
419 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
420 bank->toggle_mask |= 1 << gpio;
421 if (trigger & IRQ_TYPE_EDGE_RISING)
423 else if (trigger & IRQ_TYPE_EDGE_FALLING)
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 case METHOD_GPIO_24XX:
431 case METHOD_GPIO_44XX:
432 set_24xx_gpio_triggering(bank, gpio, trigger);
438 __raw_writel(l, reg);
444 static int gpio_irq_type(struct irq_data *d, unsigned type)
446 struct gpio_bank *bank;
451 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
452 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
454 gpio = d->irq - IH_GPIO_BASE;
456 if (check_gpio(gpio) < 0)
459 if (type & ~IRQ_TYPE_SENSE_MASK)
462 /* OMAP1 allows only only edge triggering */
463 if (!cpu_class_is_omap2()
464 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
467 bank = irq_data_get_irq_chip_data(d);
468 spin_lock_irqsave(&bank->lock, flags);
469 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
470 spin_unlock_irqrestore(&bank->lock, flags);
472 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
473 __irq_set_handler_locked(d->irq, handle_level_irq);
474 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
475 __irq_set_handler_locked(d->irq, handle_edge_irq);
480 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
482 void __iomem *reg = bank->base;
484 switch (bank->method) {
485 #ifdef CONFIG_ARCH_OMAP15XX
486 case METHOD_GPIO_1510:
487 reg += OMAP1510_GPIO_INT_STATUS;
490 #ifdef CONFIG_ARCH_OMAP16XX
491 case METHOD_GPIO_1610:
492 reg += OMAP1610_GPIO_IRQSTATUS1;
495 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
496 case METHOD_GPIO_7XX:
497 reg += OMAP7XX_GPIO_INT_STATUS;
500 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
501 case METHOD_GPIO_24XX:
502 reg += OMAP24XX_GPIO_IRQSTATUS1;
505 #if defined(CONFIG_ARCH_OMAP4)
506 case METHOD_GPIO_44XX:
507 reg += OMAP4_GPIO_IRQSTATUS0;
514 __raw_writel(gpio_mask, reg);
516 /* Workaround for clearing DSP GPIO interrupts to allow retention */
517 if (cpu_is_omap24xx() || cpu_is_omap34xx())
518 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
519 else if (cpu_is_omap44xx())
520 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
522 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx())
523 __raw_writel(gpio_mask, reg);
525 /* Flush posted write for the irq status to avoid spurious interrupts */
529 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
531 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
534 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
536 void __iomem *reg = bank->base;
539 u32 mask = (1 << bank->width) - 1;
541 switch (bank->method) {
542 #ifdef CONFIG_ARCH_OMAP1
544 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
548 #ifdef CONFIG_ARCH_OMAP15XX
549 case METHOD_GPIO_1510:
550 reg += OMAP1510_GPIO_INT_MASK;
554 #ifdef CONFIG_ARCH_OMAP16XX
555 case METHOD_GPIO_1610:
556 reg += OMAP1610_GPIO_IRQENABLE1;
559 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
560 case METHOD_GPIO_7XX:
561 reg += OMAP7XX_GPIO_INT_MASK;
565 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
566 case METHOD_GPIO_24XX:
567 reg += OMAP24XX_GPIO_IRQENABLE1;
570 #if defined(CONFIG_ARCH_OMAP4)
571 case METHOD_GPIO_44XX:
572 reg += OMAP4_GPIO_IRQSTATUSSET0;
580 l = __raw_readl(reg);
587 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
589 void __iomem *reg = bank->base;
592 switch (bank->method) {
593 #ifdef CONFIG_ARCH_OMAP1
595 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
596 l = __raw_readl(reg);
603 #ifdef CONFIG_ARCH_OMAP15XX
604 case METHOD_GPIO_1510:
605 reg += OMAP1510_GPIO_INT_MASK;
606 l = __raw_readl(reg);
613 #ifdef CONFIG_ARCH_OMAP16XX
614 case METHOD_GPIO_1610:
616 reg += OMAP1610_GPIO_SET_IRQENABLE1;
618 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
622 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
623 case METHOD_GPIO_7XX:
624 reg += OMAP7XX_GPIO_INT_MASK;
625 l = __raw_readl(reg);
632 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
633 case METHOD_GPIO_24XX:
635 reg += OMAP24XX_GPIO_SETIRQENABLE1;
637 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
641 #ifdef CONFIG_ARCH_OMAP4
642 case METHOD_GPIO_44XX:
644 reg += OMAP4_GPIO_IRQSTATUSSET0;
646 reg += OMAP4_GPIO_IRQSTATUSCLR0;
654 __raw_writel(l, reg);
657 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
659 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio), enable);
663 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
664 * 1510 does not seem to have a wake-up register. If JTAG is connected
665 * to the target, system will wake up always on GPIO events. While
666 * system is running all registered GPIO interrupts need to have wake-up
667 * enabled. When system is suspended, only selected GPIO interrupts need
668 * to have wake-up enabled.
670 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
672 unsigned long uninitialized_var(flags);
674 switch (bank->method) {
675 #ifdef CONFIG_ARCH_OMAP16XX
677 case METHOD_GPIO_1610:
678 spin_lock_irqsave(&bank->lock, flags);
680 bank->suspend_wakeup |= (1 << gpio);
682 bank->suspend_wakeup &= ~(1 << gpio);
683 spin_unlock_irqrestore(&bank->lock, flags);
686 #ifdef CONFIG_ARCH_OMAP2PLUS
687 case METHOD_GPIO_24XX:
688 case METHOD_GPIO_44XX:
689 if (bank->non_wakeup_gpios & (1 << gpio)) {
690 printk(KERN_ERR "Unable to modify wakeup on "
691 "non-wakeup GPIO%d\n",
692 (bank - gpio_bank) * bank->width + gpio);
695 spin_lock_irqsave(&bank->lock, flags);
697 bank->suspend_wakeup |= (1 << gpio);
699 bank->suspend_wakeup &= ~(1 << gpio);
700 spin_unlock_irqrestore(&bank->lock, flags);
704 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
710 static void _reset_gpio(struct gpio_bank *bank, int gpio)
712 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
713 _set_gpio_irqenable(bank, gpio, 0);
714 _clear_gpio_irqstatus(bank, gpio);
715 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
718 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
719 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
721 unsigned int gpio = d->irq - IH_GPIO_BASE;
722 struct gpio_bank *bank;
725 if (check_gpio(gpio) < 0)
727 bank = irq_data_get_irq_chip_data(d);
728 retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable);
733 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
735 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
738 spin_lock_irqsave(&bank->lock, flags);
740 /* Set trigger to none. You need to enable the desired trigger with
741 * request_irq() or set_irq_type().
743 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
745 #ifdef CONFIG_ARCH_OMAP15XX
746 if (bank->method == METHOD_GPIO_1510) {
749 /* Claim the pin for MPU */
750 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
751 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
754 if (!cpu_class_is_omap1()) {
755 if (!bank->mod_usage) {
756 void __iomem *reg = bank->base;
759 if (cpu_is_omap24xx() || cpu_is_omap34xx())
760 reg += OMAP24XX_GPIO_CTRL;
761 else if (cpu_is_omap44xx())
762 reg += OMAP4_GPIO_CTRL;
763 ctrl = __raw_readl(reg);
764 /* Module is enabled, clocks are not gated */
766 __raw_writel(ctrl, reg);
768 bank->mod_usage |= 1 << offset;
770 spin_unlock_irqrestore(&bank->lock, flags);
775 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
777 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
780 spin_lock_irqsave(&bank->lock, flags);
781 #ifdef CONFIG_ARCH_OMAP16XX
782 if (bank->method == METHOD_GPIO_1610) {
783 /* Disable wake-up during idle for dynamic tick */
784 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
785 __raw_writel(1 << offset, reg);
788 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
789 if (bank->method == METHOD_GPIO_24XX) {
790 /* Disable wake-up during idle for dynamic tick */
791 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
792 __raw_writel(1 << offset, reg);
795 #ifdef CONFIG_ARCH_OMAP4
796 if (bank->method == METHOD_GPIO_44XX) {
797 /* Disable wake-up during idle for dynamic tick */
798 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
799 __raw_writel(1 << offset, reg);
802 if (!cpu_class_is_omap1()) {
803 bank->mod_usage &= ~(1 << offset);
804 if (!bank->mod_usage) {
805 void __iomem *reg = bank->base;
808 if (cpu_is_omap24xx() || cpu_is_omap34xx())
809 reg += OMAP24XX_GPIO_CTRL;
810 else if (cpu_is_omap44xx())
811 reg += OMAP4_GPIO_CTRL;
812 ctrl = __raw_readl(reg);
813 /* Module is disabled, clocks are gated */
815 __raw_writel(ctrl, reg);
818 _reset_gpio(bank, bank->chip.base + offset);
819 spin_unlock_irqrestore(&bank->lock, flags);
823 * We need to unmask the GPIO bank interrupt as soon as possible to
824 * avoid missing GPIO interrupts for other lines in the bank.
825 * Then we need to mask-read-clear-unmask the triggered GPIO lines
826 * in the bank to avoid missing nested interrupts for a GPIO line.
827 * If we wait to unmask individual GPIO lines in the bank after the
828 * line's interrupt handler has been run, we may miss some nested
831 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
833 void __iomem *isr_reg = NULL;
835 unsigned int gpio_irq, gpio_index;
836 struct gpio_bank *bank;
839 struct irq_chip *chip = irq_desc_get_chip(desc);
841 chained_irq_enter(chip, desc);
843 bank = irq_get_handler_data(irq);
844 #ifdef CONFIG_ARCH_OMAP1
845 if (bank->method == METHOD_MPUIO)
846 isr_reg = bank->base +
847 OMAP_MPUIO_GPIO_INT / bank->stride;
849 #ifdef CONFIG_ARCH_OMAP15XX
850 if (bank->method == METHOD_GPIO_1510)
851 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
853 #if defined(CONFIG_ARCH_OMAP16XX)
854 if (bank->method == METHOD_GPIO_1610)
855 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
857 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
858 if (bank->method == METHOD_GPIO_7XX)
859 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
861 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
862 if (bank->method == METHOD_GPIO_24XX)
863 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
865 #if defined(CONFIG_ARCH_OMAP4)
866 if (bank->method == METHOD_GPIO_44XX)
867 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
870 if (WARN_ON(!isr_reg))
874 u32 isr_saved, level_mask = 0;
877 enabled = _get_gpio_irqbank_mask(bank);
878 isr_saved = isr = __raw_readl(isr_reg) & enabled;
880 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
883 if (cpu_class_is_omap2()) {
884 level_mask = bank->level_mask & enabled;
887 /* clear edge sensitive interrupts before handler(s) are
888 called so that we don't miss any interrupt occurred while
890 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
891 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
892 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
894 /* if there is only edge sensitive GPIO pin interrupts
895 configured, we could unmask GPIO bank interrupt immediately */
896 if (!level_mask && !unmasked) {
898 chained_irq_exit(chip, desc);
906 gpio_irq = bank->virtual_irq_start;
907 for (; isr != 0; isr >>= 1, gpio_irq++) {
908 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
913 #ifdef CONFIG_ARCH_OMAP1
915 * Some chips can't respond to both rising and falling
916 * at the same time. If this irq was requested with
917 * both flags, we need to flip the ICR data for the IRQ
918 * to respond to the IRQ for the opposite direction.
919 * This will be indicated in the bank toggle_mask.
921 if (bank->toggle_mask & (1 << gpio_index))
922 _toggle_gpio_edge_triggering(bank, gpio_index);
925 generic_handle_irq(gpio_irq);
928 /* if bank has any level sensitive GPIO pin interrupt
929 configured, we must unmask the bank interrupt only after
930 handler(s) are executed in order to avoid spurious bank
934 chained_irq_exit(chip, desc);
937 static void gpio_irq_shutdown(struct irq_data *d)
939 unsigned int gpio = d->irq - IH_GPIO_BASE;
940 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
943 spin_lock_irqsave(&bank->lock, flags);
944 _reset_gpio(bank, gpio);
945 spin_unlock_irqrestore(&bank->lock, flags);
948 static void gpio_ack_irq(struct irq_data *d)
950 unsigned int gpio = d->irq - IH_GPIO_BASE;
951 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
953 _clear_gpio_irqstatus(bank, gpio);
956 static void gpio_mask_irq(struct irq_data *d)
958 unsigned int gpio = d->irq - IH_GPIO_BASE;
959 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
962 spin_lock_irqsave(&bank->lock, flags);
963 _set_gpio_irqenable(bank, gpio, 0);
964 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
965 spin_unlock_irqrestore(&bank->lock, flags);
968 static void gpio_unmask_irq(struct irq_data *d)
970 unsigned int gpio = d->irq - IH_GPIO_BASE;
971 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
972 unsigned int irq_mask = GPIO_BIT(bank, gpio);
973 u32 trigger = irqd_get_trigger_type(d);
976 spin_lock_irqsave(&bank->lock, flags);
978 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
980 /* For level-triggered GPIOs, the clearing must be done after
981 * the HW source is cleared, thus after the handler has run */
982 if (bank->level_mask & irq_mask) {
983 _set_gpio_irqenable(bank, gpio, 0);
984 _clear_gpio_irqstatus(bank, gpio);
987 _set_gpio_irqenable(bank, gpio, 1);
988 spin_unlock_irqrestore(&bank->lock, flags);
991 static struct irq_chip gpio_irq_chip = {
993 .irq_shutdown = gpio_irq_shutdown,
994 .irq_ack = gpio_ack_irq,
995 .irq_mask = gpio_mask_irq,
996 .irq_unmask = gpio_unmask_irq,
997 .irq_set_type = gpio_irq_type,
998 .irq_set_wake = gpio_wake_enable,
1001 /*---------------------------------------------------------------------*/
1003 #ifdef CONFIG_ARCH_OMAP1
1005 /* MPUIO uses the always-on 32k clock */
1007 static void mpuio_ack_irq(struct irq_data *d)
1009 /* The ISR is reset automatically, so do nothing here. */
1012 static void mpuio_mask_irq(struct irq_data *d)
1014 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1015 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1017 _set_gpio_irqenable(bank, gpio, 0);
1020 static void mpuio_unmask_irq(struct irq_data *d)
1022 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1023 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1025 _set_gpio_irqenable(bank, gpio, 1);
1028 static struct irq_chip mpuio_irq_chip = {
1030 .irq_ack = mpuio_ack_irq,
1031 .irq_mask = mpuio_mask_irq,
1032 .irq_unmask = mpuio_unmask_irq,
1033 .irq_set_type = gpio_irq_type,
1034 #ifdef CONFIG_ARCH_OMAP16XX
1035 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1036 .irq_set_wake = gpio_wake_enable,
1041 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1044 #ifdef CONFIG_ARCH_OMAP16XX
1046 #include <linux/platform_device.h>
1048 static int omap_mpuio_suspend_noirq(struct device *dev)
1050 struct platform_device *pdev = to_platform_device(dev);
1051 struct gpio_bank *bank = platform_get_drvdata(pdev);
1052 void __iomem *mask_reg = bank->base +
1053 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1054 unsigned long flags;
1056 spin_lock_irqsave(&bank->lock, flags);
1057 bank->saved_wakeup = __raw_readl(mask_reg);
1058 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1059 spin_unlock_irqrestore(&bank->lock, flags);
1064 static int omap_mpuio_resume_noirq(struct device *dev)
1066 struct platform_device *pdev = to_platform_device(dev);
1067 struct gpio_bank *bank = platform_get_drvdata(pdev);
1068 void __iomem *mask_reg = bank->base +
1069 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1070 unsigned long flags;
1072 spin_lock_irqsave(&bank->lock, flags);
1073 __raw_writel(bank->saved_wakeup, mask_reg);
1074 spin_unlock_irqrestore(&bank->lock, flags);
1079 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1080 .suspend_noirq = omap_mpuio_suspend_noirq,
1081 .resume_noirq = omap_mpuio_resume_noirq,
1084 /* use platform_driver for this. */
1085 static struct platform_driver omap_mpuio_driver = {
1088 .pm = &omap_mpuio_dev_pm_ops,
1092 static struct platform_device omap_mpuio_device = {
1096 .driver = &omap_mpuio_driver.driver,
1098 /* could list the /proc/iomem resources */
1101 static inline void mpuio_init(void)
1103 struct gpio_bank *bank = &gpio_bank[0];
1104 platform_set_drvdata(&omap_mpuio_device, bank);
1106 if (platform_driver_register(&omap_mpuio_driver) == 0)
1107 (void) platform_device_register(&omap_mpuio_device);
1111 static inline void mpuio_init(void) {}
1116 extern struct irq_chip mpuio_irq_chip;
1118 #define bank_is_mpuio(bank) 0
1119 static inline void mpuio_init(void) {}
1123 /*---------------------------------------------------------------------*/
1125 /* REVISIT these are stupid implementations! replace by ones that
1126 * don't switch on METHOD_* and which mostly avoid spinlocks
1129 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1131 struct gpio_bank *bank;
1132 unsigned long flags;
1134 bank = container_of(chip, struct gpio_bank, chip);
1135 spin_lock_irqsave(&bank->lock, flags);
1136 _set_gpio_direction(bank, offset, 1);
1137 spin_unlock_irqrestore(&bank->lock, flags);
1141 static int gpio_is_input(struct gpio_bank *bank, int mask)
1143 void __iomem *reg = bank->base + bank->regs->direction;
1145 return __raw_readl(reg) & mask;
1148 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1150 struct gpio_bank *bank;
1155 gpio = chip->base + offset;
1156 bank = container_of(chip, struct gpio_bank, chip);
1158 mask = GPIO_BIT(bank, gpio);
1160 if (gpio_is_input(bank, mask))
1161 return _get_gpio_datain(bank, gpio);
1163 return _get_gpio_dataout(bank, gpio);
1166 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1168 struct gpio_bank *bank;
1169 unsigned long flags;
1171 bank = container_of(chip, struct gpio_bank, chip);
1172 spin_lock_irqsave(&bank->lock, flags);
1173 bank->set_dataout(bank, offset, value);
1174 _set_gpio_direction(bank, offset, 0);
1175 spin_unlock_irqrestore(&bank->lock, flags);
1179 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1182 struct gpio_bank *bank;
1183 unsigned long flags;
1185 bank = container_of(chip, struct gpio_bank, chip);
1188 bank->dbck = clk_get(bank->dev, "dbclk");
1189 if (IS_ERR(bank->dbck))
1190 dev_err(bank->dev, "Could not get gpio dbck\n");
1193 spin_lock_irqsave(&bank->lock, flags);
1194 _set_gpio_debounce(bank, offset, debounce);
1195 spin_unlock_irqrestore(&bank->lock, flags);
1200 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1202 struct gpio_bank *bank;
1203 unsigned long flags;
1205 bank = container_of(chip, struct gpio_bank, chip);
1206 spin_lock_irqsave(&bank->lock, flags);
1207 bank->set_dataout(bank, offset, value);
1208 spin_unlock_irqrestore(&bank->lock, flags);
1211 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1213 struct gpio_bank *bank;
1215 bank = container_of(chip, struct gpio_bank, chip);
1216 return bank->virtual_irq_start + offset;
1219 /*---------------------------------------------------------------------*/
1221 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1225 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1226 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1227 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1228 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1229 else if (cpu_is_omap44xx())
1230 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1234 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1235 (rev >> 4) & 0x0f, rev & 0x0f);
1238 /* This lock class tells lockdep that GPIO irqs are in a different
1239 * category than their parents, so it won't report false recursion.
1241 static struct lock_class_key gpio_lock_class;
1243 static inline int init_gpio_info(struct platform_device *pdev)
1245 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1246 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1249 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1255 /* TODO: Cleanup cpu_is_* checks */
1256 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1258 if (cpu_class_is_omap2()) {
1259 if (cpu_is_omap44xx()) {
1260 __raw_writel(0xffffffff, bank->base +
1261 OMAP4_GPIO_IRQSTATUSCLR0);
1262 __raw_writel(0x00000000, bank->base +
1263 OMAP4_GPIO_DEBOUNCENABLE);
1264 /* Initialize interface clk ungated, module enabled */
1265 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1266 } else if (cpu_is_omap34xx()) {
1267 __raw_writel(0x00000000, bank->base +
1268 OMAP24XX_GPIO_IRQENABLE1);
1269 __raw_writel(0xffffffff, bank->base +
1270 OMAP24XX_GPIO_IRQSTATUS1);
1271 __raw_writel(0x00000000, bank->base +
1272 OMAP24XX_GPIO_DEBOUNCE_EN);
1274 /* Initialize interface clk ungated, module enabled */
1275 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1276 } else if (cpu_is_omap24xx()) {
1277 static const u32 non_wakeup_gpios[] = {
1278 0xe203ffc0, 0x08700040
1280 if (id < ARRAY_SIZE(non_wakeup_gpios))
1281 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1283 } else if (cpu_class_is_omap1()) {
1284 if (bank_is_mpuio(bank))
1285 __raw_writew(0xffff, bank->base +
1286 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1287 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1288 __raw_writew(0xffff, bank->base
1289 + OMAP1510_GPIO_INT_MASK);
1290 __raw_writew(0x0000, bank->base
1291 + OMAP1510_GPIO_INT_STATUS);
1293 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1294 __raw_writew(0x0000, bank->base
1295 + OMAP1610_GPIO_IRQENABLE1);
1296 __raw_writew(0xffff, bank->base
1297 + OMAP1610_GPIO_IRQSTATUS1);
1298 __raw_writew(0x0014, bank->base
1299 + OMAP1610_GPIO_SYSCONFIG);
1302 * Enable system clock for GPIO module.
1303 * The CAM_CLK_CTRL *is* really the right place.
1305 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1308 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1309 __raw_writel(0xffffffff, bank->base
1310 + OMAP7XX_GPIO_INT_MASK);
1311 __raw_writel(0x00000000, bank->base
1312 + OMAP7XX_GPIO_INT_STATUS);
1317 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1322 bank->mod_usage = 0;
1324 * REVISIT eventually switch from OMAP-specific gpio structs
1325 * over to the generic ones
1327 bank->chip.request = omap_gpio_request;
1328 bank->chip.free = omap_gpio_free;
1329 bank->chip.direction_input = gpio_input;
1330 bank->chip.get = gpio_get;
1331 bank->chip.direction_output = gpio_output;
1332 bank->chip.set_debounce = gpio_debounce;
1333 bank->chip.set = gpio_set;
1334 bank->chip.to_irq = gpio_2irq;
1335 if (bank_is_mpuio(bank)) {
1336 bank->chip.label = "mpuio";
1337 #ifdef CONFIG_ARCH_OMAP16XX
1338 bank->chip.dev = &omap_mpuio_device.dev;
1340 bank->chip.base = OMAP_MPUIO(0);
1342 bank->chip.label = "gpio";
1343 bank->chip.base = gpio;
1344 gpio += bank->width;
1346 bank->chip.ngpio = bank->width;
1348 gpiochip_add(&bank->chip);
1350 for (j = bank->virtual_irq_start;
1351 j < bank->virtual_irq_start + bank->width; j++) {
1352 irq_set_lockdep_class(j, &gpio_lock_class);
1353 irq_set_chip_data(j, bank);
1354 if (bank_is_mpuio(bank))
1355 irq_set_chip(j, &mpuio_irq_chip);
1357 irq_set_chip(j, &gpio_irq_chip);
1358 irq_set_handler(j, handle_simple_irq);
1359 set_irq_flags(j, IRQF_VALID);
1361 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1362 irq_set_handler_data(bank->irq, bank);
1365 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1367 static int gpio_init_done;
1368 struct omap_gpio_platform_data *pdata;
1369 struct resource *res;
1371 struct gpio_bank *bank;
1373 if (!pdev->dev.platform_data)
1376 pdata = pdev->dev.platform_data;
1378 if (!gpio_init_done) {
1381 ret = init_gpio_info(pdev);
1387 bank = &gpio_bank[id];
1389 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1390 if (unlikely(!res)) {
1391 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1395 bank->irq = res->start;
1396 bank->virtual_irq_start = pdata->virtual_irq_start;
1397 bank->method = pdata->bank_type;
1398 bank->dev = &pdev->dev;
1399 bank->dbck_flag = pdata->dbck_flag;
1400 bank->stride = pdata->bank_stride;
1401 bank->width = pdata->bank_width;
1403 bank->regs = pdata->regs;
1405 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1406 bank->set_dataout = _set_gpio_dataout_reg;
1408 bank->set_dataout = _set_gpio_dataout_mask;
1410 spin_lock_init(&bank->lock);
1412 /* Static mapping, never released */
1413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1414 if (unlikely(!res)) {
1415 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1419 bank->base = ioremap(res->start, resource_size(res));
1421 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1425 pm_runtime_enable(bank->dev);
1426 pm_runtime_get_sync(bank->dev);
1428 omap_gpio_mod_init(bank, id);
1429 omap_gpio_chip_init(bank);
1430 omap_gpio_show_rev(bank);
1432 if (!gpio_init_done)
1438 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1439 static int omap_gpio_suspend(void)
1443 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1446 for (i = 0; i < gpio_bank_count; i++) {
1447 struct gpio_bank *bank = &gpio_bank[i];
1448 void __iomem *wake_status;
1449 void __iomem *wake_clear;
1450 void __iomem *wake_set;
1451 unsigned long flags;
1453 switch (bank->method) {
1454 #ifdef CONFIG_ARCH_OMAP16XX
1455 case METHOD_GPIO_1610:
1456 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1457 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1458 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1461 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1462 case METHOD_GPIO_24XX:
1463 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1464 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1465 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1468 #ifdef CONFIG_ARCH_OMAP4
1469 case METHOD_GPIO_44XX:
1470 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1471 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1472 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1479 spin_lock_irqsave(&bank->lock, flags);
1480 bank->saved_wakeup = __raw_readl(wake_status);
1481 __raw_writel(0xffffffff, wake_clear);
1482 __raw_writel(bank->suspend_wakeup, wake_set);
1483 spin_unlock_irqrestore(&bank->lock, flags);
1489 static void omap_gpio_resume(void)
1493 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1496 for (i = 0; i < gpio_bank_count; i++) {
1497 struct gpio_bank *bank = &gpio_bank[i];
1498 void __iomem *wake_clear;
1499 void __iomem *wake_set;
1500 unsigned long flags;
1502 switch (bank->method) {
1503 #ifdef CONFIG_ARCH_OMAP16XX
1504 case METHOD_GPIO_1610:
1505 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1506 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1509 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1510 case METHOD_GPIO_24XX:
1511 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1512 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1515 #ifdef CONFIG_ARCH_OMAP4
1516 case METHOD_GPIO_44XX:
1517 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1518 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1525 spin_lock_irqsave(&bank->lock, flags);
1526 __raw_writel(0xffffffff, wake_clear);
1527 __raw_writel(bank->saved_wakeup, wake_set);
1528 spin_unlock_irqrestore(&bank->lock, flags);
1532 static struct syscore_ops omap_gpio_syscore_ops = {
1533 .suspend = omap_gpio_suspend,
1534 .resume = omap_gpio_resume,
1539 #ifdef CONFIG_ARCH_OMAP2PLUS
1541 static int workaround_enabled;
1543 void omap2_gpio_prepare_for_idle(int off_mode)
1548 if (cpu_is_omap34xx())
1551 for (i = min; i < gpio_bank_count; i++) {
1552 struct gpio_bank *bank = &gpio_bank[i];
1556 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1557 clk_disable(bank->dbck);
1562 /* If going to OFF, remove triggering for all
1563 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1564 * generated. See OMAP2420 Errata item 1.101. */
1565 if (!(bank->enabled_non_wakeup_gpios))
1568 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1569 bank->saved_datain = __raw_readl(bank->base +
1570 OMAP24XX_GPIO_DATAIN);
1571 l1 = __raw_readl(bank->base +
1572 OMAP24XX_GPIO_FALLINGDETECT);
1573 l2 = __raw_readl(bank->base +
1574 OMAP24XX_GPIO_RISINGDETECT);
1577 if (cpu_is_omap44xx()) {
1578 bank->saved_datain = __raw_readl(bank->base +
1580 l1 = __raw_readl(bank->base +
1581 OMAP4_GPIO_FALLINGDETECT);
1582 l2 = __raw_readl(bank->base +
1583 OMAP4_GPIO_RISINGDETECT);
1586 bank->saved_fallingdetect = l1;
1587 bank->saved_risingdetect = l2;
1588 l1 &= ~bank->enabled_non_wakeup_gpios;
1589 l2 &= ~bank->enabled_non_wakeup_gpios;
1591 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1592 __raw_writel(l1, bank->base +
1593 OMAP24XX_GPIO_FALLINGDETECT);
1594 __raw_writel(l2, bank->base +
1595 OMAP24XX_GPIO_RISINGDETECT);
1598 if (cpu_is_omap44xx()) {
1599 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1600 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1606 workaround_enabled = 0;
1609 workaround_enabled = 1;
1612 void omap2_gpio_resume_after_idle(void)
1617 if (cpu_is_omap34xx())
1619 for (i = min; i < gpio_bank_count; i++) {
1620 struct gpio_bank *bank = &gpio_bank[i];
1621 u32 l = 0, gen, gen0, gen1;
1624 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1625 clk_enable(bank->dbck);
1627 if (!workaround_enabled)
1630 if (!(bank->enabled_non_wakeup_gpios))
1633 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1634 __raw_writel(bank->saved_fallingdetect,
1635 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1636 __raw_writel(bank->saved_risingdetect,
1637 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1638 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1641 if (cpu_is_omap44xx()) {
1642 __raw_writel(bank->saved_fallingdetect,
1643 bank->base + OMAP4_GPIO_FALLINGDETECT);
1644 __raw_writel(bank->saved_risingdetect,
1645 bank->base + OMAP4_GPIO_RISINGDETECT);
1646 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1649 /* Check if any of the non-wakeup interrupt GPIOs have changed
1650 * state. If so, generate an IRQ by software. This is
1651 * horribly racy, but it's the best we can do to work around
1652 * this silicon bug. */
1653 l ^= bank->saved_datain;
1654 l &= bank->enabled_non_wakeup_gpios;
1657 * No need to generate IRQs for the rising edge for gpio IRQs
1658 * configured with falling edge only; and vice versa.
1660 gen0 = l & bank->saved_fallingdetect;
1661 gen0 &= bank->saved_datain;
1663 gen1 = l & bank->saved_risingdetect;
1664 gen1 &= ~(bank->saved_datain);
1666 /* FIXME: Consider GPIO IRQs with level detections properly! */
1667 gen = l & (~(bank->saved_fallingdetect) &
1668 ~(bank->saved_risingdetect));
1669 /* Consider all GPIO IRQs needed to be updated */
1675 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1676 old0 = __raw_readl(bank->base +
1677 OMAP24XX_GPIO_LEVELDETECT0);
1678 old1 = __raw_readl(bank->base +
1679 OMAP24XX_GPIO_LEVELDETECT1);
1680 __raw_writel(old0 | gen, bank->base +
1681 OMAP24XX_GPIO_LEVELDETECT0);
1682 __raw_writel(old1 | gen, bank->base +
1683 OMAP24XX_GPIO_LEVELDETECT1);
1684 __raw_writel(old0, bank->base +
1685 OMAP24XX_GPIO_LEVELDETECT0);
1686 __raw_writel(old1, bank->base +
1687 OMAP24XX_GPIO_LEVELDETECT1);
1690 if (cpu_is_omap44xx()) {
1691 old0 = __raw_readl(bank->base +
1692 OMAP4_GPIO_LEVELDETECT0);
1693 old1 = __raw_readl(bank->base +
1694 OMAP4_GPIO_LEVELDETECT1);
1695 __raw_writel(old0 | l, bank->base +
1696 OMAP4_GPIO_LEVELDETECT0);
1697 __raw_writel(old1 | l, bank->base +
1698 OMAP4_GPIO_LEVELDETECT1);
1699 __raw_writel(old0, bank->base +
1700 OMAP4_GPIO_LEVELDETECT0);
1701 __raw_writel(old1, bank->base +
1702 OMAP4_GPIO_LEVELDETECT1);
1711 #ifdef CONFIG_ARCH_OMAP3
1712 /* save the registers of bank 2-6 */
1713 void omap_gpio_save_context(void)
1717 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1718 for (i = 1; i < gpio_bank_count; i++) {
1719 struct gpio_bank *bank = &gpio_bank[i];
1720 gpio_context[i].irqenable1 =
1721 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1722 gpio_context[i].irqenable2 =
1723 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1724 gpio_context[i].wake_en =
1725 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1726 gpio_context[i].ctrl =
1727 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1728 gpio_context[i].oe =
1729 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1730 gpio_context[i].leveldetect0 =
1731 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1732 gpio_context[i].leveldetect1 =
1733 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1734 gpio_context[i].risingdetect =
1735 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1736 gpio_context[i].fallingdetect =
1737 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1738 gpio_context[i].dataout =
1739 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1743 /* restore the required registers of bank 2-6 */
1744 void omap_gpio_restore_context(void)
1748 for (i = 1; i < gpio_bank_count; i++) {
1749 struct gpio_bank *bank = &gpio_bank[i];
1750 __raw_writel(gpio_context[i].irqenable1,
1751 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1752 __raw_writel(gpio_context[i].irqenable2,
1753 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1754 __raw_writel(gpio_context[i].wake_en,
1755 bank->base + OMAP24XX_GPIO_WAKE_EN);
1756 __raw_writel(gpio_context[i].ctrl,
1757 bank->base + OMAP24XX_GPIO_CTRL);
1758 __raw_writel(gpio_context[i].oe,
1759 bank->base + OMAP24XX_GPIO_OE);
1760 __raw_writel(gpio_context[i].leveldetect0,
1761 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1762 __raw_writel(gpio_context[i].leveldetect1,
1763 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1764 __raw_writel(gpio_context[i].risingdetect,
1765 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1766 __raw_writel(gpio_context[i].fallingdetect,
1767 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1768 __raw_writel(gpio_context[i].dataout,
1769 bank->base + OMAP24XX_GPIO_DATAOUT);
1774 static struct platform_driver omap_gpio_driver = {
1775 .probe = omap_gpio_probe,
1777 .name = "omap_gpio",
1782 * gpio driver register needs to be done before
1783 * machine_init functions access gpio APIs.
1784 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1786 static int __init omap_gpio_drv_reg(void)
1788 return platform_driver_register(&omap_gpio_driver);
1790 postcore_initcall(omap_gpio_drv_reg);
1792 static int __init omap_gpio_sysinit(void)
1796 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1797 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1798 register_syscore_ops(&omap_gpio_syscore_ops);
1804 arch_initcall(omap_gpio_sysinit);