2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/basic_mmio_gpio.h>
30 #include <mach/hardware.h>
31 #include <asm-generic/bug.h>
33 struct mxc_gpio_port {
34 struct list_head node;
38 int virtual_irq_start;
39 struct bgpio_chip bgc;
44 * MX2 has one interrupt *for all* gpio ports. The list is used
45 * to save the references to all ports, so that mx2_gpio_irq_handler
46 * can walk through all interrupt status registers.
48 static LIST_HEAD(mxc_gpio_ports);
50 #define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
52 #define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
53 #define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
54 #define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
55 #define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
56 #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
57 #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
58 #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
60 #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
61 #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
62 #define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
63 #define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
64 #define GPIO_INT_NONE 0x4
66 /* Note: This driver assumes 32 GPIOs are handled in one register */
68 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
70 writel(1 << index, port->base + GPIO_ISR);
73 static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
78 l = readl(port->base + GPIO_IMR);
79 l = (l & (~(1 << index))) | (!!enable << index);
80 writel(l, port->base + GPIO_IMR);
83 static void gpio_ack_irq(struct irq_data *d)
85 struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
86 u32 gpio = irq_to_gpio(d->irq);
87 _clear_gpio_irqstatus(port, gpio & 0x1f);
90 static void gpio_mask_irq(struct irq_data *d)
92 struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
93 u32 gpio = irq_to_gpio(d->irq);
94 _set_gpio_irqenable(port, gpio & 0x1f, 0);
97 static void gpio_unmask_irq(struct irq_data *d)
99 struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
100 u32 gpio = irq_to_gpio(d->irq);
101 _set_gpio_irqenable(port, gpio & 0x1f, 1);
104 static int gpio_set_irq_type(struct irq_data *d, u32 type)
106 u32 gpio = irq_to_gpio(d->irq);
107 struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
110 void __iomem *reg = port->base;
112 port->both_edges &= ~(1 << (gpio & 31));
114 case IRQ_TYPE_EDGE_RISING:
115 edge = GPIO_INT_RISE_EDGE;
117 case IRQ_TYPE_EDGE_FALLING:
118 edge = GPIO_INT_FALL_EDGE;
120 case IRQ_TYPE_EDGE_BOTH:
121 val = gpio_get_value(gpio & 31);
123 edge = GPIO_INT_LOW_LEV;
124 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
126 edge = GPIO_INT_HIGH_LEV;
127 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
129 port->both_edges |= 1 << (gpio & 31);
131 case IRQ_TYPE_LEVEL_LOW:
132 edge = GPIO_INT_LOW_LEV;
134 case IRQ_TYPE_LEVEL_HIGH:
135 edge = GPIO_INT_HIGH_LEV;
141 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
143 val = readl(reg) & ~(0x3 << (bit << 1));
144 writel(val | (edge << (bit << 1)), reg);
145 _clear_gpio_irqstatus(port, gpio & 0x1f);
150 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
152 void __iomem *reg = port->base;
156 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
159 edge = (val >> (bit << 1)) & 3;
160 val &= ~(0x3 << (bit << 1));
161 if (edge == GPIO_INT_HIGH_LEV) {
162 edge = GPIO_INT_LOW_LEV;
163 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
164 } else if (edge == GPIO_INT_LOW_LEV) {
165 edge = GPIO_INT_HIGH_LEV;
166 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
168 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
172 writel(val | (edge << (bit << 1)), reg);
175 /* handle 32 interrupts in one status register */
176 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
178 u32 gpio_irq_no_base = port->virtual_irq_start;
180 while (irq_stat != 0) {
181 int irqoffset = fls(irq_stat) - 1;
183 if (port->both_edges & (1 << irqoffset))
184 mxc_flip_edge(port, irqoffset);
186 generic_handle_irq(gpio_irq_no_base + irqoffset);
188 irq_stat &= ~(1 << irqoffset);
192 /* MX1 and MX3 has one interrupt *per* gpio port */
193 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
196 struct mxc_gpio_port *port = irq_get_handler_data(irq);
198 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
200 mxc_gpio_irq_handler(port, irq_stat);
203 /* MX2 has one interrupt *for all* gpio ports */
204 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
206 u32 irq_msk, irq_stat;
207 struct mxc_gpio_port *port;
209 /* walk through all interrupt status registers */
210 list_for_each_entry(port, &mxc_gpio_ports, node) {
211 irq_msk = readl(port->base + GPIO_IMR);
215 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
217 mxc_gpio_irq_handler(port, irq_stat);
222 * Set interrupt number "irq" in the GPIO as a wake-up source.
223 * While system is running, all registered GPIO interrupts need to have
224 * wake-up enabled. When system is suspended, only selected GPIO interrupts
225 * need to have wake-up enabled.
226 * @param irq interrupt source number
227 * @param enable enable as wake-up if equal to non-zero
228 * @return This function returns 0 on success.
230 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
232 u32 gpio = irq_to_gpio(d->irq);
233 u32 gpio_idx = gpio & 0x1F;
234 struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
237 if (port->irq_high && (gpio_idx >= 16))
238 enable_irq_wake(port->irq_high);
240 enable_irq_wake(port->irq);
242 if (port->irq_high && (gpio_idx >= 16))
243 disable_irq_wake(port->irq_high);
245 disable_irq_wake(port->irq);
251 static struct irq_chip gpio_irq_chip = {
253 .irq_ack = gpio_ack_irq,
254 .irq_mask = gpio_mask_irq,
255 .irq_unmask = gpio_unmask_irq,
256 .irq_set_type = gpio_set_irq_type,
257 .irq_set_wake = gpio_set_wake_irq,
261 * This lock class tells lockdep that GPIO irqs are in a different
262 * category than their parents, so it won't report false recursion.
264 static struct lock_class_key gpio_lock_class;
266 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
268 struct mxc_gpio_port *port;
269 struct resource *iores;
272 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
276 port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32;
278 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284 if (!request_mem_region(iores->start, resource_size(iores),
290 port->base = ioremap(iores->start, resource_size(iores));
293 goto out_release_mem;
296 port->irq_high = platform_get_irq(pdev, 1);
297 port->irq = platform_get_irq(pdev, 0);
303 /* disable the interrupt and clear the status */
304 writel(0, port->base + GPIO_IMR);
305 writel(~0, port->base + GPIO_ISR);
307 for (i = port->virtual_irq_start;
308 i < port->virtual_irq_start + 32; i++) {
309 irq_set_lockdep_class(i, &gpio_lock_class);
310 irq_set_chip_and_handler(i, &gpio_irq_chip, handle_level_irq);
311 set_irq_flags(i, IRQF_VALID);
312 irq_set_chip_data(i, port);
316 /* setup one handler for all GPIO interrupts */
318 irq_set_chained_handler(port->irq,
319 mx2_gpio_irq_handler);
321 /* setup one handler for each entry */
322 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
323 irq_set_handler_data(port->irq, port);
324 if (port->irq_high > 0) {
325 /* setup handler for GPIO 16 to 31 */
326 irq_set_chained_handler(port->irq_high,
327 mx3_gpio_irq_handler);
328 irq_set_handler_data(port->irq_high, port);
332 err = bgpio_init(&port->bgc, &pdev->dev, 4,
333 port->base + GPIO_PSR,
334 port->base + GPIO_DR, NULL,
335 port->base + GPIO_GDIR, NULL, false);
339 port->bgc.gc.base = pdev->id * 32;
341 err = gpiochip_add(&port->bgc.gc);
343 goto out_bgpio_remove;
345 list_add_tail(&port->node, &mxc_gpio_ports);
350 bgpio_remove(&port->bgc);
354 release_mem_region(iores->start, resource_size(iores));
357 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
361 static struct platform_driver mxc_gpio_driver = {
364 .owner = THIS_MODULE,
366 .probe = mxc_gpio_probe,
369 static int __init gpio_mxc_init(void)
371 return platform_driver_register(&mxc_gpio_driver);
373 postcore_initcall(gpio_mxc_init);
375 MODULE_AUTHOR("Freescale Semiconductor, "
376 "Daniel Mack <danielncaiaq.de>, "
377 "Juergen Beisert <kernel@pengutronix.de>");
378 MODULE_DESCRIPTION("Freescale MXC GPIO");
379 MODULE_LICENSE("GPL");