2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/module.h>
37 #include <linux/gpio.h>
38 #include <linux/irq.h>
39 #include <linux/slab.h>
40 #include <linux/irqdomain.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_device.h>
44 #include <linux/platform_device.h>
45 #include <linux/pinctrl/consumer.h>
48 * GPIO unit register offsets.
50 #define GPIO_OUT_OFF 0x0000
51 #define GPIO_IO_CONF_OFF 0x0004
52 #define GPIO_BLINK_EN_OFF 0x0008
53 #define GPIO_IN_POL_OFF 0x000c
54 #define GPIO_DATA_IN_OFF 0x0010
55 #define GPIO_EDGE_CAUSE_OFF 0x0014
56 #define GPIO_EDGE_MASK_OFF 0x0018
57 #define GPIO_LEVEL_MASK_OFF 0x001c
59 /* The MV78200 has per-CPU registers for edge mask and level mask */
60 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
61 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
63 /* The Armada XP has per-CPU registers for interrupt cause, interrupt
64 * mask and interrupt level mask. Those are relative to the
66 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
67 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
68 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
70 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
71 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
72 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
74 #define MVEBU_MAX_GPIO_PER_BANK 32
76 struct mvebu_gpio_chip {
77 struct gpio_chip chip;
79 void __iomem *membase;
80 void __iomem *percpu_membase;
82 struct irq_domain *domain;
87 * Functions returning addresses of individual registers for a given
90 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
92 return mvchip->membase + GPIO_OUT_OFF;
95 static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
97 return mvchip->membase + GPIO_BLINK_EN_OFF;
100 static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
102 return mvchip->membase + GPIO_IO_CONF_OFF;
105 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
107 return mvchip->membase + GPIO_IN_POL_OFF;
110 static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
112 return mvchip->membase + GPIO_DATA_IN_OFF;
115 static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
119 switch(mvchip->soc_variant) {
120 case MVEBU_GPIO_SOC_VARIANT_ORION:
121 case MVEBU_GPIO_SOC_VARIANT_MV78200:
122 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
123 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
124 cpu = smp_processor_id();
125 return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
131 static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
135 switch(mvchip->soc_variant) {
136 case MVEBU_GPIO_SOC_VARIANT_ORION:
137 return mvchip->membase + GPIO_EDGE_MASK_OFF;
138 case MVEBU_GPIO_SOC_VARIANT_MV78200:
139 cpu = smp_processor_id();
140 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
141 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
142 cpu = smp_processor_id();
143 return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
149 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
153 switch(mvchip->soc_variant) {
154 case MVEBU_GPIO_SOC_VARIANT_ORION:
155 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
156 case MVEBU_GPIO_SOC_VARIANT_MV78200:
157 cpu = smp_processor_id();
158 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
159 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
160 cpu = smp_processor_id();
161 return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
168 * Functions implementing the gpio_chip methods
171 static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
173 return pinctrl_request_gpio(chip->base + pin);
176 static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
178 pinctrl_free_gpio(chip->base + pin);
181 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
183 struct mvebu_gpio_chip *mvchip =
184 container_of(chip, struct mvebu_gpio_chip, chip);
188 spin_lock_irqsave(&mvchip->lock, flags);
189 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
194 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
195 spin_unlock_irqrestore(&mvchip->lock, flags);
198 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
200 struct mvebu_gpio_chip *mvchip =
201 container_of(chip, struct mvebu_gpio_chip, chip);
204 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
205 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
206 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
208 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
211 return (u >> pin) & 1;
214 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
216 struct mvebu_gpio_chip *mvchip =
217 container_of(chip, struct mvebu_gpio_chip, chip);
221 spin_lock_irqsave(&mvchip->lock, flags);
222 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
227 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
228 spin_unlock_irqrestore(&mvchip->lock, flags);
231 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
233 struct mvebu_gpio_chip *mvchip =
234 container_of(chip, struct mvebu_gpio_chip, chip);
239 /* Check with the pinctrl driver whether this pin is usable as
241 ret = pinctrl_gpio_direction_input(chip->base + pin);
245 spin_lock_irqsave(&mvchip->lock, flags);
246 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
248 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
249 spin_unlock_irqrestore(&mvchip->lock, flags);
254 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
257 struct mvebu_gpio_chip *mvchip =
258 container_of(chip, struct mvebu_gpio_chip, chip);
263 /* Check with the pinctrl driver whether this pin is usable as
265 ret = pinctrl_gpio_direction_output(chip->base + pin);
269 mvebu_gpio_blink(chip, pin, 0);
270 mvebu_gpio_set(chip, pin, value);
272 spin_lock_irqsave(&mvchip->lock, flags);
273 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
275 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
276 spin_unlock_irqrestore(&mvchip->lock, flags);
281 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
283 struct mvebu_gpio_chip *mvchip =
284 container_of(chip, struct mvebu_gpio_chip, chip);
285 return irq_create_mapping(mvchip->domain, pin);
289 * Functions implementing the irq_chip methods
291 static void mvebu_gpio_irq_ack(struct irq_data *d)
293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
294 struct mvebu_gpio_chip *mvchip = gc->private;
295 u32 mask = ~(1 << (d->irq - gc->irq_base));
298 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
302 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
304 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
305 struct mvebu_gpio_chip *mvchip = gc->private;
306 u32 mask = 1 << (d->irq - gc->irq_base);
309 gc->mask_cache &= ~mask;
310 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
314 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
316 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
317 struct mvebu_gpio_chip *mvchip = gc->private;
318 u32 mask = 1 << (d->irq - gc->irq_base);
321 gc->mask_cache |= mask;
322 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
326 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
328 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
329 struct mvebu_gpio_chip *mvchip = gc->private;
330 u32 mask = 1 << (d->irq - gc->irq_base);
333 gc->mask_cache &= ~mask;
334 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
338 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
340 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
341 struct mvebu_gpio_chip *mvchip = gc->private;
342 u32 mask = 1 << (d->irq - gc->irq_base);
345 gc->mask_cache |= mask;
346 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
350 /*****************************************************************************
353 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
354 * value of the line or the opposite value.
356 * Level IRQ handlers: DATA_IN is used directly as cause register.
357 * Interrupt are masked by LEVEL_MASK registers.
358 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
359 * Interrupt are masked by EDGE_MASK registers.
360 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
361 * the polarity to catch the next line transaction.
362 * This is a race condition that might not perfectly
363 * work on some use cases.
365 * Every eight GPIO lines are grouped (OR'ed) before going up to main
369 * data-in /--------| |-----| |----\
370 * -----| |----- ---- to main cause reg
371 * X \----------------| |----/
372 * polarity LEVEL mask
374 ****************************************************************************/
376 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
378 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
379 struct irq_chip_type *ct = irq_data_get_chip_type(d);
380 struct mvebu_gpio_chip *mvchip = gc->private;
386 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
391 type &= IRQ_TYPE_SENSE_MASK;
392 if (type == IRQ_TYPE_NONE)
395 /* Check if we need to change chip and handler */
396 if (!(ct->type & type))
397 if (irq_setup_alt_chip(d, type))
401 * Configure interrupt polarity.
404 case IRQ_TYPE_EDGE_RISING:
405 case IRQ_TYPE_LEVEL_HIGH:
406 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
408 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
410 case IRQ_TYPE_EDGE_FALLING:
411 case IRQ_TYPE_LEVEL_LOW:
412 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
414 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
416 case IRQ_TYPE_EDGE_BOTH: {
419 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
420 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
423 * set initial polarity based on current input level
425 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
427 u |= 1 << pin; /* falling */
429 u &= ~(1 << pin); /* rising */
430 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
437 static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
439 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
446 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
447 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
448 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
449 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
451 for (i = 0; i < mvchip->chip.ngpio; i++) {
454 irq = mvchip->irqbase + i;
456 if (!(cause & (1 << i)))
459 type = irqd_get_trigger_type(irq_get_irq_data(irq));
460 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
461 /* Swap polarity (race with GPIO line) */
464 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
466 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
468 generic_handle_irq(irq);
472 static struct platform_device_id mvebu_gpio_ids[] = {
474 .name = "orion-gpio",
476 .name = "mv78200-gpio",
478 .name = "armadaxp-gpio",
483 MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
485 static struct of_device_id mvebu_gpio_of_match[] = {
487 .compatible = "marvell,orion-gpio",
488 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
491 .compatible = "marvell,mv78200-gpio",
492 .data = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
495 .compatible = "marvell,armadaxp-gpio",
496 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
502 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
504 static int mvebu_gpio_probe(struct platform_device *pdev)
506 struct mvebu_gpio_chip *mvchip;
507 const struct of_device_id *match;
508 struct device_node *np = pdev->dev.of_node;
509 struct resource *res;
510 struct irq_chip_generic *gc;
511 struct irq_chip_type *ct;
516 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
518 soc_variant = (int) match->data;
520 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 dev_err(&pdev->dev, "Cannot get memory resource\n");
528 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
530 dev_err(&pdev->dev, "Cannot allocate memory\n");
534 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
535 dev_err(&pdev->dev, "Missing ngpios OF property\n");
539 id = of_alias_get_id(pdev->dev.of_node, "gpio");
541 dev_err(&pdev->dev, "Couldn't get OF id\n");
545 mvchip->soc_variant = soc_variant;
546 mvchip->chip.label = dev_name(&pdev->dev);
547 mvchip->chip.dev = &pdev->dev;
548 mvchip->chip.request = mvebu_gpio_request;
549 mvchip->chip.free = mvebu_gpio_free;
550 mvchip->chip.direction_input = mvebu_gpio_direction_input;
551 mvchip->chip.get = mvebu_gpio_get;
552 mvchip->chip.direction_output = mvebu_gpio_direction_output;
553 mvchip->chip.set = mvebu_gpio_set;
554 mvchip->chip.to_irq = mvebu_gpio_to_irq;
555 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
556 mvchip->chip.ngpio = ngpios;
557 mvchip->chip.can_sleep = 0;
559 mvchip->chip.of_node = np;
562 spin_lock_init(&mvchip->lock);
563 mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
564 if (! mvchip->membase) {
565 dev_err(&pdev->dev, "Cannot ioremap\n");
566 kfree(mvchip->chip.label);
570 /* The Armada XP has a second range of registers for the
571 * per-CPU registers */
572 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
573 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
575 dev_err(&pdev->dev, "Cannot get memory resource\n");
576 kfree(mvchip->chip.label);
580 mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
581 if (! mvchip->percpu_membase) {
582 dev_err(&pdev->dev, "Cannot ioremap\n");
583 kfree(mvchip->chip.label);
589 * Mask and clear GPIO interrupts.
591 switch(soc_variant) {
592 case MVEBU_GPIO_SOC_VARIANT_ORION:
593 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
594 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
595 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
597 case MVEBU_GPIO_SOC_VARIANT_MV78200:
598 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
599 for (cpu = 0; cpu < 2; cpu++) {
600 writel_relaxed(0, mvchip->membase +
601 GPIO_EDGE_MASK_MV78200_OFF(cpu));
602 writel_relaxed(0, mvchip->membase +
603 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
606 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
607 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
608 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
609 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
610 for (cpu = 0; cpu < 4; cpu++) {
611 writel_relaxed(0, mvchip->percpu_membase +
612 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
613 writel_relaxed(0, mvchip->percpu_membase +
614 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
615 writel_relaxed(0, mvchip->percpu_membase +
616 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
623 gpiochip_add(&mvchip->chip);
625 /* Some gpio controllers do not provide irq support */
626 if (!of_irq_count(np))
629 /* Setup the interrupt handlers. Each chip can have up to 4
630 * interrupt handlers, with each handler dealing with 8 GPIO
632 for (i = 0; i < 4; i++) {
634 irq = platform_get_irq(pdev, i);
637 irq_set_handler_data(irq, mvchip);
638 irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
641 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
642 if (mvchip->irqbase < 0) {
643 dev_err(&pdev->dev, "no irqs\n");
644 kfree(mvchip->chip.label);
648 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
649 mvchip->membase, handle_level_irq);
651 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
652 kfree(mvchip->chip.label);
656 gc->private = mvchip;
657 ct = &gc->chip_types[0];
658 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
659 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
660 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
661 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
662 ct->chip.name = mvchip->chip.label;
664 ct = &gc->chip_types[1];
665 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
666 ct->chip.irq_ack = mvebu_gpio_irq_ack;
667 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
668 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
669 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
670 ct->handler = handle_edge_irq;
671 ct->chip.name = mvchip->chip.label;
673 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
674 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
676 /* Setup irq domain on top of the generic chip. */
677 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
679 &irq_domain_simple_ops,
681 if (!mvchip->domain) {
682 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
684 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
685 IRQ_LEVEL | IRQ_NOPROBE);
687 kfree(mvchip->chip.label);
694 static struct platform_driver mvebu_gpio_driver = {
696 .name = "mvebu-gpio",
697 .owner = THIS_MODULE,
698 .of_match_table = mvebu_gpio_of_match,
700 .probe = mvebu_gpio_probe,
701 .id_table = mvebu_gpio_ids,
704 static int __init mvebu_gpio_init(void)
706 return platform_driver_register(&mvebu_gpio_driver);
708 postcore_initcall(mvebu_gpio_init);