2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <linux/acpi.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/spinlock.h>
18 #include <linux/of_gpio.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/property.h>
23 #include <linux/mod_devicetable.h>
24 #include <linux/slab.h>
25 #include <linux/irq.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/bitops.h>
28 #include <linux/interrupt.h>
30 #define MPC8XXX_GPIO_PINS 32
38 #define GPIO_ICR2 0x18
41 struct mpc8xxx_gpio_chip {
46 int (*direction_output)(struct gpio_chip *chip,
47 unsigned offset, int value);
49 struct irq_domain *irq;
54 * This hardware has a big endian bit assignment such that GPIO line 0 is
55 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
56 * This inline helper give the right bitmask for a certain line.
58 static inline u32 mpc_pin2mask(unsigned int offset)
60 return BIT(31 - offset);
63 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
64 * defined as output cannot be determined by reading GPDAT register,
65 * so we use shadow data register instead. The status of input pins
66 * is determined by reading GPDAT register.
68 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
72 u32 out_mask, out_shadow;
74 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
75 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
76 out_shadow = gc->bgpio_data & out_mask;
78 return !!((val | out_shadow) & mpc_pin2mask(gpio));
81 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
82 unsigned int gpio, int val)
84 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
85 /* GPIO 28..31 are input only on MPC5121 */
89 return mpc8xxx_gc->direction_output(gc, gpio, val);
92 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
93 unsigned int gpio, int val)
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
96 /* GPIO 0..3 are input only on MPC5125 */
100 return mpc8xxx_gc->direction_output(gc, gpio, val);
103 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
105 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
107 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
108 return irq_create_mapping(mpc8xxx_gc->irq, offset);
113 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
120 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
121 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
122 for_each_set_bit(i, &mask, 32)
123 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
128 static void mpc8xxx_irq_unmask(struct irq_data *d)
130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
138 | mpc_pin2mask(irqd_to_hwirq(d)));
140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
143 static void mpc8xxx_irq_mask(struct irq_data *d)
145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
149 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
151 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
152 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
153 & ~mpc_pin2mask(irqd_to_hwirq(d)));
155 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
158 static void mpc8xxx_irq_ack(struct irq_data *d)
160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
161 struct gpio_chip *gc = &mpc8xxx_gc->gc;
163 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
164 mpc_pin2mask(irqd_to_hwirq(d)));
167 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
169 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
170 struct gpio_chip *gc = &mpc8xxx_gc->gc;
174 case IRQ_TYPE_EDGE_FALLING:
175 case IRQ_TYPE_LEVEL_LOW:
176 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
177 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
178 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
179 | mpc_pin2mask(irqd_to_hwirq(d)));
180 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
183 case IRQ_TYPE_EDGE_BOTH:
184 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
185 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
186 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
187 & ~mpc_pin2mask(irqd_to_hwirq(d)));
188 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
198 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
200 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
201 struct gpio_chip *gc = &mpc8xxx_gc->gc;
202 unsigned long gpio = irqd_to_hwirq(d);
208 reg = mpc8xxx_gc->regs + GPIO_ICR;
209 shift = (15 - gpio) * 2;
211 reg = mpc8xxx_gc->regs + GPIO_ICR2;
212 shift = (15 - (gpio % 16)) * 2;
216 case IRQ_TYPE_EDGE_FALLING:
217 case IRQ_TYPE_LEVEL_LOW:
218 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
221 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
224 case IRQ_TYPE_EDGE_RISING:
225 case IRQ_TYPE_LEVEL_HIGH:
226 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
227 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
229 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
232 case IRQ_TYPE_EDGE_BOTH:
233 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
234 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
235 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
245 static struct irq_chip mpc8xxx_irq_chip = {
246 .name = "mpc8xxx-gpio",
247 .irq_unmask = mpc8xxx_irq_unmask,
248 .irq_mask = mpc8xxx_irq_mask,
249 .irq_ack = mpc8xxx_irq_ack,
250 /* this might get overwritten in mpc8xxx_probe() */
251 .irq_set_type = mpc8xxx_irq_set_type,
254 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
255 irq_hw_number_t hwirq)
257 irq_set_chip_data(irq, h->host_data);
258 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
263 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
264 .map = mpc8xxx_gpio_irq_map,
265 .xlate = irq_domain_xlate_twocell,
268 struct mpc8xxx_gpio_devtype {
269 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
270 int (*gpio_get)(struct gpio_chip *, unsigned int);
271 int (*irq_set_type)(struct irq_data *, unsigned int);
274 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
275 .gpio_dir_out = mpc5121_gpio_dir_out,
276 .irq_set_type = mpc512x_irq_set_type,
279 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
280 .gpio_dir_out = mpc5125_gpio_dir_out,
281 .irq_set_type = mpc512x_irq_set_type,
284 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
285 .gpio_get = mpc8572_gpio_get,
288 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
289 .irq_set_type = mpc8xxx_irq_set_type,
292 static const struct of_device_id mpc8xxx_gpio_ids[] = {
293 { .compatible = "fsl,mpc8349-gpio", },
294 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
295 { .compatible = "fsl,mpc8610-gpio", },
296 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
297 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
298 { .compatible = "fsl,pq3-gpio", },
299 { .compatible = "fsl,ls1028a-gpio", },
300 { .compatible = "fsl,ls1088a-gpio", },
301 { .compatible = "fsl,qoriq-gpio", },
305 static int mpc8xxx_probe(struct platform_device *pdev)
307 struct device_node *np = pdev->dev.of_node;
308 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
309 struct gpio_chip *gc;
310 const struct mpc8xxx_gpio_devtype *devtype = NULL;
311 struct fwnode_handle *fwnode;
314 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
318 platform_set_drvdata(pdev, mpc8xxx_gc);
320 raw_spin_lock_init(&mpc8xxx_gc->lock);
322 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
323 if (IS_ERR(mpc8xxx_gc->regs))
324 return PTR_ERR(mpc8xxx_gc->regs);
326 gc = &mpc8xxx_gc->gc;
327 gc->parent = &pdev->dev;
329 if (device_property_read_bool(&pdev->dev, "little-endian")) {
330 ret = bgpio_init(gc, &pdev->dev, 4,
331 mpc8xxx_gc->regs + GPIO_DAT,
333 mpc8xxx_gc->regs + GPIO_DIR, NULL,
337 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
339 ret = bgpio_init(gc, &pdev->dev, 4,
340 mpc8xxx_gc->regs + GPIO_DAT,
342 mpc8xxx_gc->regs + GPIO_DIR, NULL,
344 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
347 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
350 mpc8xxx_gc->direction_output = gc->direction_output;
352 devtype = device_get_match_data(&pdev->dev);
354 devtype = &mpc8xxx_gpio_devtype_default;
357 * It's assumed that only a single type of gpio controller is available
358 * on the current machine, so overwriting global data is fine.
360 if (devtype->irq_set_type)
361 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
363 if (devtype->gpio_dir_out)
364 gc->direction_output = devtype->gpio_dir_out;
365 if (devtype->gpio_get)
366 gc->get = devtype->gpio_get;
368 gc->to_irq = mpc8xxx_gpio_to_irq;
371 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
372 * the input enable of each individual GPIO port. When an individual
373 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
374 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
375 * the port value to the GPIO Data Register.
377 fwnode = dev_fwnode(&pdev->dev);
378 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
379 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
380 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
381 is_acpi_node(fwnode))
382 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
384 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
387 "GPIO chip registration failed with status %d\n", ret);
391 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
392 if (mpc8xxx_gc->irqn < 0)
393 return mpc8xxx_gc->irqn;
395 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
397 &mpc8xxx_gpio_irq_ops,
400 if (!mpc8xxx_gc->irq)
403 /* ack and mask all irqs */
404 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
405 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
407 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
408 mpc8xxx_gpio_irq_cascade,
409 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
413 "failed to devm_request_irq(%d), ret = %d\n",
414 mpc8xxx_gc->irqn, ret);
420 irq_domain_remove(mpc8xxx_gc->irq);
424 static int mpc8xxx_remove(struct platform_device *pdev)
426 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
428 if (mpc8xxx_gc->irq) {
429 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
430 irq_domain_remove(mpc8xxx_gc->irq);
437 static const struct acpi_device_id gpio_acpi_ids[] = {
441 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
444 static struct platform_driver mpc8xxx_plat_driver = {
445 .probe = mpc8xxx_probe,
446 .remove = mpc8xxx_remove,
448 .name = "gpio-mpc8xxx",
449 .of_match_table = mpc8xxx_gpio_ids,
450 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
454 static int __init mpc8xxx_init(void)
456 return platform_driver_register(&mpc8xxx_plat_driver);
459 arch_initcall(mpc8xxx_init);