1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic driver for memory-mapped GPIO controllers.
5 * Copyright 2008 MontaVista Software, Inc.
6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
18 `....trivial..'~`.```.```
20 * .```````~~~~`..`.``.``.
21 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
25 * ``.`.``...``` ```.. output pins are also supported.`
26 * ^^ `````.`````````.,``~``~``~~``````
28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
32 * ..````````......``````````` \o_
36 * ...`````~~`.....``.`..........``````.`.``.```........``.
37 * ` 8, 16, 32 and 64 bits registers are supported, and``.
38 * . the number of GPIOs is determined by the width of ~
39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
43 #include <linux/init.h>
44 #include <linux/err.h>
45 #include <linux/bug.h>
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/spinlock.h>
49 #include <linux/compiler.h>
50 #include <linux/types.h>
51 #include <linux/errno.h>
52 #include <linux/log2.h>
53 #include <linux/ioport.h>
55 #include <linux/gpio/driver.h>
56 #include <linux/slab.h>
57 #include <linux/bitops.h>
58 #include <linux/platform_device.h>
59 #include <linux/mod_devicetable.h>
61 #include <linux/of_device.h>
65 static void bgpio_write8(void __iomem *reg, unsigned long data)
70 static unsigned long bgpio_read8(void __iomem *reg)
75 static void bgpio_write16(void __iomem *reg, unsigned long data)
80 static unsigned long bgpio_read16(void __iomem *reg)
85 static void bgpio_write32(void __iomem *reg, unsigned long data)
90 static unsigned long bgpio_read32(void __iomem *reg)
95 #if BITS_PER_LONG >= 64
96 static void bgpio_write64(void __iomem *reg, unsigned long data)
101 static unsigned long bgpio_read64(void __iomem *reg)
105 #endif /* BITS_PER_LONG >= 64 */
107 static void bgpio_write16be(void __iomem *reg, unsigned long data)
109 iowrite16be(data, reg);
112 static unsigned long bgpio_read16be(void __iomem *reg)
114 return ioread16be(reg);
117 static void bgpio_write32be(void __iomem *reg, unsigned long data)
119 iowrite32be(data, reg);
122 static unsigned long bgpio_read32be(void __iomem *reg)
124 return ioread32be(reg);
127 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
130 return BIT(gc->bgpio_bits - 1 - line);
134 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
136 unsigned long pinmask = bgpio_line2mask(gc, gpio);
137 bool dir = !!(gc->bgpio_dir & pinmask);
140 return !!(gc->read_reg(gc->reg_set) & pinmask);
142 return !!(gc->read_reg(gc->reg_dat) & pinmask);
146 * This assumes that the bits in the GPIO register are in native endianness.
147 * We only assign the function pointer if we have that.
149 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
152 unsigned long get_mask = 0;
153 unsigned long set_mask = 0;
155 /* Make sure we first clear any bits that are zero when we read the register */
158 set_mask = *mask & gc->bgpio_dir;
159 get_mask = *mask & ~gc->bgpio_dir;
162 *bits |= gc->read_reg(gc->reg_set) & set_mask;
164 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
169 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
171 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
175 * This only works if the bits in the GPIO register are in native endianness.
177 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
180 /* Make sure we first clear any bits that are zero when we read the register */
182 *bits |= gc->read_reg(gc->reg_dat) & *mask;
187 * With big endian mirrored bit order it becomes more tedious.
189 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
192 unsigned long readmask = 0;
196 /* Make sure we first clear any bits that are zero when we read the register */
199 /* Create a mirrored mask */
200 for_each_set_bit(bit, mask, gc->ngpio)
201 readmask |= bgpio_line2mask(gc, bit);
203 /* Read the register */
204 val = gc->read_reg(gc->reg_dat) & readmask;
207 * Mirror the result into the "bits" result, this will give line 0
208 * in bit 0 ... line 31 in bit 31 for a 32bit register.
210 for_each_set_bit(bit, &val, gc->ngpio)
211 *bits |= bgpio_line2mask(gc, bit);
216 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
220 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
222 unsigned long mask = bgpio_line2mask(gc, gpio);
225 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
228 gc->bgpio_data |= mask;
230 gc->bgpio_data &= ~mask;
232 gc->write_reg(gc->reg_dat, gc->bgpio_data);
234 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237 static void bgpio_set_direct(struct gpio_chip *gc, unsigned int gpio, int val)
239 unsigned long mask = bgpio_line2mask(gc, gpio);
242 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
244 gc->bgpio_data = gc->read_reg(gc->reg_dat);
247 gc->bgpio_data |= mask;
249 gc->bgpio_data &= ~mask;
251 gc->write_reg(gc->reg_dat, gc->bgpio_data);
253 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
256 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
259 unsigned long mask = bgpio_line2mask(gc, gpio);
262 gc->write_reg(gc->reg_set, mask);
264 gc->write_reg(gc->reg_clr, mask);
267 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
269 unsigned long mask = bgpio_line2mask(gc, gpio);
272 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
275 gc->bgpio_data |= mask;
277 gc->bgpio_data &= ~mask;
279 gc->write_reg(gc->reg_set, gc->bgpio_data);
281 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
284 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
285 unsigned long *mask, unsigned long *bits,
286 unsigned long *set_mask,
287 unsigned long *clear_mask)
294 for_each_set_bit(i, mask, gc->bgpio_bits) {
295 if (test_bit(i, bits))
296 *set_mask |= bgpio_line2mask(gc, i);
298 *clear_mask |= bgpio_line2mask(gc, i);
302 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
308 unsigned long set_mask, clear_mask;
310 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
312 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
314 gc->bgpio_data |= set_mask;
315 gc->bgpio_data &= ~clear_mask;
317 gc->write_reg(reg, gc->bgpio_data);
319 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
322 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
325 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
328 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
331 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
334 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
338 unsigned long set_mask, clear_mask;
340 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
343 gc->write_reg(gc->reg_set, set_mask);
345 gc->write_reg(gc->reg_clr, clear_mask);
348 static void bgpio_set_multiple_direct(struct gpio_chip *gc,
353 unsigned long set_mask, clear_mask;
355 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
357 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
359 gc->bgpio_data = gc->read_reg(gc->reg_dat);
361 gc->bgpio_data |= set_mask;
362 gc->bgpio_data &= ~clear_mask;
364 gc->write_reg(gc->reg_dat, gc->bgpio_data);
366 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
369 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
374 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
380 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
383 gc->set(gc, gpio, val);
388 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
392 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
394 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
397 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
399 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
401 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
406 static int bgpio_dir_in_direct(struct gpio_chip *gc, unsigned int gpio)
410 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
413 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
415 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
417 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
420 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
422 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
424 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
429 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
431 /* Return 0 if output, 1 if input */
432 if (gc->bgpio_dir_unreadable) {
433 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
434 return GPIO_LINE_DIRECTION_OUT;
435 return GPIO_LINE_DIRECTION_IN;
438 if (gc->reg_dir_out) {
439 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
440 return GPIO_LINE_DIRECTION_OUT;
441 return GPIO_LINE_DIRECTION_IN;
445 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
446 return GPIO_LINE_DIRECTION_OUT;
448 return GPIO_LINE_DIRECTION_IN;
451 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
455 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
457 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
460 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
462 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
464 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
467 static void bgpio_dir_out_direct(struct gpio_chip *gc, unsigned int gpio,
472 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
475 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
477 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
479 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
482 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
484 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
486 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
489 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
492 bgpio_dir_out(gc, gpio, val);
493 gc->set(gc, gpio, val);
497 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
500 gc->set(gc, gpio, val);
501 bgpio_dir_out(gc, gpio, val);
505 static int bgpio_dir_out_dir_first_direct(struct gpio_chip *gc,
506 unsigned int gpio, int val)
508 bgpio_dir_out_direct(gc, gpio, val);
509 gc->set(gc, gpio, val);
513 static int bgpio_dir_out_val_first_direct(struct gpio_chip *gc,
514 unsigned int gpio, int val)
516 gc->set(gc, gpio, val);
517 bgpio_dir_out_direct(gc, gpio, val);
521 static int bgpio_setup_accessors(struct device *dev,
522 struct gpio_chip *gc,
526 switch (gc->bgpio_bits) {
528 gc->read_reg = bgpio_read8;
529 gc->write_reg = bgpio_write8;
533 gc->read_reg = bgpio_read16be;
534 gc->write_reg = bgpio_write16be;
536 gc->read_reg = bgpio_read16;
537 gc->write_reg = bgpio_write16;
542 gc->read_reg = bgpio_read32be;
543 gc->write_reg = bgpio_write32be;
545 gc->read_reg = bgpio_read32;
546 gc->write_reg = bgpio_write32;
549 #if BITS_PER_LONG >= 64
553 "64 bit big endian byte order unsupported\n");
556 gc->read_reg = bgpio_read64;
557 gc->write_reg = bgpio_write64;
560 #endif /* BITS_PER_LONG >= 64 */
562 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
570 * Create the device and allocate the resources. For setting GPIO's there are
571 * three supported configurations:
573 * - single input/output register resource (named "dat").
574 * - set/clear pair (named "set" and "clr").
575 * - single output register resource and single input resource ("set" and
578 * For the single output register, this drives a 1 by setting a bit and a zero
579 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
580 * in the set register and clears it by setting a bit in the clear register.
581 * The configuration is detected by which resources are present.
583 * For setting the GPIO direction, there are three supported configurations:
585 * - simple bidirection GPIO that requires no configuration.
586 * - an output direction register (named "dirout") where a 1 bit
587 * indicates the GPIO is an output.
588 * - an input direction register (named "dirin") where a 1 bit indicates
589 * the GPIO is an input.
591 static int bgpio_setup_io(struct gpio_chip *gc,
605 gc->set = bgpio_set_with_clear;
606 gc->set_multiple = bgpio_set_multiple_with_clear;
607 } else if (set && !clr) {
609 gc->set = bgpio_set_set;
610 gc->set_multiple = bgpio_set_multiple_set;
611 } else if (flags & BGPIOF_NO_OUTPUT) {
612 gc->set = bgpio_set_none;
613 gc->set_multiple = NULL;
614 } else if (flags & BGPIOF_REG_DIRECT) {
615 gc->set = bgpio_set_direct;
616 gc->set_multiple = bgpio_set_multiple_direct;
619 gc->set_multiple = bgpio_set_multiple;
622 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
623 (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
624 gc->get = bgpio_get_set;
626 gc->get_multiple = bgpio_get_set_multiple;
628 * We deliberately avoid assigning the ->get_multiple() call
629 * for big endian mirrored registers which are ALSO reflecting
630 * their value in the set register when used as output. It is
631 * simply too much complexity, let the GPIO core fall back to
632 * reading each line individually in that fringe case.
637 gc->get_multiple = bgpio_get_multiple_be;
639 gc->get_multiple = bgpio_get_multiple;
645 static int bgpio_setup_direction(struct gpio_chip *gc,
646 void __iomem *dirout,
650 if (dirout || dirin) {
651 gc->reg_dir_out = dirout;
652 gc->reg_dir_in = dirin;
653 if (flags & BGPIOF_REG_DIRECT) {
654 if (flags & BGPIOF_NO_SET_ON_INPUT)
655 gc->direction_output =
656 bgpio_dir_out_dir_first_direct;
658 gc->direction_output =
659 bgpio_dir_out_val_first_direct;
660 gc->direction_input = bgpio_dir_in_direct;
662 if (flags & BGPIOF_NO_SET_ON_INPUT)
663 gc->direction_output = bgpio_dir_out_dir_first;
665 gc->direction_output = bgpio_dir_out_val_first;
666 gc->direction_input = bgpio_dir_in;
668 gc->get_direction = bgpio_get_dir;
670 if (flags & BGPIOF_NO_OUTPUT)
671 gc->direction_output = bgpio_dir_out_err;
673 gc->direction_output = bgpio_simple_dir_out;
674 gc->direction_input = bgpio_simple_dir_in;
680 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
682 if (gpio_pin < chip->ngpio)
689 * bgpio_init() - Initialize generic GPIO accessor functions
690 * @gc: the GPIO chip to set up
691 * @dev: the parent device of the new GPIO chip (compulsory)
692 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
693 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
694 * is expected that a 1 in the corresponding bit in this register means the
696 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
697 * expected that we write the line with 1 in this register to drive the GPIO line
699 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
700 * expected that we write the line with 1 in this register to drive the GPIO line
701 * low. It is allowed to leave this address as NULL, in that case the SET register
702 * will be assumed to also clear the GPIO lines, by actively writing the line
704 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
705 * that setting a line to 1 in this register will turn that line into an
706 * output line. Conversely, setting the line to 0 will turn that line into
708 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
709 * that setting a line to 1 in this register will turn that line into an
710 * input line. Conversely, setting the line to 0 will turn that line into
712 * @flags: Different flags that will affect the behaviour of the device, such as
715 int bgpio_init(struct gpio_chip *gc, struct device *dev,
716 unsigned long sz, void __iomem *dat, void __iomem *set,
717 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
722 if (!is_power_of_2(sz))
725 gc->bgpio_bits = sz * 8;
726 if (gc->bgpio_bits > BITS_PER_LONG)
729 raw_spin_lock_init(&gc->bgpio_lock);
731 gc->label = dev_name(dev);
733 gc->request = bgpio_request;
734 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
736 ret = gpiochip_get_ngpios(gc, dev);
738 gc->ngpio = gc->bgpio_bits;
740 gc->bgpio_bits = roundup_pow_of_two(round_up(gc->ngpio, 8));
742 ret = bgpio_setup_io(gc, dat, set, clr, flags);
746 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
750 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
754 gc->bgpio_data = gc->read_reg(gc->reg_dat);
755 if (gc->set == bgpio_set_set &&
756 !(flags & BGPIOF_UNREADABLE_REG_SET))
757 gc->bgpio_data = gc->read_reg(gc->reg_set);
759 if (flags & BGPIOF_UNREADABLE_REG_DIR)
760 gc->bgpio_dir_unreadable = true;
763 * Inspect hardware to find initial direction setting.
765 if ((gc->reg_dir_out || gc->reg_dir_in) &&
766 !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
768 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
769 else if (gc->reg_dir_in)
770 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
772 * If we have two direction registers, synchronise
773 * input setting to output setting, the library
774 * can not handle a line being input and output at
777 if (gc->reg_dir_out && gc->reg_dir_in)
778 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
783 EXPORT_SYMBOL_GPL(bgpio_init);
785 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
787 static void __iomem *bgpio_map(struct platform_device *pdev,
789 resource_size_t sane_sz)
794 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
798 sz = resource_size(r);
800 return IOMEM_ERR_PTR(-EINVAL);
802 return devm_ioremap_resource(&pdev->dev, r);
806 static const struct of_device_id bgpio_of_match[] = {
807 { .compatible = "brcm,bcm6345-gpio" },
808 { .compatible = "wd,mbl-gpio" },
809 { .compatible = "ni,169445-nand-gpio" },
812 MODULE_DEVICE_TABLE(of, bgpio_of_match);
814 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
815 unsigned long *flags)
817 struct bgpio_pdata *pdata;
819 if (!of_match_device(bgpio_of_match, &pdev->dev))
822 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
825 return ERR_PTR(-ENOMEM);
829 if (of_device_is_big_endian(pdev->dev.of_node))
830 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
832 if (of_property_read_bool(pdev->dev.of_node, "no-output"))
833 *flags |= BGPIOF_NO_OUTPUT;
838 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
839 unsigned long *flags)
843 #endif /* CONFIG_OF */
845 static int bgpio_pdev_probe(struct platform_device *pdev)
847 struct device *dev = &pdev->dev;
852 void __iomem *dirout;
855 unsigned long flags = 0;
857 struct gpio_chip *gc;
858 struct bgpio_pdata *pdata;
860 pdata = bgpio_parse_dt(pdev, &flags);
862 return PTR_ERR(pdata);
865 pdata = dev_get_platdata(dev);
866 flags = pdev->id_entry->driver_data;
869 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
873 sz = resource_size(r);
875 dat = bgpio_map(pdev, "dat", sz);
879 set = bgpio_map(pdev, "set", sz);
883 clr = bgpio_map(pdev, "clr", sz);
887 dirout = bgpio_map(pdev, "dirout", sz);
889 return PTR_ERR(dirout);
891 dirin = bgpio_map(pdev, "dirin", sz);
893 return PTR_ERR(dirin);
895 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
899 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
905 gc->label = pdata->label;
906 gc->base = pdata->base;
907 if (pdata->ngpio > 0)
908 gc->ngpio = pdata->ngpio;
911 platform_set_drvdata(pdev, gc);
913 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
916 static const struct platform_device_id bgpio_id_table[] = {
918 .name = "basic-mmio-gpio",
921 .name = "basic-mmio-gpio-be",
922 .driver_data = BGPIOF_BIG_ENDIAN,
926 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
928 static struct platform_driver bgpio_driver = {
930 .name = "basic-mmio-gpio",
931 .of_match_table = of_match_ptr(bgpio_of_match),
933 .id_table = bgpio_id_table,
934 .probe = bgpio_pdev_probe,
937 module_platform_driver(bgpio_driver);
939 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
941 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
942 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
943 MODULE_LICENSE("GPL");