drivers/gpio/gpio-lpc18xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * GPIO driver for NXP LPC18xx/43xx.
   4  *
   5  * Copyright (C) 2018 Vladimir Zapolskiy <vz@mleia.com>
   6  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
   7  *
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/io.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20
  21 /* LPC18xx GPIO register offsets */
  22 #define LPC18XX_REG_DIR(n)      (0x2000 + n * sizeof(u32))
  23
  24 #define LPC18XX_MAX_PORTS       8
  25 #define LPC18XX_PINS_PER_PORT   32
  26
  27 /* LPC18xx GPIO pin interrupt controller register offsets */
  28 #define LPC18XX_GPIO_PIN_IC_ISEL        0x00
  29 #define LPC18XX_GPIO_PIN_IC_IENR        0x04
  30 #define LPC18XX_GPIO_PIN_IC_SIENR       0x08
  31 #define LPC18XX_GPIO_PIN_IC_CIENR       0x0c
  32 #define LPC18XX_GPIO_PIN_IC_IENF        0x10
  33 #define LPC18XX_GPIO_PIN_IC_SIENF       0x14
  34 #define LPC18XX_GPIO_PIN_IC_CIENF       0x18
  35 #define LPC18XX_GPIO_PIN_IC_RISE        0x1c
  36 #define LPC18XX_GPIO_PIN_IC_FALL        0x20
  37 #define LPC18XX_GPIO_PIN_IC_IST         0x24
  38
  39 #define NR_LPC18XX_GPIO_PIN_IC_IRQS     8
  40
  41 struct lpc18xx_gpio_pin_ic {
  42         void __iomem *base;
  43         struct irq_domain *domain;
  44         struct raw_spinlock lock;
  45 };
  46
  47 struct lpc18xx_gpio_chip {
  48         struct gpio_chip gpio;
  49         void __iomem *base;
  50         struct clk *clk;
  51         struct lpc18xx_gpio_pin_ic *pin_ic;
  52         spinlock_t lock;
  53 };
  54
  55 static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic,
  56                                             u32 pin, bool set)
  57 {
  58         u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
  59
  60         if (set)
  61                 val &= ~BIT(pin);
  62         else
  63                 val |= BIT(pin);
  64
  65         writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL);
  66 }
  67
  68 static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic,
  69                                            u32 pin, u32 reg)
  70 {
  71         writel_relaxed(BIT(pin), ic->base + reg);
  72 }
  73
  74 static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d)
  75 {
  76         struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  77         u32 type = irqd_get_trigger_type(d);
  78
  79         raw_spin_lock(&ic->lock);
  80
  81         if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
  82                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  83                                         LPC18XX_GPIO_PIN_IC_CIENR);
  84
  85         if (type & IRQ_TYPE_EDGE_FALLING)
  86                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
  87                                         LPC18XX_GPIO_PIN_IC_CIENF);
  88
  89         raw_spin_unlock(&ic->lock);
  90
  91         irq_chip_mask_parent(d);
  92 }
  93
  94 static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d)
  95 {
  96         struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
  97         u32 type = irqd_get_trigger_type(d);
  98
  99         raw_spin_lock(&ic->lock);
 100
 101         if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING)
 102                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
 103                                         LPC18XX_GPIO_PIN_IC_SIENR);
 104
 105         if (type & IRQ_TYPE_EDGE_FALLING)
 106                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
 107                                         LPC18XX_GPIO_PIN_IC_SIENF);
 108
 109         raw_spin_unlock(&ic->lock);
 110
 111         irq_chip_unmask_parent(d);
 112 }
 113
 114 static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d)
 115 {
 116         struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
 117         u32 type = irqd_get_trigger_type(d);
 118
 119         raw_spin_lock(&ic->lock);
 120
 121         if (type & IRQ_TYPE_EDGE_BOTH)
 122                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
 123                                         LPC18XX_GPIO_PIN_IC_IST);
 124
 125         raw_spin_unlock(&ic->lock);
 126
 127         irq_chip_eoi_parent(d);
 128 }
 129
 130 static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type)
 131 {
 132         struct lpc18xx_gpio_pin_ic *ic = d->chip_data;
 133
 134         raw_spin_lock(&ic->lock);
 135
 136         if (type & IRQ_TYPE_LEVEL_HIGH) {
 137                 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
 138                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
 139                                         LPC18XX_GPIO_PIN_IC_SIENF);
 140         } else if (type & IRQ_TYPE_LEVEL_LOW) {
 141                 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true);
 142                 lpc18xx_gpio_pin_ic_set(ic, d->hwirq,
 143                                         LPC18XX_GPIO_PIN_IC_CIENF);
 144         } else {
 145                 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false);
 146         }
 147
 148         raw_spin_unlock(&ic->lock);
 149
 150         return 0;
 151 }
 152
 153 static struct irq_chip lpc18xx_gpio_pin_ic = {
 154         .name           = "LPC18xx GPIO pin",
 155         .irq_mask       = lpc18xx_gpio_pin_ic_mask,
 156         .irq_unmask     = lpc18xx_gpio_pin_ic_unmask,
 157         .irq_eoi        = lpc18xx_gpio_pin_ic_eoi,
 158         .irq_set_type   = lpc18xx_gpio_pin_ic_set_type,
 159         .flags          = IRQCHIP_SET_TYPE_MASKED,
 160 };
 161
 162 static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain,
 163                                             unsigned int virq,
 164                                             unsigned int nr_irqs, void *data)
 165 {
 166         struct irq_fwspec parent_fwspec, *fwspec = data;
 167         struct lpc18xx_gpio_pin_ic *ic = domain->host_data;
 168         irq_hw_number_t hwirq;
 169         int ret;
 170
 171         if (nr_irqs != 1)
 172                 return -EINVAL;
 173
 174         hwirq = fwspec->param[0];
 175         if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS)
 176                 return -EINVAL;
 177
 178         /*
 179          * All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated
 180          * into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC
 181          */
 182         parent_fwspec.fwnode = domain->parent->fwnode;
 183         parent_fwspec.param_count = 1;
 184         parent_fwspec.param[0] = hwirq + 32;
 185
 186         ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
 187         if (ret < 0) {
 188                 pr_err("failed to allocate parent irq %u: %d\n",
 189                        parent_fwspec.param[0], ret);
 190                 return ret;
 191         }
 192
 193         return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
 194                                              &lpc18xx_gpio_pin_ic, ic);
 195 }
 196
 197 static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = {
 198         .alloc  = lpc18xx_gpio_pin_ic_domain_alloc,
 199         .xlate  = irq_domain_xlate_twocell,
 200         .free   = irq_domain_free_irqs_common,
 201 };
 202
 203 static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc)
 204 {
 205         struct device *dev = gc->gpio.parent;
 206         struct irq_domain *parent_domain;
 207         struct device_node *parent_node;
 208         struct lpc18xx_gpio_pin_ic *ic;
 209         struct resource res;
 210         int ret, index;
 211
 212         parent_node = of_irq_find_parent(dev->of_node);
 213         if (!parent_node)
 214                 return -ENXIO;
 215
 216         parent_domain = irq_find_host(parent_node);
 217         of_node_put(parent_node);
 218         if (!parent_domain)
 219                 return -ENXIO;
 220
 221         ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL);
 222         if (!ic)
 223                 return -ENOMEM;
 224
 225         index = of_property_match_string(dev->of_node, "reg-names",
 226                                          "gpio-pin-ic");
 227         if (index < 0) {
 228                 ret = -ENODEV;
 229                 goto free_ic;
 230         }
 231
 232         ret = of_address_to_resource(dev->of_node, index, &res);
 233         if (ret < 0)
 234                 goto free_ic;
 235
 236         ic->base = devm_ioremap_resource(dev, &res);
 237         if (IS_ERR(ic->base)) {
 238                 ret = PTR_ERR(ic->base);
 239                 goto free_ic;
 240         }
 241
 242         raw_spin_lock_init(&ic->lock);
 243
 244         ic->domain = irq_domain_add_hierarchy(parent_domain, 0,
 245                                               NR_LPC18XX_GPIO_PIN_IC_IRQS,
 246                                               dev->of_node,
 247                                               &lpc18xx_gpio_pin_ic_domain_ops,
 248                                               ic);
 249         if (!ic->domain) {
 250                 pr_err("unable to add irq domain\n");
 251                 ret = -ENODEV;
 252                 goto free_iomap;
 253         }
 254
 255         gc->pin_ic = ic;
 256
 257         return 0;
 258
 259 free_iomap:
 260         devm_iounmap(dev, ic->base);
 261 free_ic:
 262         devm_kfree(dev, ic);
 263
 264         return ret;
 265 }
 266
 267 static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 268 {
 269         struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
 270         writeb(value ? 1 : 0, gc->base + offset);
 271 }
 272
 273 static int lpc18xx_gpio_get(struct gpio_chip *chip, unsigned offset)
 274 {
 275         struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
 276         return !!readb(gc->base + offset);
 277 }
 278
 279 static int lpc18xx_gpio_direction(struct gpio_chip *chip, unsigned offset,
 280                                   bool out)
 281 {
 282         struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip);
 283         unsigned long flags;
 284         u32 port, pin, dir;
 285
 286         port = offset / LPC18XX_PINS_PER_PORT;
 287         pin  = offset % LPC18XX_PINS_PER_PORT;
 288
 289         spin_lock_irqsave(&gc->lock, flags);
 290         dir = readl(gc->base + LPC18XX_REG_DIR(port));
 291         if (out)
 292                 dir |= BIT(pin);
 293         else
 294                 dir &= ~BIT(pin);
 295         writel(dir, gc->base + LPC18XX_REG_DIR(port));
 296         spin_unlock_irqrestore(&gc->lock, flags);
 297
 298         return 0;
 299 }
 300
 301 static int lpc18xx_gpio_direction_input(struct gpio_chip *chip,
 302                                         unsigned offset)
 303 {
 304         return lpc18xx_gpio_direction(chip, offset, false);
 305 }
 306
 307 static int lpc18xx_gpio_direction_output(struct gpio_chip *chip,
 308                                          unsigned offset, int value)
 309 {
 310         lpc18xx_gpio_set(chip, offset, value);
 311         return lpc18xx_gpio_direction(chip, offset, true);
 312 }
 313
 314 static const struct gpio_chip lpc18xx_chip = {
 315         .label                  = "lpc18xx/43xx-gpio",
 316         .request                = gpiochip_generic_request,
 317         .free                   = gpiochip_generic_free,
 318         .direction_input        = lpc18xx_gpio_direction_input,
 319         .direction_output       = lpc18xx_gpio_direction_output,
 320         .set                    = lpc18xx_gpio_set,
 321         .get                    = lpc18xx_gpio_get,
 322         .ngpio                  = LPC18XX_MAX_PORTS * LPC18XX_PINS_PER_PORT,
 323         .owner                  = THIS_MODULE,
 324 };
 325
 326 static int lpc18xx_gpio_probe(struct platform_device *pdev)
 327 {
 328         struct device *dev = &pdev->dev;
 329         struct lpc18xx_gpio_chip *gc;
 330         int index, ret;
 331
 332         gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
 333         if (!gc)
 334                 return -ENOMEM;
 335
 336         gc->gpio = lpc18xx_chip;
 337         platform_set_drvdata(pdev, gc);
 338
 339         index = of_property_match_string(dev->of_node, "reg-names", "gpio");
 340         if (index < 0) {
 341                 /* To support backward compatibility take the first resource */
 342                 gc->base = devm_platform_ioremap_resource(pdev, 0);
 343         } else {
 344                 struct resource res;
 345
 346                 ret = of_address_to_resource(dev->of_node, index, &res);
 347                 if (ret < 0)
 348                         return ret;
 349
 350                 gc->base = devm_ioremap_resource(dev, &res);
 351         }
 352         if (IS_ERR(gc->base))
 353                 return PTR_ERR(gc->base);
 354
 355         gc->clk = devm_clk_get(dev, NULL);
 356         if (IS_ERR(gc->clk)) {
 357                 dev_err(dev, "input clock not found\n");
 358                 return PTR_ERR(gc->clk);
 359         }
 360
 361         ret = clk_prepare_enable(gc->clk);
 362         if (ret) {
 363                 dev_err(dev, "unable to enable clock\n");
 364                 return ret;
 365         }
 366
 367         spin_lock_init(&gc->lock);
 368
 369         gc->gpio.parent = dev;
 370
 371         ret = devm_gpiochip_add_data(dev, &gc->gpio, gc);
 372         if (ret) {
 373                 dev_err(dev, "failed to add gpio chip\n");
 374                 clk_disable_unprepare(gc->clk);
 375                 return ret;
 376         }
 377
 378         /* On error GPIO pin interrupt controller just won't be registered */
 379         lpc18xx_gpio_pin_ic_probe(gc);
 380
 381         return 0;
 382 }
 383
 384 static int lpc18xx_gpio_remove(struct platform_device *pdev)
 385 {
 386         struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev);
 387
 388         if (gc->pin_ic)
 389                 irq_domain_remove(gc->pin_ic->domain);
 390
 391         clk_disable_unprepare(gc->clk);
 392
 393         return 0;
 394 }
 395
 396 static const struct of_device_id lpc18xx_gpio_match[] = {
 397         { .compatible = "nxp,lpc1850-gpio" },
 398         { }
 399 };
 400 MODULE_DEVICE_TABLE(of, lpc18xx_gpio_match);
 401
 402 static struct platform_driver lpc18xx_gpio_driver = {
 403         .probe  = lpc18xx_gpio_probe,
 404         .remove = lpc18xx_gpio_remove,
 405         .driver = {
 406                 .name           = "lpc18xx-gpio",
 407                 .of_match_table = lpc18xx_gpio_match,
 408         },
 409 };
 410 module_platform_driver(lpc18xx_gpio_driver);
 411
 412 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
 413 MODULE_AUTHOR("Vladimir Zapolskiy <vz@mleia.com>");
 414 MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx");
 415 MODULE_LICENSE("GPL v2");