1 // SPDX-License-Identifier: GPL-2.0
4 // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
6 // based on previous work and know-how from:
7 // Deepak Saxena <dsaxena@plexity.net>
9 #include <linux/gpio/driver.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/irqchip.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/bitops.h>
18 #define IXP4XX_REG_GPOUT 0x00
19 #define IXP4XX_REG_GPOE 0x04
20 #define IXP4XX_REG_GPIN 0x08
21 #define IXP4XX_REG_GPIS 0x0C
22 #define IXP4XX_REG_GPIT1 0x10
23 #define IXP4XX_REG_GPIT2 0x14
24 #define IXP4XX_REG_GPCLK 0x18
25 #define IXP4XX_REG_GPDBSEL 0x1C
28 * The hardware uses 3 bits to indicate interrupt "style".
29 * we clear and set these three bits accordingly. The lower 24
30 * bits in two registers (GPIT1 and GPIT2) are used to set up
31 * the style for 8 lines each for a total of 16 GPIO lines.
33 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
34 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
35 #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
36 #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
37 #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
38 #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
39 #define IXP4XX_GPIO_STYLE_SIZE 3
42 * struct ixp4xx_gpio - IXP4 GPIO state container
43 * @dev: containing device for this instance
44 * @fwnode: the fwnode for this GPIO chip
45 * @gc: gpiochip for this instance
46 * @base: remapped I/O-memory base
47 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
52 struct fwnode_handle *fwnode;
55 unsigned long long irq_edge;
58 static void ixp4xx_gpio_irq_ack(struct irq_data *d)
60 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
61 struct ixp4xx_gpio *g = gpiochip_get_data(gc);
63 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
66 static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
68 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
69 struct ixp4xx_gpio *g = gpiochip_get_data(gc);
71 /* ACK when unmasking if not edge-triggered */
72 if (!(g->irq_edge & BIT(d->hwirq)))
73 ixp4xx_gpio_irq_ack(d);
75 irq_chip_unmask_parent(d);
78 static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
80 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
81 struct ixp4xx_gpio *g = gpiochip_get_data(gc);
89 case IRQ_TYPE_EDGE_BOTH:
90 irq_set_handler_locked(d, handle_edge_irq);
91 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
92 g->irq_edge |= BIT(d->hwirq);
94 case IRQ_TYPE_EDGE_RISING:
95 irq_set_handler_locked(d, handle_edge_irq);
96 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
97 g->irq_edge |= BIT(d->hwirq);
99 case IRQ_TYPE_EDGE_FALLING:
100 irq_set_handler_locked(d, handle_edge_irq);
101 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
102 g->irq_edge |= BIT(d->hwirq);
104 case IRQ_TYPE_LEVEL_HIGH:
105 irq_set_handler_locked(d, handle_level_irq);
106 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
107 g->irq_edge &= ~BIT(d->hwirq);
109 case IRQ_TYPE_LEVEL_LOW:
110 irq_set_handler_locked(d, handle_level_irq);
111 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
112 g->irq_edge &= ~BIT(d->hwirq);
121 int_reg = IXP4XX_REG_GPIT2;
124 int_reg = IXP4XX_REG_GPIT1;
127 raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);
129 /* Clear the style for the appropriate pin */
130 val = __raw_readl(g->base + int_reg);
131 val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
132 __raw_writel(val, g->base + int_reg);
134 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
136 /* Set the new style */
137 val = __raw_readl(g->base + int_reg);
138 val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
139 __raw_writel(val, g->base + int_reg);
141 /* Force-configure this line as an input */
142 val = __raw_readl(g->base + IXP4XX_REG_GPOE);
143 val |= BIT(d->hwirq);
144 __raw_writel(val, g->base + IXP4XX_REG_GPOE);
146 raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
148 /* This parent only accept level high (asserted) */
149 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
152 static struct irq_chip ixp4xx_gpio_irqchip = {
154 .irq_ack = ixp4xx_gpio_irq_ack,
155 .irq_mask = irq_chip_mask_parent,
156 .irq_unmask = ixp4xx_gpio_irq_unmask,
157 .irq_set_type = ixp4xx_gpio_irq_set_type,
160 static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
162 unsigned int child_type,
163 unsigned int *parent,
164 unsigned int *parent_type)
166 /* All these interrupts are level high in the CPU */
167 *parent_type = IRQ_TYPE_LEVEL_HIGH;
169 /* GPIO lines 0..12 have dedicated IRQs */
178 if (child >= 2 && child <= 12) {
179 *parent = child + 17;
185 static int ixp4xx_gpio_probe(struct platform_device *pdev)
188 struct device *dev = &pdev->dev;
189 struct device_node *np = dev->of_node;
190 struct irq_domain *parent;
191 struct resource *res;
192 struct ixp4xx_gpio *g;
193 struct gpio_irq_chip *girq;
194 struct device_node *irq_parent;
197 g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
203 g->base = devm_ioremap_resource(dev, res);
205 return PTR_ERR(g->base);
207 irq_parent = of_irq_find_parent(np);
209 dev_err(dev, "no IRQ parent node\n");
212 parent = irq_find_host(irq_parent);
214 dev_err(dev, "no IRQ parent domain\n");
217 g->fwnode = of_node_to_fwnode(np);
220 * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
223 if (of_machine_is_compatible("dlink,dsm-g600-a") ||
224 of_machine_is_compatible("iom,nas-100d"))
225 __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
228 * This is a very special big-endian ARM issue: when the IXP4xx is
229 * run in big endian mode, all registers in the machine are switched
230 * around to the CPU-native endianness. As you see mostly in the
231 * driver we use __raw_readl()/__raw_writel() to access the registers
232 * in the appropriate order. With the GPIO library we need to specify
233 * byte order explicitly, so this flag needs to be set when compiling
236 #if defined(CONFIG_CPU_BIG_ENDIAN)
237 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
242 /* Populate and register gpio chip */
243 ret = bgpio_init(&g->gc, dev, 4,
244 g->base + IXP4XX_REG_GPIN,
245 g->base + IXP4XX_REG_GPOUT,
248 g->base + IXP4XX_REG_GPOE,
251 dev_err(dev, "unable to init generic GPIO\n");
255 g->gc.label = "IXP4XX_GPIO_CHIP";
257 * TODO: when we have migrated to device tree and all GPIOs
258 * are fetched using phandles, set this to -1 to get rid of
259 * the fixed gpiochip base.
262 g->gc.parent = &pdev->dev;
263 g->gc.owner = THIS_MODULE;
266 girq->chip = &ixp4xx_gpio_irqchip;
267 girq->fwnode = g->fwnode;
268 girq->parent_domain = parent;
269 girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
270 girq->handler = handle_bad_irq;
271 girq->default_type = IRQ_TYPE_NONE;
273 ret = devm_gpiochip_add_data(dev, &g->gc, g);
275 dev_err(dev, "failed to add SoC gpiochip\n");
279 platform_set_drvdata(pdev, g);
280 dev_info(dev, "IXP4 GPIO registered\n");
285 static const struct of_device_id ixp4xx_gpio_of_match[] = {
287 .compatible = "intel,ixp4xx-gpio",
293 static struct platform_driver ixp4xx_gpio_driver = {
295 .name = "ixp4xx-gpio",
296 .of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
298 .probe = ixp4xx_gpio_probe,
300 builtin_platform_driver(ixp4xx_gpio_driver);