2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include <asm/errno.h>
18 #include <asm/arch-sc8825/ldo.h>
20 #include <asm/arch/sc8810_reg_global.h>
22 #include <asm/arch/regs_global.h>
23 #include <asm/arch/regs_cpc.h>
24 #include <linux/gpio.h>
25 #include <asm/arch/pinmap.h>
26 #include <asm/arch/gpio.h>
27 #include <ubi_uboot.h>
29 /* 16 GPIO share a group of registers */
30 #define GPIO_GROUP_NR (16)
31 #define GPIO_GROUP_MASK (0xFFFF)
33 #define GPIO_GROUP_OFFSET (0x80)
34 #define ANA_GPIO_GROUP_OFFSET (0x40)
36 /* registers definitions for GPIO controller */
37 #define REG_GPIO_DATA (0x0000)
38 #define REG_GPIO_DMSK (0x0004)
39 #define REG_GPIO_DIR (0x0008) /* only for gpio */
40 #define REG_GPIO_IS (0x000c) /* only for gpio */
41 #define REG_GPIO_IBE (0x0010) /* only for gpio */
42 #define REG_GPIO_IEV (0x0014)
43 #define REG_GPIO_IE (0x0018)
44 #define REG_GPIO_RIS (0x001c)
45 #define REG_GPIO_MIS (0x0020)
46 #define REG_GPIO_IC (0x0024)
47 #define REG_GPIO_INEN (0x0028) /* only for gpio */
49 /* 8 EIC share a group of registers */
50 #define EIC_GROUP_NR (8)
51 #define EIC_GROUP_MASK (0xFF)
53 /* registers definitions for EIC controller */
54 #define REG_EIC_DATA REG_GPIO_DATA
55 #define REG_EIC_DMSK REG_GPIO_DMSK
56 #define REG_EIC_IEV REG_GPIO_IEV
57 #define REG_EIC_IE REG_GPIO_IE
58 #define REG_EIC_RIS REG_GPIO_RIS
59 #define REG_EIC_MIS REG_GPIO_MIS
60 #define REG_EIC_IC REG_GPIO_IC
61 #define REG_EIC_TRIG (0x0028) /* only for eic */
62 #define REG_EIC_0CTRL (0x0040)
63 #define REG_EIC_1CTRL (0x0044)
64 #define REG_EIC_2CTRL (0x0048)
65 #define REG_EIC_3CTRL (0x004c)
66 #define REG_EIC_4CTRL (0x0050)
67 #define REG_EIC_5CTRL (0x0054)
68 #define REG_EIC_6CTRL (0x0058)
69 #define REG_EIC_7CTRL (0x005c)
70 #define REG_EIC_DUMMYCTRL (0x0000)
72 /* bits definitions for register REG_EIC_DUMMYCTRL */
73 #define BIT_FORCE_CLK_DBNC BIT(15)
74 #define BIT_EIC_DBNC_EN BIT(14)
75 #define SHIFT_EIC_DBNC_CNT (0)
76 #define MASK_EIC_DBNC_CNT (0xFFF)
77 #define BITS_EIC_DBNC_CNT(_x_) ((_x) & 0xFFF)
79 struct sci_gpio_chip {
80 struct gpio_chip chip;
83 uint32_t group_offset;
85 uint32_t(*read_reg) (uint32_t addr);
86 void (*write_reg) (uint32_t value, uint32_t addr);
87 void (*set_bits) (uint32_t bits, uint32_t addr);
88 void (*clr_bits) (uint32_t bits, uint32_t addr);
91 #define to_sci_gpio(c) container_of(c, struct sci_gpio_chip, chip)
94 static uint32_t d_read_reg(uint32_t addr)
96 return __raw_readl(addr);
99 static void d_write_reg(uint32_t value, uint32_t addr)
101 __raw_writel(value, addr);
104 static void d_set_bits(uint32_t bits, uint32_t addr)
106 __raw_writel(__raw_readl(addr) | bits, addr);
109 static void d_clr_bits(uint32_t bits, uint32_t addr)
111 __raw_writel(__raw_readl(addr) & ~bits, addr);
115 static uint32_t a_read_reg(uint32_t addr)
117 return sci_adi_read(addr);
120 static void a_write_reg(uint32_t value, uint32_t addr)
122 sci_adi_raw_write(addr, value);
125 static void a_set_bits(uint32_t bits, uint32_t addr)
127 sci_adi_set(addr, bits);
130 static void a_clr_bits(uint32_t bits, uint32_t addr)
132 sci_adi_clr(addr, bits);
135 static int sci_gpio_read(struct gpio_chip *chip, uint32_t offset, uint32_t reg)
137 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
138 int group = offset / GPIO_GROUP_NR;
139 int bitof = offset & (GPIO_GROUP_NR - 1);
140 int addr = sci_gpio->base_addr + sci_gpio->group_offset * group + reg;
141 int value = sci_gpio->read_reg(addr) & GPIO_GROUP_MASK;
143 return (value >> bitof) & 0x1;
146 static void sci_gpio_write(struct gpio_chip *chip, uint32_t offset,
147 uint32_t reg, int value)
149 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
150 int group = offset / GPIO_GROUP_NR;
151 int bitof = offset & (GPIO_GROUP_NR - 1);
152 int addr = sci_gpio->base_addr + sci_gpio->group_offset * group + reg;
155 sci_gpio->set_bits(1 << bitof, addr);
157 sci_gpio->clr_bits(1 << bitof, addr);
161 /* GPIO/EIC libgpio interfaces */
162 static int sci_gpio_request(struct gpio_chip *chip, unsigned offset)
164 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
165 sci_gpio_write(chip, offset, REG_GPIO_DMSK, 1);
169 static void sci_gpio_free(struct gpio_chip *chip, unsigned offset)
171 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
172 sci_gpio_write(chip, offset, REG_GPIO_DMSK, 0);
175 static int sci_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
177 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
178 sci_gpio_write(chip, offset, REG_GPIO_DIR, 0);
179 sci_gpio_write(chip, offset, REG_GPIO_INEN, 1);
183 static int sci_eic_direction_input(struct gpio_chip *chip, unsigned offset)
186 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
190 static int sci_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
193 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, value);
194 sci_gpio_write(chip, offset, REG_GPIO_DIR, 1);
195 sci_gpio_write(chip, offset, REG_GPIO_INEN, 0);
196 sci_gpio_write(chip, offset, REG_GPIO_DATA, value);
200 static int sci_gpio_get(struct gpio_chip *chip, unsigned offset)
202 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
203 return sci_gpio_read(chip, offset, REG_GPIO_DATA);
206 static void sci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
208 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, value);
209 sci_gpio_write(chip, offset, REG_GPIO_DATA, value);
212 static int sci_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
216 pr_err("%s %d+%d\n", __FUNCTION__, chip->base, offset);
220 static int sci_eic_set_debounce(struct gpio_chip *chip, unsigned offset,
224 pr_info("%s %d+%d\n", __FUNCTION__, chip->base, offset);
228 static int sci_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
233 static int sci_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
238 static struct sci_gpio_chip d_sci_gpio = {
239 .chip.label = "sprd-d-gpio",
240 .chip.request = sci_gpio_request,
241 .chip.free = sci_gpio_free,
242 .chip.direction_input = sci_gpio_direction_input,
243 .chip.get = sci_gpio_get,
244 .chip.direction_output = sci_gpio_direction_output,
245 .chip.set = sci_gpio_set,
246 .chip.set_debounce = sci_gpio_set_debounce,
247 .chip.to_irq = sci_gpio_to_irq,
249 .group_offset = GPIO_GROUP_OFFSET,
250 .read_reg = d_read_reg,
251 .write_reg = d_write_reg,
252 .set_bits = d_set_bits,
253 .clr_bits = d_clr_bits,
256 static struct sci_gpio_chip a_sci_gpio = {
257 .chip.label = "sprd-a-gpio",
258 .chip.request = sci_gpio_request,
259 .chip.free = sci_gpio_free,
260 .chip.direction_input = sci_gpio_direction_input,
261 .chip.get = sci_gpio_get,
262 .chip.direction_output = sci_gpio_direction_output,
263 .chip.set = sci_gpio_set,
264 .chip.set_debounce = sci_gpio_set_debounce,
265 .chip.to_irq = sci_gpio_to_irq,
267 .group_offset = ANA_GPIO_GROUP_OFFSET,
268 .read_reg = a_read_reg,
269 .write_reg = a_write_reg,
270 .set_bits = a_set_bits,
271 .clr_bits = a_clr_bits,
275 * EIC has the same register layout with GPIO when it's used as GPI.
276 * So most implementation of GPIO can be shared by EIC.
278 static struct sci_gpio_chip d_sci_eic = {
279 .chip.label = "sprd-d-eic",
280 .chip.request = sci_gpio_request,
281 .chip.free = sci_gpio_free,
282 .chip.direction_input = sci_eic_direction_input,
283 .chip.get = sci_gpio_get,
284 .chip.direction_output = NULL,
286 .chip.set_debounce = sci_eic_set_debounce,
287 .chip.to_irq = sci_gpio_to_irq,
289 .group_offset = GPIO_GROUP_OFFSET,
290 .read_reg = d_read_reg,
291 .write_reg = d_write_reg,
292 .set_bits = d_set_bits,
293 .clr_bits = d_clr_bits,
296 static struct sci_gpio_chip a_sci_eic = {
297 .chip.label = "sprd-a-eic",
298 .chip.request = sci_gpio_request,
299 .chip.free = sci_gpio_free,
300 .chip.direction_input = sci_eic_direction_input,
301 .chip.get = sci_gpio_get,
302 .chip.direction_output = NULL,
304 .chip.set_debounce = sci_eic_set_debounce,
305 .chip.to_irq = sci_gpio_to_irq,
307 .group_offset = ANA_GPIO_GROUP_OFFSET,
308 .read_reg = a_read_reg,
309 .write_reg = a_write_reg,
310 .set_bits = a_set_bits,
311 .clr_bits = a_clr_bits,
315 void sprd_gpio_init(struct eic_gpio_resource *r)
322 sci_glb_set(GR_GEN0, GEN0_EIC_EN);
323 sci_glb_set(GR_GEN0, GEN0_GPIO_EN);
324 sci_glb_set(GR_GEN0, GEN0_GPIO_RTC_EN);
325 sci_adi_set(ANA_APB_CLK_EN,
326 EIC_EB | GPIO_EB | RTC_EIC_EB);
329 d_sci_gpio.base_addr = r[ENUM_ID_D_GPIO].base_addr;
330 d_sci_gpio.chip.base = r[ENUM_ID_D_GPIO].chip_base;
331 d_sci_gpio.chip.ngpio = r[ENUM_ID_D_GPIO].chip_ngpio;
333 d_sci_eic.base_addr = r[ENUM_ID_D_EIC].base_addr;
334 d_sci_eic.chip.base = r[ENUM_ID_D_EIC].chip_base;
335 d_sci_eic.chip.ngpio = r[ENUM_ID_D_EIC].chip_ngpio;
337 a_sci_gpio.base_addr = r[ENUM_ID_A_GPIO].base_addr;
338 a_sci_gpio.chip.base = r[ENUM_ID_A_GPIO].chip_base;
339 a_sci_gpio.chip.ngpio = r[ENUM_ID_A_GPIO].chip_ngpio;
341 a_sci_eic.base_addr = r[ENUM_ID_A_EIC].base_addr;
342 a_sci_eic.chip.base = r[ENUM_ID_A_EIC].chip_base;
343 a_sci_eic.chip.ngpio = r[ENUM_ID_A_EIC].chip_ngpio;
345 gpiochip_add(&d_sci_eic.chip);
346 gpiochip_add(&d_sci_gpio.chip);
347 gpiochip_add(&a_sci_eic.chip);
348 gpiochip_add(&a_sci_gpio.chip);
354 static int eic_gpio_remove(void)
358 ret += gpiochip_remove(&d_sci_eic.chip);
359 ret += gpiochip_remove(&d_sci_gpio.chip);
360 ret += gpiochip_remove(&a_sci_eic.chip);
361 ret += gpiochip_remove(&a_sci_gpio.chip);