2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/bug.h>
23 #include <linux/of_device.h>
24 #include <linux/irqdomain.h>
26 #include <soc/sprd/sci.h>
27 #include <soc/sprd/sci_glb_regs.h>
28 #include <soc/sprd/gpio.h>
29 #include <soc/sprd/adi.h>
31 /* 16 GPIO share a group of registers */
32 #define GPIO_GROUP_NR (16)
33 #define GPIO_GROUP_MASK (0xFFFF)
35 #define GPIO_GROUP_OFFSET (0x80)
36 #define ANA_GPIO_GROUP_OFFSET (0x40)
38 /* registers definitions for GPIO controller */
39 #define REG_GPIO_DATA (0x0000)
40 #define REG_GPIO_DMSK (0x0004)
41 #define REG_GPIO_DIR (0x0008) /* only for gpio */
42 #define REG_GPIO_IS (0x000c) /* only for gpio */
43 #define REG_GPIO_IBE (0x0010) /* only for gpio */
44 #define REG_GPIO_IEV (0x0014)
45 #define REG_GPIO_IE (0x0018)
46 #define REG_GPIO_RIS (0x001c)
47 #define REG_GPIO_MIS (0x0020)
48 #define REG_GPIO_IC (0x0024)
49 #define REG_GPIO_INEN (0x0028) /* only for gpio */
51 /* 8 EIC share a group of registers */
52 #define EIC_GROUP_NR (8)
53 #define EIC_GROUP_MASK (0xFF)
55 /* registers definitions for EIC controller */
56 #define REG_EIC_DATA REG_GPIO_DATA
57 #define REG_EIC_DMSK REG_GPIO_DMSK
58 #define REG_EIC_IEV REG_GPIO_IEV
59 #define REG_EIC_IE REG_GPIO_IE
60 #define REG_EIC_RIS REG_GPIO_RIS
61 #define REG_EIC_MIS REG_GPIO_MIS
62 #define REG_EIC_IC REG_GPIO_IC
63 #define REG_EIC_TRIG (0x0028) /* only for eic */
64 #define REG_EIC_0CTRL (0x0040)
65 #define REG_EIC_1CTRL (0x0044)
66 #define REG_EIC_2CTRL (0x0048)
67 #define REG_EIC_3CTRL (0x004c)
68 #define REG_EIC_4CTRL (0x0050)
69 #define REG_EIC_5CTRL (0x0054)
70 #define REG_EIC_6CTRL (0x0058)
71 #define REG_EIC_7CTRL (0x005c)
72 #define REG_EIC_DUMMYCTRL (0x0000)
74 /* bits definitions for register REG_EIC_DUMMYCTRL */
75 #define BIT_FORCE_CLK_DBNC BIT(15)
76 #define BIT_EIC_DBNC_EN BIT(14)
77 #define SHIFT_EIC_DBNC_CNT (0)
78 #define MASK_EIC_DBNC_CNT (0xFFF)
79 #define BITS_EIC_DBNC_CNT(_x_) ((_x) & 0xFFF)
81 struct sci_gpio_chip {
82 struct gpio_chip chip;
84 unsigned long base_addr;
85 uint32_t group_offset;
86 struct irq_domain *irq_domain;
89 uint32_t(*read_reg) (unsigned long addr);
90 void (*write_reg) (uint32_t value, unsigned long addr);
91 void (*set_bits) (uint32_t bits, unsigned long addr);
92 void (*clr_bits) (uint32_t bits, unsigned long addr);
95 #define to_sci_gpio(c) container_of(c, struct sci_gpio_chip, chip)
98 static uint32_t d_read_reg(unsigned long addr)
100 return __raw_readl((const volatile void *)addr);
103 static void d_write_reg(uint32_t value, unsigned long addr)
105 __raw_writel(value, (volatile void *)addr);
108 static void d_set_bits(uint32_t bits, unsigned long addr)
110 __raw_writel(__raw_readl((const volatile void *)addr) | bits, (volatile void *)addr);
113 static void d_clr_bits(uint32_t bits, unsigned long addr)
115 __raw_writel(__raw_readl((const volatile void *)addr) & ~bits, (volatile void *)addr);
119 static uint32_t a_read_reg(unsigned long addr)
121 return sci_adi_read(addr);
124 static void a_write_reg(uint32_t value, unsigned long addr)
126 sci_adi_raw_write(addr, value);
129 static void a_set_bits(uint32_t bits, unsigned long addr)
131 sci_adi_set(addr, bits);
134 static void a_clr_bits(uint32_t bits, unsigned long addr)
136 sci_adi_clr(addr, bits);
139 static int sci_gpio_read(struct gpio_chip *chip, uint32_t offset, uint32_t reg)
141 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
142 int group = offset / GPIO_GROUP_NR;
143 int bitof = offset & (GPIO_GROUP_NR - 1);
144 unsigned long addr = sci_gpio->base_addr + sci_gpio->group_offset * group + reg;
145 int value = sci_gpio->read_reg(addr) & GPIO_GROUP_MASK;
147 return (value >> bitof) & 0x1;
150 static void sci_gpio_write(struct gpio_chip *chip, uint32_t offset,
151 uint32_t reg, int value)
153 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
154 int group = offset / GPIO_GROUP_NR;
155 int bitof = offset & (GPIO_GROUP_NR - 1);
156 unsigned long addr = sci_gpio->base_addr + sci_gpio->group_offset * group + reg;
159 sci_gpio->set_bits(1 << bitof, addr);
161 sci_gpio->clr_bits(1 << bitof, addr);
165 /* GPIO/EIC libgpio interfaces */
166 static int sci_gpio_request(struct gpio_chip *chip, unsigned offset)
168 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
169 sci_gpio_write(chip, offset, REG_GPIO_DMSK, 1);
173 static void sci_gpio_free(struct gpio_chip *chip, unsigned offset)
175 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
176 sci_gpio_write(chip, offset, REG_GPIO_DMSK, 0);
179 static int sci_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
181 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
182 sci_gpio_write(chip, offset, REG_GPIO_DIR, 0);
183 sci_gpio_write(chip, offset, REG_GPIO_INEN, 1);
187 static int sci_eic_direction_input(struct gpio_chip *chip, unsigned offset)
190 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
194 static int sci_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
197 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, value);
198 sci_gpio_write(chip, offset, REG_GPIO_DIR, 1);
199 sci_gpio_write(chip, offset, REG_GPIO_INEN, 0);
200 sci_gpio_write(chip, offset, REG_GPIO_DATA, value);
204 static int sci_gpio_get(struct gpio_chip *chip, unsigned offset)
206 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
207 return sci_gpio_read(chip, offset, REG_GPIO_DATA);
210 static void sci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
212 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, value);
213 sci_gpio_write(chip, offset, REG_GPIO_DATA, value);
216 static int sci_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
220 pr_err("%s %d+%d\n", __FUNCTION__, chip->base, offset);
224 static int sci_eic_set_debounce(struct gpio_chip *chip, unsigned offset,
228 pr_info("%s %d+%d\n", __FUNCTION__, chip->base, offset);
233 static int sci_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
235 struct irq_domain *irq_domain;
236 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
238 irq_domain = sci_gpio->irq_domain;
239 return irq_find_mapping(irq_domain, offset);
242 static int sci_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
245 struct irq_domain *irq_domain;
246 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
248 irq_domain = sci_gpio->irq_domain;
249 base_irq = irq_find_mapping(irq_domain, 0);
250 return irq - base_irq;
253 static int sci_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
255 return chip->base + offset + GPIO_IRQ_START;
258 static int sci_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
260 return irq - GPIO_IRQ_START - chip->base;
265 static struct sci_gpio_chip d_sci_gpio = {
266 .chip.label = "sprd-d-gpio",
267 .chip.request = sci_gpio_request,
268 .chip.free = sci_gpio_free,
269 .chip.direction_input = sci_gpio_direction_input,
270 .chip.get = sci_gpio_get,
271 .chip.direction_output = sci_gpio_direction_output,
272 .chip.set = sci_gpio_set,
273 .chip.set_debounce = sci_gpio_set_debounce,
274 .chip.to_irq = sci_gpio_to_irq,
276 .group_offset = GPIO_GROUP_OFFSET,
277 .read_reg = d_read_reg,
278 .write_reg = d_write_reg,
279 .set_bits = d_set_bits,
280 .clr_bits = d_clr_bits,
284 static struct sci_gpio_chip a_sci_gpio = {
285 .chip.label = "sprd-a-gpio",
286 .chip.request = sci_gpio_request,
287 .chip.free = sci_gpio_free,
288 .chip.direction_input = sci_gpio_direction_input,
289 .chip.get = sci_gpio_get,
290 .chip.direction_output = sci_gpio_direction_output,
291 .chip.set = sci_gpio_set,
292 .chip.set_debounce = sci_gpio_set_debounce,
293 .chip.to_irq = sci_gpio_to_irq,
295 .group_offset = ANA_GPIO_GROUP_OFFSET,
296 .read_reg = a_read_reg,
297 .write_reg = a_write_reg,
298 .set_bits = a_set_bits,
299 .clr_bits = a_clr_bits,
304 * EIC has the same register layout with GPIO when it's used as GPI.
305 * So most implementation of GPIO can be shared by EIC.
307 static struct sci_gpio_chip d_sci_eic = {
308 .chip.label = "sprd-d-eic",
309 .chip.request = sci_gpio_request,
310 .chip.free = sci_gpio_free,
311 .chip.direction_input = sci_eic_direction_input,
312 .chip.get = sci_gpio_get,
313 .chip.direction_output = NULL,
315 .chip.set_debounce = sci_eic_set_debounce,
316 .chip.to_irq = sci_gpio_to_irq,
318 .group_offset = GPIO_GROUP_OFFSET,
319 .read_reg = d_read_reg,
320 .write_reg = d_write_reg,
321 .set_bits = d_set_bits,
322 .clr_bits = d_clr_bits,
326 static struct sci_gpio_chip a_sci_eic = {
327 .chip.label = "sprd-a-eic",
328 .chip.request = sci_gpio_request,
329 .chip.free = sci_gpio_free,
330 .chip.direction_input = sci_eic_direction_input,
331 .chip.get = sci_gpio_get,
332 .chip.direction_output = NULL,
334 .chip.set_debounce = sci_eic_set_debounce,
335 .chip.to_irq = sci_gpio_to_irq,
337 .group_offset = ANA_GPIO_GROUP_OFFSET,
338 .read_reg = a_read_reg,
339 .write_reg = a_write_reg,
340 .set_bits = a_set_bits,
341 .clr_bits = a_clr_bits,
345 /* GPIO/EIC irq interfaces */
346 static void sci_gpio_irq_ack(struct irq_data *data)
348 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
349 int offset = sci_irq_to_gpio(chip, data->irq);
350 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
351 sci_gpio_write(chip, offset, REG_GPIO_IC, 1);
354 static void sci_gpio_irq_mask(struct irq_data *data)
356 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
357 int offset = sci_irq_to_gpio(chip, data->irq);
358 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
359 sci_gpio_write(chip, offset, REG_GPIO_IE, 0);
362 static void sci_gpio_irq_unmask(struct irq_data *data)
364 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
365 int offset = sci_irq_to_gpio(chip, data->irq);
366 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
367 sci_gpio_write(chip, offset, REG_GPIO_IE, 1);
370 static void sci_eic_irq_unmask(struct irq_data *data)
372 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
373 int offset = sci_irq_to_gpio(chip, data->irq);
374 pr_debug("%s %d+%d\n", __FUNCTION__, chip->base, offset);
375 sci_gpio_write(chip, offset, REG_EIC_IE, 1);
377 /* TODO: the interval of two EIC trigger needs be longer than 2ms */
378 sci_gpio_write(chip, offset, REG_EIC_TRIG, 1);
381 static int sci_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
383 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
384 int offset = sci_irq_to_gpio(chip, data->irq);
385 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, flow_type);
387 case IRQ_TYPE_EDGE_RISING:
388 sci_gpio_write(chip, offset, REG_GPIO_IS, 0);
389 sci_gpio_write(chip, offset, REG_GPIO_IBE, 0);
390 sci_gpio_write(chip, offset, REG_GPIO_IEV, 1);
391 __irq_set_handler_locked(data->irq, handle_edge_irq);
393 case IRQ_TYPE_EDGE_FALLING:
394 sci_gpio_write(chip, offset, REG_GPIO_IS, 0);
395 sci_gpio_write(chip, offset, REG_GPIO_IBE, 0);
396 sci_gpio_write(chip, offset, REG_GPIO_IEV, 0);
397 __irq_set_handler_locked(data->irq, handle_edge_irq);
399 case IRQ_TYPE_EDGE_BOTH:
400 sci_gpio_write(chip, offset, REG_GPIO_IS, 0);
401 sci_gpio_write(chip, offset, REG_GPIO_IBE, 1);
402 __irq_set_handler_locked(data->irq, handle_edge_irq);
404 case IRQ_TYPE_LEVEL_HIGH:
405 sci_gpio_write(chip, offset, REG_GPIO_IS, 1);
406 sci_gpio_write(chip, offset, REG_GPIO_IBE, 0);
407 sci_gpio_write(chip, offset, REG_GPIO_IEV, 1);
408 __irq_set_handler_locked(data->irq, handle_level_irq);
410 case IRQ_TYPE_LEVEL_LOW:
411 sci_gpio_write(chip, offset, REG_GPIO_IS, 1);
412 sci_gpio_write(chip, offset, REG_GPIO_IBE, 0);
413 sci_gpio_write(chip, offset, REG_GPIO_IEV, 0);
414 __irq_set_handler_locked(data->irq, handle_level_irq);
423 static int sci_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
425 struct gpio_chip *chip = (struct gpio_chip *)data->chip_data;
426 int offset = sci_irq_to_gpio(chip, data->irq);
427 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, offset, flow_type);
429 case IRQ_TYPE_LEVEL_HIGH:
430 sci_gpio_write(chip, offset, REG_EIC_IEV, 1);
431 __irq_set_handler_locked(data->irq, handle_level_irq);
433 case IRQ_TYPE_LEVEL_LOW:
434 sci_gpio_write(chip, offset, REG_EIC_IEV, 0);
435 __irq_set_handler_locked(data->irq, handle_level_irq);
444 static int sci_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
446 return on ? 0 : -EPERM;
449 static struct irq_chip d_gpio_irq_chip = {
450 .name = "irq-d-gpio",
451 .irq_disable = sci_gpio_irq_mask,
452 .irq_ack = sci_gpio_irq_ack,
453 .irq_mask = sci_gpio_irq_mask,
454 .irq_unmask = sci_gpio_irq_unmask,
455 .irq_set_type = sci_gpio_irq_set_type,
456 .irq_set_wake = sci_gpio_irq_set_wake,
459 static struct irq_chip a_gpio_irq_chip = {
460 .name = "irq-a-gpio",
461 .irq_disable = sci_gpio_irq_mask,
462 .irq_ack = sci_gpio_irq_ack,
463 .irq_mask = sci_gpio_irq_mask,
464 .irq_unmask = sci_gpio_irq_unmask,
465 .irq_set_type = sci_gpio_irq_set_type,
466 .irq_set_wake = sci_gpio_irq_set_wake,
470 * EIC has the same register layout with GPIO when it's used as GPI.
471 * So most implementation of GPIO can be shared by EIC.
473 static struct irq_chip d_eic_irq_chip = {
475 .irq_disable = sci_gpio_irq_mask,
476 .irq_ack = sci_gpio_irq_ack,
477 .irq_mask = sci_gpio_irq_mask,
478 .irq_unmask = sci_eic_irq_unmask,
479 .irq_set_type = sci_eic_irq_set_type,
482 static struct irq_chip a_eic_irq_chip = {
484 .irq_disable = sci_gpio_irq_mask,
485 .irq_ack = sci_gpio_irq_ack,
486 .irq_mask = sci_gpio_irq_mask,
487 .irq_unmask = sci_eic_irq_unmask,
488 .irq_set_type = sci_eic_irq_set_type,
491 static void gpio_eic_handler(int irq, struct gpio_chip *chip)
493 struct sci_gpio_chip *sci_gpio = to_sci_gpio(chip);
494 int group, n, value, count = 0;
497 pr_debug("%s %d+%d %d\n", __FUNCTION__, chip->base, chip->ngpio, irq);
498 for (group = 0; group * GPIO_GROUP_NR < chip->ngpio; group++) {
500 sci_gpio->base_addr + sci_gpio->group_offset * group +
502 value = sci_gpio->read_reg(addr) & GPIO_GROUP_MASK;
507 n = chip->to_irq(chip, group * GPIO_GROUP_NR + n);
508 pr_debug("%s generic_handle_n %d\n", __FUNCTION__, n);
510 generic_handle_irq(n);
516 static irqreturn_t gpio_muxed_handler(int irq, void *dev_id)
518 struct gpio_chip *chip = dev_id;
519 gpio_eic_handler(irq, chip);
523 /* gpio/eic cascaded irq handler */
524 static void gpio_muxed_flow_handler(unsigned int irq, struct irq_desc *desc)
526 struct gpio_chip *chip = irq_get_handler_data(irq);
527 gpio_eic_handler(irq, chip);
530 static struct irqaction __d_gpio_irq = {
532 .flags = IRQF_DISABLED | IRQF_NO_SUSPEND,
533 .handler = gpio_muxed_handler,
534 .dev_id = &d_sci_gpio.chip,
537 static struct irqaction __d_eic_irq = {
539 .flags = IRQF_DISABLED | IRQF_NO_SUSPEND,
540 .handler = gpio_muxed_handler,
541 .dev_id = &d_sci_eic.chip,
544 #if (NR_GPIO_IRQS < ARCH_NR_GPIOS)
545 #error "NR_GPIO_IRQS is not match with the sum of builtin/SoC GPIOs and EICs"
549 static void gpio_irq_init(int irq, struct gpio_chip *gpiochip,
550 struct irq_chip *irqchip)
553 struct sci_gpio_chip *sci_gpio = to_sci_gpio(gpiochip);
554 struct irq_domain *irq_domain = sci_gpio->irq_domain;
556 /* setup the cascade irq handlers */
557 if (sci_gpio->is_adi_gpio) {
558 /*TODO*/ irq_set_chained_handler(irq, gpio_muxed_flow_handler);
559 irq_set_handler_data(irq, gpiochip);
562 for (i = 0; i < gpiochip->ngpio; i++) {
563 n = irq_create_mapping(irq_domain, i);
564 irq_set_chip_and_handler(n, irqchip, handle_level_irq);
565 irq_set_chip_data(n, gpiochip);
566 set_irq_flags(n, IRQF_VALID);
570 static void gpio_irq_init(int irq, struct gpio_chip *gpiochip,
571 struct irq_chip *irqchip)
573 int n = gpiochip->to_irq(gpiochip, 0);
574 int irqend = n + gpiochip->ngpio;
576 /* setup the cascade irq handlers */
577 if (irq >= NR_SCI_PHY_IRQS) {
578 irq_set_chained_handler(irq, gpio_muxed_flow_handler);
579 irq_set_handler_data(irq, gpiochip);
582 for (; n < irqend; n++) {
583 irq_set_chip_and_handler(n, irqchip, handle_level_irq);
584 irq_set_chip_data(n, gpiochip);
585 set_irq_flags(n, IRQF_VALID);
592 struct sprd_gpio_match_data {
593 struct sci_gpio_chip *sci_gpio_chip;
594 struct irq_chip *irq_chip;
595 struct irqaction *irqaction;
597 static struct sprd_gpio_match_data d_eic_match = {
598 .sci_gpio_chip = &d_sci_eic,
599 .irq_chip = &d_eic_irq_chip,
600 .irqaction = &__d_eic_irq,
603 static struct sprd_gpio_match_data d_gpio_match = {
604 .sci_gpio_chip = &d_sci_gpio,
605 .irq_chip = &d_gpio_irq_chip,
606 .irqaction = &__d_gpio_irq,
609 static struct sprd_gpio_match_data a_eic_match = {
610 .sci_gpio_chip = &a_sci_eic,
611 .irq_chip = &a_eic_irq_chip,
615 static struct sprd_gpio_match_data a_gpio_match = {
616 .sci_gpio_chip = &a_sci_gpio,
617 .irq_chip = &a_gpio_irq_chip,
621 static struct of_device_id eic_gpio_match_table[] = {
622 {.compatible = "sprd,d-eic-gpio",.data = &d_eic_match},
623 {.compatible = "sprd,d-gpio-gpio",.data = &d_gpio_match},
624 {.compatible = "sprd,a-eic-gpio",.data = &a_eic_match},
625 {.compatible = "sprd,a-gpio-gpio",.data = &a_gpio_match},
629 static int eic_gpio_probe(struct platform_device *pdev)
631 struct eic_gpio_resource *r = pdev->dev.platform_data;
632 const struct of_device_id *match;
633 struct sprd_gpio_match_data *match_data;
634 struct device_node *np = pdev->dev.of_node;
635 struct sci_gpio_chip *sgc;
637 struct irqaction *ia;
638 static bool init_done = false;
639 struct resource *res;
640 struct irq_domain *irq_domain;
648 #if defined(CONFIG_ARCH_SC8825)
649 sci_glb_set(REG_GLB_GEN0, BIT_EIC_EB);
650 sci_glb_set(REG_GLB_GEN0, BIT_GPIO_EB);
651 sci_glb_set(REG_GLB_GEN0, BIT_RTC_EIC_EB);
652 sci_adi_set(ANA_REG_GLB_ANA_APB_CLK_EN,
653 BIT_ANA_EIC_EB | BIT_ANA_GPIO_EB | BIT_ANA_RTC_EIC_EB);
654 #elif (defined(CONFIG_ARCH_SCX15)||defined(CONFIG_ADIE_SC2723S)||defined(CONFIG_ADIE_SC2723))
655 sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB | BIT_EIC_EB);
656 sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_EIC_RTC_EB);
657 sci_adi_set(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_EIC_EN);
658 sci_adi_set(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_EIC_EN);
659 #elif defined(CONFIG_ARCH_SCX35)
660 sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB | BIT_EIC_EB);
661 sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_EIC_RTC_EB);
662 sci_adi_set(ANA_REG_GLB_ARM_MODULE_EN,
663 BIT_ANA_EIC_EN | BIT_ANA_GPIO_EN);
664 sci_adi_set(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_EIC_EN);
669 match = of_match_device(eic_gpio_match_table, &pdev->dev);
670 match_data = (struct sprd_gpio_match_data *)(match->data);
671 sgc = match_data->sci_gpio_chip;
672 ic = match_data->irq_chip;
673 ia = match_data->irqaction;
675 if(match_data==&a_eic_match)
676 sgc->base_addr = ANA_EIC_BASE;
679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
681 dev_err(&pdev->dev, "No reg of property specified\n");
685 sgc->base_addr = (unsigned long)ioremap_nocache(res->start,
686 res->end - res->start);
688 panic("ioremap failed!\n");
691 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
697 if (of_property_read_u32(np, "ngpios", (u32 *)(&sgc->chip.ngpio))) {
698 dev_err(&pdev->dev, "No ngpios of property specified\n");
699 release_mem_region(res->start, resource_size(res));
702 if (of_property_read_u32(np, "gpiobase", (u32 *)(&sgc->chip.base))) {
703 dev_err(&pdev->dev, "No gpiobase of property specified\n");
707 dev_info(&pdev->dev, "base_addr %lx, gpio base %d, ngpio %d, irq %d",
708 sgc->base_addr, sgc->chip.base, sgc->chip.ngpio, irq);
711 sgc->chip.of_node = np;
713 gpiochip_add(&sgc->chip);
715 irq_domain = irq_domain_add_linear(np, sgc->chip.ngpio,
716 &irq_domain_simple_ops, NULL);
718 dev_err(&pdev->dev, "failed to add irq domain\n");
719 gpiochip_remove(&sgc->chip);
720 release_mem_region(res->start, resource_size(res));
723 sgc->irq_domain = irq_domain;
726 gpio_irq_init(irq, &sgc->chip, ic);
734 static int eic_gpio_remove(struct platform_device *pdev)
737 const struct of_device_id *match;
738 struct sprd_gpio_match_data *match_data;
739 struct sci_gpio_chip *sgc;
741 match = of_match_device(eic_gpio_match_table, &pdev->dev);
742 match_data = (struct sprd_gpio_match_data *)(match->data);
743 sgc = match_data->sci_gpio_chip;
744 ret = gpiochip_remove(&sgc->chip);
749 static int eic_gpio_probe(struct platform_device *pdev)
751 struct eic_gpio_resource *r = pdev->dev.platform_data;
752 struct irq_domain *irq_domain;
757 #if defined(CONFIG_ARCH_SC8825)
758 sci_glb_set(REG_GLB_GEN0, BIT_EIC_EB);
759 sci_glb_set(REG_GLB_GEN0, BIT_GPIO_EB);
760 sci_glb_set(REG_GLB_GEN0, BIT_RTC_EIC_EB);
761 sci_adi_set(ANA_REG_GLB_ANA_APB_CLK_EN,
762 BIT_ANA_EIC_EB | BIT_ANA_GPIO_EB | BIT_ANA_RTC_EIC_EB);
763 #elif (defined(CONFIG_ARCH_SCX15)||defined(CONFIG_ADIE_SC2723S)||defined(CONFIG_ADIE_SC2723))
764 sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB | BIT_EIC_EB);
765 sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_EIC_RTC_EB);
766 sci_adi_set(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_EIC_EN);
767 sci_adi_set(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_EIC_EN);
768 #elif defined(CONFIG_ARCH_SCX35)
769 sci_glb_set(REG_AON_APB_APB_EB0, BIT_GPIO_EB | BIT_EIC_EB);
770 sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_EIC_RTC_EB);
771 sci_adi_set(ANA_REG_GLB_ARM_MODULE_EN,
772 BIT_ANA_EIC_EN | BIT_ANA_GPIO_EN);
773 sci_adi_set(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_EIC_EN);
776 d_sci_gpio.base_addr = r[ENUM_ID_D_GPIO].base_addr;
777 d_sci_gpio.chip.base = r[ENUM_ID_D_GPIO].chip_base;
778 d_sci_gpio.chip.ngpio = r[ENUM_ID_D_GPIO].chip_ngpio;
780 d_sci_eic.base_addr = r[ENUM_ID_D_EIC].base_addr;
781 d_sci_eic.chip.base = r[ENUM_ID_D_EIC].chip_base;
782 d_sci_eic.chip.ngpio = r[ENUM_ID_D_EIC].chip_ngpio;
784 a_sci_gpio.base_addr = r[ENUM_ID_A_GPIO].base_addr;
785 a_sci_gpio.chip.base = r[ENUM_ID_A_GPIO].chip_base;
786 a_sci_gpio.chip.ngpio = r[ENUM_ID_A_GPIO].chip_ngpio;
788 a_sci_eic.base_addr = r[ENUM_ID_A_EIC].base_addr;
789 a_sci_eic.chip.base = r[ENUM_ID_A_EIC].chip_base;
790 a_sci_eic.chip.ngpio = r[ENUM_ID_A_EIC].chip_ngpio;
792 if (d_sci_eic.chip.ngpio > 0)
793 gpiochip_add(&d_sci_eic.chip);
795 if (d_sci_gpio.chip.ngpio > 0)
796 gpiochip_add(&d_sci_gpio.chip);
798 if (a_sci_eic.chip.ngpio > 0)
799 gpiochip_add(&a_sci_eic.chip);
801 if (a_sci_gpio.chip.ngpio > 0)
802 gpiochip_add(&a_sci_gpio.chip);
804 if (-1 != r[ENUM_ID_D_GPIO].irq) {
805 gpio_irq_init(r[ENUM_ID_D_GPIO].irq, &d_sci_gpio.chip,
807 setup_irq(r[ENUM_ID_D_GPIO].irq, &__d_gpio_irq);
810 if (-1 != r[ENUM_ID_D_EIC].irq) {
811 gpio_irq_init(r[ENUM_ID_D_EIC].irq, &d_sci_eic.chip,
813 setup_irq(r[ENUM_ID_D_EIC].irq, &__d_eic_irq);
816 if (-1 != r[ENUM_ID_A_GPIO].irq)
817 gpio_irq_init(r[ENUM_ID_A_GPIO].irq, &a_sci_gpio.chip,
820 if (-1 != r[ENUM_ID_A_EIC].irq)
821 gpio_irq_init(r[ENUM_ID_A_EIC].irq, &a_sci_eic.chip,
827 static int eic_gpio_remove(struct platform_device *pdev)
831 if (d_sci_eic.chip.ngpio > 0)
832 ret += gpiochip_remove(&d_sci_eic.chip);
833 if (d_sci_gpio.chip.ngpio > 0)
834 ret += gpiochip_remove(&d_sci_gpio.chip);
835 if (a_sci_eic.chip.ngpio > 0)
836 ret += gpiochip_remove(&a_sci_eic.chip);
837 if (a_sci_gpio.chip.ngpio > 0)
838 ret += gpiochip_remove(&a_sci_gpio.chip);
844 static struct platform_driver eic_gpio_driver = {
845 .driver.name = "eic-gpio",
846 .driver.owner = THIS_MODULE,
847 .driver.of_match_table = of_match_ptr(eic_gpio_match_table),
848 .probe = eic_gpio_probe,
849 .remove = eic_gpio_remove,
852 static int __init eic_gpio_init(void)
854 return platform_driver_register(&eic_gpio_driver);
857 postcore_initcall(eic_gpio_init);
859 static void __exit eic_gpio_exit(void)
861 return platform_driver_unregister(&eic_gpio_driver);
864 module_exit(eic_gpio_exit);