1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
9 #include <linux/bits.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
14 #include <linux/ioport.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqdesc.h>
17 #include <linux/isa.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/spinlock.h>
22 #include <linux/types.h>
24 #include "gpio-i8255.h"
26 MODULE_IMPORT_NS(I8255);
28 #define IDI_48_EXTENT 8
29 #define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
31 static unsigned int base[MAX_NUM_IDI_48];
32 static unsigned int num_idi_48;
33 module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
34 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
36 static unsigned int irq[MAX_NUM_IDI_48];
37 static unsigned int num_irq;
38 module_param_hw_array(irq, uint, irq, &num_irq, 0);
39 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
42 * struct idi_48_reg - device register structure
43 * @port0: Port 0 Inputs
45 * @port1: Port 1 Inputs
46 * @irq: Read: IRQ Status Register/IRQ Clear
47 * Write: IRQ Enable/Disable
57 * struct idi_48_gpio - GPIO device private data structure
58 * @chip: instance of the gpio_chip
59 * @lock: synchronization lock to prevent I/O race conditions
60 * @irq_mask: input bits affected by interrupts
61 * @reg: I/O address offset for the device registers
62 * @cos_enb: Change-Of-State IRQ enable boundaries mask
65 struct gpio_chip chip;
67 unsigned char irq_mask[6];
68 struct idi_48_reg __iomem *reg;
69 unsigned char cos_enb;
72 static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
74 return GPIO_LINE_DIRECTION_IN;
77 static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
82 static int idi_48_gpio_get(struct gpio_chip *chip, unsigned int offset)
84 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
85 void __iomem *const ppi = idi48gpio->reg;
87 return i8255_get(ppi, offset);
90 static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
93 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
94 void __iomem *const ppi = idi48gpio->reg;
96 i8255_get_multiple(ppi, mask, bits, chip->ngpio);
101 static void idi_48_irq_ack(struct irq_data *data)
105 static void idi_48_irq_mask(struct irq_data *data)
107 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
108 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
109 const unsigned int offset = irqd_to_hwirq(data);
110 const unsigned long boundary = offset / 8;
111 const unsigned long mask = BIT(offset % 8);
114 spin_lock_irqsave(&idi48gpio->lock, flags);
116 idi48gpio->irq_mask[boundary] &= ~mask;
118 /* Exit early if there are still input lines with IRQ unmasked */
119 if (idi48gpio->irq_mask[boundary])
122 idi48gpio->cos_enb &= ~BIT(boundary);
124 iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
127 spin_unlock_irqrestore(&idi48gpio->lock, flags);
130 static void idi_48_irq_unmask(struct irq_data *data)
132 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
133 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
134 const unsigned int offset = irqd_to_hwirq(data);
135 const unsigned long boundary = offset / 8;
136 const unsigned long mask = BIT(offset % 8);
137 unsigned int prev_irq_mask;
140 spin_lock_irqsave(&idi48gpio->lock, flags);
142 prev_irq_mask = idi48gpio->irq_mask[boundary];
144 idi48gpio->irq_mask[boundary] |= mask;
146 /* Exit early if IRQ was already unmasked for this boundary */
150 idi48gpio->cos_enb |= BIT(boundary);
152 iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
155 spin_unlock_irqrestore(&idi48gpio->lock, flags);
158 static int idi_48_irq_set_type(struct irq_data *data, unsigned int flow_type)
160 /* The only valid irq types are none and both-edges */
161 if (flow_type != IRQ_TYPE_NONE &&
162 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
168 static struct irq_chip idi_48_irqchip = {
169 .name = "104-idi-48",
170 .irq_ack = idi_48_irq_ack,
171 .irq_mask = idi_48_irq_mask,
172 .irq_unmask = idi_48_irq_unmask,
173 .irq_set_type = idi_48_irq_set_type
176 static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
178 struct idi_48_gpio *const idi48gpio = dev_id;
179 unsigned long cos_status;
180 unsigned long boundary;
181 unsigned long irq_mask;
182 unsigned long bit_num;
184 struct gpio_chip *const chip = &idi48gpio->chip;
186 spin_lock(&idi48gpio->lock);
188 cos_status = ioread8(&idi48gpio->reg->irq);
190 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
191 if (cos_status & BIT(6)) {
192 spin_unlock(&idi48gpio->lock);
196 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
199 for_each_set_bit(boundary, &cos_status, 6) {
200 irq_mask = idi48gpio->irq_mask[boundary];
202 for_each_set_bit(bit_num, &irq_mask, 8) {
203 gpio = bit_num + boundary * 8;
205 generic_handle_domain_irq(chip->irq.domain,
210 spin_unlock(&idi48gpio->lock);
215 #define IDI48_NGPIO 48
216 static const char *idi48_names[IDI48_NGPIO] = {
217 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
218 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
219 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
220 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
221 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
222 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
223 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
224 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
227 static int idi_48_irq_init_hw(struct gpio_chip *gc)
229 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
231 /* Disable IRQ by default */
232 iowrite8(0, &idi48gpio->reg->irq);
233 ioread8(&idi48gpio->reg->irq);
238 static int idi_48_probe(struct device *dev, unsigned int id)
240 struct idi_48_gpio *idi48gpio;
241 const char *const name = dev_name(dev);
242 struct gpio_irq_chip *girq;
245 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
249 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
250 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
251 base[id], base[id] + IDI_48_EXTENT);
255 idi48gpio->reg = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
259 idi48gpio->chip.label = name;
260 idi48gpio->chip.parent = dev;
261 idi48gpio->chip.owner = THIS_MODULE;
262 idi48gpio->chip.base = -1;
263 idi48gpio->chip.ngpio = IDI48_NGPIO;
264 idi48gpio->chip.names = idi48_names;
265 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
266 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
267 idi48gpio->chip.get = idi_48_gpio_get;
268 idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
270 girq = &idi48gpio->chip.irq;
271 girq->chip = &idi_48_irqchip;
272 /* This will let us handle the parent IRQ in the driver */
273 girq->parent_handler = NULL;
274 girq->num_parents = 0;
275 girq->parents = NULL;
276 girq->default_type = IRQ_TYPE_NONE;
277 girq->handler = handle_edge_irq;
278 girq->init_hw = idi_48_irq_init_hw;
280 spin_lock_init(&idi48gpio->lock);
282 err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
284 dev_err(dev, "GPIO registering failed (%d)\n", err);
288 err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
291 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
298 static struct isa_driver idi_48_driver = {
299 .probe = idi_48_probe,
304 module_isa_driver_with_irq(idi_48_driver, num_idi_48, num_irq);
306 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
307 MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
308 MODULE_LICENSE("GPL v2");