1 // SPDX-License-Identifier: GPL-2.0+
3 * GPIO driver for TI DaVinci DA8xx SOCs.
5 * (C) Copyright 2011 Guralp Systems Ltd.
6 * Laurence Withers <lwithers@guralp.com>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/davinci_misc.h>
17 #ifndef CONFIG_DM_GPIO
18 static struct gpio_registry {
20 char name[GPIO_NAME_SIZE];
21 } gpio_registry[MAX_NUM_GPIOS];
23 #if defined(CONFIG_SOC_DA8XX)
24 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
26 #if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
27 static const struct pinmux_config gpio_pinmux[] = {
28 { pinmux(13), 8, 6 }, /* GP0[0] */
44 { pinmux(15), 8, 6 }, /* GP1[0] */
60 { pinmux(17), 8, 6 }, /* GP2[0] */
76 { pinmux(10), 8, 1 }, /* GP3[0] */
92 { pinmux(12), 8, 4 }, /* GP4[0] */
100 { pinmux(13), 8, 4 },
101 { pinmux(13), 8, 5 },
102 { pinmux(11), 8, 7 },
103 { pinmux(12), 8, 0 },
104 { pinmux(12), 8, 1 },
105 { pinmux(12), 8, 2 },
106 { pinmux(12), 8, 3 },
108 { pinmux(7), 8, 3 }, /* GP5[0] */
124 { pinmux(5), 8, 1 }, /* GP6[0] */
140 { pinmux(1), 8, 0 }, /* GP7[0] */
157 #else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
158 static const struct pinmux_config gpio_pinmux[] = {
159 { pinmux(1), 8, 7 }, /* GP0[0] */
175 { pinmux(4), 8, 7 }, /* GP1[0] */
191 { pinmux(6), 8, 7 }, /* GP2[0] */
207 { pinmux(8), 8, 7 }, /* GP3[0] */
223 { pinmux(10), 8, 7 }, /* GP4[0] */
224 { pinmux(10), 8, 6 },
225 { pinmux(10), 8, 5 },
226 { pinmux(10), 8, 4 },
227 { pinmux(10), 8, 3 },
228 { pinmux(10), 8, 2 },
229 { pinmux(10), 8, 1 },
230 { pinmux(10), 8, 0 },
239 { pinmux(12), 8, 7 }, /* GP5[0] */
240 { pinmux(12), 8, 6 },
241 { pinmux(12), 8, 5 },
242 { pinmux(12), 8, 4 },
243 { pinmux(12), 8, 3 },
244 { pinmux(12), 8, 2 },
245 { pinmux(12), 8, 1 },
246 { pinmux(12), 8, 0 },
247 { pinmux(11), 8, 7 },
248 { pinmux(11), 8, 6 },
249 { pinmux(11), 8, 5 },
250 { pinmux(11), 8, 4 },
251 { pinmux(11), 8, 3 },
252 { pinmux(11), 8, 2 },
253 { pinmux(11), 8, 1 },
254 { pinmux(11), 8, 0 },
255 { pinmux(19), 8, 6 }, /* GP6[0] */
256 { pinmux(19), 8, 5 },
257 { pinmux(19), 8, 4 },
258 { pinmux(19), 8, 3 },
259 { pinmux(19), 8, 2 },
260 { pinmux(16), 8, 1 },
261 { pinmux(14), 8, 1 },
262 { pinmux(14), 8, 0 },
263 { pinmux(13), 8, 7 },
264 { pinmux(13), 8, 6 },
265 { pinmux(13), 8, 5 },
266 { pinmux(13), 8, 4 },
267 { pinmux(13), 8, 3 },
268 { pinmux(13), 8, 2 },
269 { pinmux(13), 8, 1 },
270 { pinmux(13), 8, 0 },
271 { pinmux(18), 8, 1 }, /* GP7[0] */
272 { pinmux(18), 8, 0 },
273 { pinmux(17), 8, 7 },
274 { pinmux(17), 8, 6 },
275 { pinmux(17), 8, 5 },
276 { pinmux(17), 8, 4 },
277 { pinmux(17), 8, 3 },
278 { pinmux(17), 8, 2 },
279 { pinmux(17), 8, 1 },
280 { pinmux(17), 8, 0 },
281 { pinmux(16), 8, 7 },
282 { pinmux(16), 8, 6 },
283 { pinmux(16), 8, 5 },
284 { pinmux(16), 8, 4 },
285 { pinmux(16), 8, 3 },
286 { pinmux(16), 8, 2 },
287 { pinmux(19), 8, 0 }, /* GP8[0] */
295 { pinmux(19), 8, 1 },
296 { pinmux(19), 8, 0 },
297 { pinmux(18), 8, 7 },
298 { pinmux(18), 8, 6 },
299 { pinmux(18), 8, 5 },
300 { pinmux(18), 8, 4 },
301 { pinmux(18), 8, 3 },
302 { pinmux(18), 8, 2 },
304 #endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
305 #else /* !CONFIG_SOC_DA8XX */
306 #define davinci_configure_pin_mux(a, b)
307 #endif /* CONFIG_SOC_DA8XX */
309 int gpio_request(unsigned int gpio, const char *label)
311 if (gpio >= MAX_NUM_GPIOS)
314 if (gpio_registry[gpio].is_registered)
317 gpio_registry[gpio].is_registered = 1;
318 strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE);
319 gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0;
321 davinci_configure_pin_mux(&gpio_pinmux[gpio], 1);
326 int gpio_free(unsigned int gpio)
328 if (gpio >= MAX_NUM_GPIOS)
331 if (!gpio_registry[gpio].is_registered)
334 gpio_registry[gpio].is_registered = 0;
335 gpio_registry[gpio].name[0] = '\0';
336 /* Do not configure as input or change pin mux here */
341 static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio, int value)
343 clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
344 gpio_set_value(gpio, value);
348 static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio)
350 setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
354 static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio)
357 ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio));
361 static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value)
364 bank->set_data = 1U << GPIO_BIT(gpio);
366 bank->clr_data = 1U << GPIO_BIT(gpio);
371 static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio)
373 return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio));
376 #ifndef CONFIG_DM_GPIO
380 unsigned int gpio, dir, val;
381 struct davinci_gpio *bank;
383 for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) {
384 bank = GPIO_BANK(gpio);
385 dir = _gpio_get_dir(bank, gpio);
386 val = gpio_get_value(gpio);
388 printf("% 4d: %s: %d [%c] %s\n",
389 gpio, dir ? " in" : "out", val,
390 gpio_registry[gpio].is_registered ? 'x' : ' ',
391 gpio_registry[gpio].name);
395 int gpio_direction_input(unsigned int gpio)
397 struct davinci_gpio *bank;
399 bank = GPIO_BANK(gpio);
400 return _gpio_direction_input(bank, gpio);
403 int gpio_direction_output(unsigned int gpio, int value)
405 struct davinci_gpio *bank;
407 bank = GPIO_BANK(gpio);
408 return _gpio_direction_output(bank, gpio, value);
411 int gpio_get_value(unsigned int gpio)
413 struct davinci_gpio *bank;
415 bank = GPIO_BANK(gpio);
416 return _gpio_get_value(bank, gpio);
419 int gpio_set_value(unsigned int gpio, int value)
421 struct davinci_gpio *bank;
423 bank = GPIO_BANK(gpio);
424 return _gpio_set_value(bank, gpio, value);
427 #else /* CONFIG_DM_GPIO */
429 static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
431 struct davinci_gpio_bank *bank = dev_get_priv(dev);
433 /* The device tree is not broken into banks but the infrastructure is
434 * expecting it this way, so we'll first include the 0x10 offset, then
435 * calculate the bank manually based on the offset.
438 return ((struct davinci_gpio *)bank->base) + 0x10 + (offset >> 5);
441 static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset)
443 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
445 _gpio_direction_input(base, offset);
449 static int davinci_gpio_direction_output(struct udevice *dev, unsigned int offset,
452 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
454 _gpio_direction_output(base, offset, value);
458 static int davinci_gpio_get_value(struct udevice *dev, unsigned int offset)
460 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
462 return _gpio_get_value(base, offset);
465 static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset,
468 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
470 _gpio_set_value(base, offset, value);
475 static int davinci_gpio_get_function(struct udevice *dev, unsigned int offset)
478 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
480 dir = _gpio_get_dir(base, offset);
488 static const struct dm_gpio_ops gpio_davinci_ops = {
489 .direction_input = davinci_gpio_direction_input,
490 .direction_output = davinci_gpio_direction_output,
491 .get_value = davinci_gpio_get_value,
492 .set_value = davinci_gpio_set_value,
493 .get_function = davinci_gpio_get_function,
496 static int davinci_gpio_probe(struct udevice *dev)
498 struct davinci_gpio_bank *bank = dev_get_priv(dev);
499 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
500 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
501 const void *fdt = gd->fdt_blob;
502 int node = dev_of_offset(dev);
504 uc_priv->bank_name = plat->port_name;
505 uc_priv->gpio_count = fdtdec_get_int(fdt, node, "ti,ngpio", -1);
506 bank->base = (struct davinci_gpio *)plat->base;
510 static const struct udevice_id davinci_gpio_ids[] = {
511 { .compatible = "ti,dm6441-gpio" },
515 static int davinci_gpio_ofdata_to_platdata(struct udevice *dev)
517 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
520 addr = devfdt_get_addr(dev);
521 if (addr == FDT_ADDR_T_NONE)
528 U_BOOT_DRIVER(gpio_davinci) = {
529 .name = "gpio_davinci",
531 .ops = &gpio_davinci_ops,
532 .ofdata_to_platdata = of_match_ptr(davinci_gpio_ofdata_to_platdata),
533 .of_match = davinci_gpio_ids,
534 .bind = dm_scan_fdt_dev,
535 .platdata_auto_alloc_size = sizeof(struct davinci_gpio_platdata),
536 .probe = davinci_gpio_probe,
537 .priv_auto_alloc_size = sizeof(struct davinci_gpio_bank),