1 // SPDX-License-Identifier: GPL-2.0+
3 * GPIO driver for TI DaVinci DA8xx SOCs.
5 * (C) Copyright 2011 Guralp Systems Ltd.
6 * Laurence Withers <lwithers@guralp.com>
15 #include <dt-bindings/gpio/gpio.h>
17 #include "da8xx_gpio.h"
19 #if !CONFIG_IS_ENABLED(DM_GPIO)
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/davinci_misc.h>
23 static struct gpio_registry {
25 char name[GPIO_NAME_SIZE];
26 } gpio_registry[MAX_NUM_GPIOS];
28 #if defined(CONFIG_SOC_DA8XX)
29 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
31 #if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
32 static const struct pinmux_config gpio_pinmux[] = {
33 { pinmux(13), 8, 6 }, /* GP0[0] */
49 { pinmux(15), 8, 6 }, /* GP1[0] */
65 { pinmux(17), 8, 6 }, /* GP2[0] */
81 { pinmux(10), 8, 1 }, /* GP3[0] */
97 { pinmux(12), 8, 4 }, /* GP4[0] */
100 { pinmux(12), 8, 7 },
101 { pinmux(13), 8, 0 },
102 { pinmux(13), 8, 1 },
103 { pinmux(13), 8, 2 },
104 { pinmux(13), 8, 3 },
105 { pinmux(13), 8, 4 },
106 { pinmux(13), 8, 5 },
107 { pinmux(11), 8, 7 },
108 { pinmux(12), 8, 0 },
109 { pinmux(12), 8, 1 },
110 { pinmux(12), 8, 2 },
111 { pinmux(12), 8, 3 },
113 { pinmux(7), 8, 3 }, /* GP5[0] */
129 { pinmux(5), 8, 1 }, /* GP6[0] */
145 { pinmux(1), 8, 0 }, /* GP7[0] */
162 #else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
163 static const struct pinmux_config gpio_pinmux[] = {
164 { pinmux(1), 8, 7 }, /* GP0[0] */
180 { pinmux(4), 8, 7 }, /* GP1[0] */
196 { pinmux(6), 8, 7 }, /* GP2[0] */
212 { pinmux(8), 8, 7 }, /* GP3[0] */
228 { pinmux(10), 8, 7 }, /* GP4[0] */
229 { pinmux(10), 8, 6 },
230 { pinmux(10), 8, 5 },
231 { pinmux(10), 8, 4 },
232 { pinmux(10), 8, 3 },
233 { pinmux(10), 8, 2 },
234 { pinmux(10), 8, 1 },
235 { pinmux(10), 8, 0 },
244 { pinmux(12), 8, 7 }, /* GP5[0] */
245 { pinmux(12), 8, 6 },
246 { pinmux(12), 8, 5 },
247 { pinmux(12), 8, 4 },
248 { pinmux(12), 8, 3 },
249 { pinmux(12), 8, 2 },
250 { pinmux(12), 8, 1 },
251 { pinmux(12), 8, 0 },
252 { pinmux(11), 8, 7 },
253 { pinmux(11), 8, 6 },
254 { pinmux(11), 8, 5 },
255 { pinmux(11), 8, 4 },
256 { pinmux(11), 8, 3 },
257 { pinmux(11), 8, 2 },
258 { pinmux(11), 8, 1 },
259 { pinmux(11), 8, 0 },
260 { pinmux(19), 8, 6 }, /* GP6[0] */
261 { pinmux(19), 8, 5 },
262 { pinmux(19), 8, 4 },
263 { pinmux(19), 8, 3 },
264 { pinmux(19), 8, 2 },
265 { pinmux(16), 8, 1 },
266 { pinmux(14), 8, 1 },
267 { pinmux(14), 8, 0 },
268 { pinmux(13), 8, 7 },
269 { pinmux(13), 8, 6 },
270 { pinmux(13), 8, 5 },
271 { pinmux(13), 8, 4 },
272 { pinmux(13), 8, 3 },
273 { pinmux(13), 8, 2 },
274 { pinmux(13), 8, 1 },
275 { pinmux(13), 8, 0 },
276 { pinmux(18), 8, 1 }, /* GP7[0] */
277 { pinmux(18), 8, 0 },
278 { pinmux(17), 8, 7 },
279 { pinmux(17), 8, 6 },
280 { pinmux(17), 8, 5 },
281 { pinmux(17), 8, 4 },
282 { pinmux(17), 8, 3 },
283 { pinmux(17), 8, 2 },
284 { pinmux(17), 8, 1 },
285 { pinmux(17), 8, 0 },
286 { pinmux(16), 8, 7 },
287 { pinmux(16), 8, 6 },
288 { pinmux(16), 8, 5 },
289 { pinmux(16), 8, 4 },
290 { pinmux(16), 8, 3 },
291 { pinmux(16), 8, 2 },
292 { pinmux(19), 8, 0 }, /* GP8[0] */
300 { pinmux(19), 8, 1 },
301 { pinmux(19), 8, 0 },
302 { pinmux(18), 8, 7 },
303 { pinmux(18), 8, 6 },
304 { pinmux(18), 8, 5 },
305 { pinmux(18), 8, 4 },
306 { pinmux(18), 8, 3 },
307 { pinmux(18), 8, 2 },
309 #endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
310 #else /* !CONFIG_SOC_DA8XX */
311 #define davinci_configure_pin_mux(a, b)
312 #endif /* CONFIG_SOC_DA8XX */
314 int gpio_request(unsigned int gpio, const char *label)
316 if (gpio >= MAX_NUM_GPIOS)
319 if (gpio_registry[gpio].is_registered)
322 gpio_registry[gpio].is_registered = 1;
323 strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE);
324 gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0;
326 davinci_configure_pin_mux(&gpio_pinmux[gpio], 1);
331 int gpio_free(unsigned int gpio)
333 if (gpio >= MAX_NUM_GPIOS)
336 if (!gpio_registry[gpio].is_registered)
339 gpio_registry[gpio].is_registered = 0;
340 gpio_registry[gpio].name[0] = '\0';
341 /* Do not configure as input or change pin mux here */
346 static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio)
348 setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
352 static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio)
355 ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio));
359 static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value)
362 bank->set_data = 1U << GPIO_BIT(gpio);
364 bank->clr_data = 1U << GPIO_BIT(gpio);
369 static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio)
371 return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio));
374 static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio,
377 clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
378 _gpio_set_value(bank, gpio, value);
382 #if !CONFIG_IS_ENABLED(DM_GPIO)
386 unsigned int gpio, dir, val;
387 struct davinci_gpio *bank;
389 for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) {
390 bank = GPIO_BANK(gpio);
391 dir = _gpio_get_dir(bank, gpio);
392 val = gpio_get_value(gpio);
394 printf("% 4d: %s: %d [%c] %s\n",
395 gpio, dir ? " in" : "out", val,
396 gpio_registry[gpio].is_registered ? 'x' : ' ',
397 gpio_registry[gpio].name);
401 int gpio_direction_input(unsigned int gpio)
403 struct davinci_gpio *bank;
405 bank = GPIO_BANK(gpio);
406 return _gpio_direction_input(bank, gpio);
409 int gpio_direction_output(unsigned int gpio, int value)
411 struct davinci_gpio *bank;
413 bank = GPIO_BANK(gpio);
414 return _gpio_direction_output(bank, gpio, value);
417 int gpio_get_value(unsigned int gpio)
419 struct davinci_gpio *bank;
421 bank = GPIO_BANK(gpio);
422 return _gpio_get_value(bank, gpio);
425 int gpio_set_value(unsigned int gpio, int value)
427 struct davinci_gpio *bank;
429 bank = GPIO_BANK(gpio);
430 return _gpio_set_value(bank, gpio, value);
435 static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
437 struct davinci_gpio_bank *bank = dev_get_priv(dev);
441 * The device tree is not broken into banks but the infrastructure is
442 * expecting it this way, so we'll first include the 0x10 offset, then
443 * calculate the bank manually based on the offset.
444 * Casting 'addr' as Unsigned long is needed to make the math work.
446 addr = ((unsigned long)(struct davinci_gpio *)bank->base) +
447 0x10 + (0x28 * (offset >> 5));
448 return (struct davinci_gpio *)addr;
451 static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset)
453 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
456 * Fetch the address based on GPIO, but only pass the masked low 32-bits
458 _gpio_direction_input(base, (offset & 0x1f));
462 static int davinci_gpio_direction_output(struct udevice *dev, unsigned int offset,
465 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
467 _gpio_direction_output(base, (offset & 0x1f), value);
471 static int davinci_gpio_get_value(struct udevice *dev, unsigned int offset)
473 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
475 return _gpio_get_value(base, (offset & 0x1f));
478 static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset,
481 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
483 _gpio_set_value(base, (offset & 0x1f), value);
488 static int davinci_gpio_get_function(struct udevice *dev, unsigned int offset)
491 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
493 dir = _gpio_get_dir(base, offset);
501 static int davinci_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
502 struct ofnode_phandle_args *args)
504 desc->offset = args->args[0];
506 if (args->args[1] & GPIO_ACTIVE_LOW)
507 desc->flags = GPIOD_ACTIVE_LOW;
513 static const struct dm_gpio_ops gpio_davinci_ops = {
514 .direction_input = davinci_gpio_direction_input,
515 .direction_output = davinci_gpio_direction_output,
516 .get_value = davinci_gpio_get_value,
517 .set_value = davinci_gpio_set_value,
518 .get_function = davinci_gpio_get_function,
519 .xlate = davinci_gpio_xlate,
522 static int davinci_gpio_probe(struct udevice *dev)
524 struct davinci_gpio_bank *bank = dev_get_priv(dev);
525 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
526 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
527 const void *fdt = gd->fdt_blob;
528 int node = dev_of_offset(dev);
530 uc_priv->bank_name = plat->port_name;
531 uc_priv->gpio_count = fdtdec_get_int(fdt, node, "ti,ngpio", -1);
532 bank->base = (struct davinci_gpio *)plat->base;
536 static const struct udevice_id davinci_gpio_ids[] = {
537 { .compatible = "ti,dm6441-gpio" },
538 { .compatible = "ti,k2g-gpio" },
539 { .compatible = "ti,keystone-gpio" },
543 static int davinci_gpio_ofdata_to_platdata(struct udevice *dev)
545 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
548 addr = devfdt_get_addr(dev);
549 if (addr == FDT_ADDR_T_NONE)
556 U_BOOT_DRIVER(ti_dm6441_gpio) = {
557 .name = "ti_dm6441_gpio",
559 .ops = &gpio_davinci_ops,
560 .ofdata_to_platdata = of_match_ptr(davinci_gpio_ofdata_to_platdata),
561 .of_match = davinci_gpio_ids,
562 .bind = dm_scan_fdt_dev,
563 .platdata_auto_alloc_size = sizeof(struct davinci_gpio_platdata),
564 .probe = davinci_gpio_probe,
565 .priv_auto_alloc_size = sizeof(struct davinci_gpio_bank),