1 // SPDX-License-Identifier: GPL-2.0+
3 * GPIO driver for TI DaVinci DA8xx SOCs.
5 * (C) Copyright 2011 Guralp Systems Ltd.
6 * Laurence Withers <lwithers@guralp.com>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/davinci_misc.h>
16 #include <dt-bindings/gpio/gpio.h>
18 #ifndef CONFIG_DM_GPIO
19 static struct gpio_registry {
21 char name[GPIO_NAME_SIZE];
22 } gpio_registry[MAX_NUM_GPIOS];
24 #if defined(CONFIG_SOC_DA8XX)
25 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
27 #if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
28 static const struct pinmux_config gpio_pinmux[] = {
29 { pinmux(13), 8, 6 }, /* GP0[0] */
45 { pinmux(15), 8, 6 }, /* GP1[0] */
61 { pinmux(17), 8, 6 }, /* GP2[0] */
77 { pinmux(10), 8, 1 }, /* GP3[0] */
93 { pinmux(12), 8, 4 }, /* GP4[0] */
100 { pinmux(13), 8, 3 },
101 { pinmux(13), 8, 4 },
102 { pinmux(13), 8, 5 },
103 { pinmux(11), 8, 7 },
104 { pinmux(12), 8, 0 },
105 { pinmux(12), 8, 1 },
106 { pinmux(12), 8, 2 },
107 { pinmux(12), 8, 3 },
109 { pinmux(7), 8, 3 }, /* GP5[0] */
125 { pinmux(5), 8, 1 }, /* GP6[0] */
141 { pinmux(1), 8, 0 }, /* GP7[0] */
158 #else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
159 static const struct pinmux_config gpio_pinmux[] = {
160 { pinmux(1), 8, 7 }, /* GP0[0] */
176 { pinmux(4), 8, 7 }, /* GP1[0] */
192 { pinmux(6), 8, 7 }, /* GP2[0] */
208 { pinmux(8), 8, 7 }, /* GP3[0] */
224 { pinmux(10), 8, 7 }, /* GP4[0] */
225 { pinmux(10), 8, 6 },
226 { pinmux(10), 8, 5 },
227 { pinmux(10), 8, 4 },
228 { pinmux(10), 8, 3 },
229 { pinmux(10), 8, 2 },
230 { pinmux(10), 8, 1 },
231 { pinmux(10), 8, 0 },
240 { pinmux(12), 8, 7 }, /* GP5[0] */
241 { pinmux(12), 8, 6 },
242 { pinmux(12), 8, 5 },
243 { pinmux(12), 8, 4 },
244 { pinmux(12), 8, 3 },
245 { pinmux(12), 8, 2 },
246 { pinmux(12), 8, 1 },
247 { pinmux(12), 8, 0 },
248 { pinmux(11), 8, 7 },
249 { pinmux(11), 8, 6 },
250 { pinmux(11), 8, 5 },
251 { pinmux(11), 8, 4 },
252 { pinmux(11), 8, 3 },
253 { pinmux(11), 8, 2 },
254 { pinmux(11), 8, 1 },
255 { pinmux(11), 8, 0 },
256 { pinmux(19), 8, 6 }, /* GP6[0] */
257 { pinmux(19), 8, 5 },
258 { pinmux(19), 8, 4 },
259 { pinmux(19), 8, 3 },
260 { pinmux(19), 8, 2 },
261 { pinmux(16), 8, 1 },
262 { pinmux(14), 8, 1 },
263 { pinmux(14), 8, 0 },
264 { pinmux(13), 8, 7 },
265 { pinmux(13), 8, 6 },
266 { pinmux(13), 8, 5 },
267 { pinmux(13), 8, 4 },
268 { pinmux(13), 8, 3 },
269 { pinmux(13), 8, 2 },
270 { pinmux(13), 8, 1 },
271 { pinmux(13), 8, 0 },
272 { pinmux(18), 8, 1 }, /* GP7[0] */
273 { pinmux(18), 8, 0 },
274 { pinmux(17), 8, 7 },
275 { pinmux(17), 8, 6 },
276 { pinmux(17), 8, 5 },
277 { pinmux(17), 8, 4 },
278 { pinmux(17), 8, 3 },
279 { pinmux(17), 8, 2 },
280 { pinmux(17), 8, 1 },
281 { pinmux(17), 8, 0 },
282 { pinmux(16), 8, 7 },
283 { pinmux(16), 8, 6 },
284 { pinmux(16), 8, 5 },
285 { pinmux(16), 8, 4 },
286 { pinmux(16), 8, 3 },
287 { pinmux(16), 8, 2 },
288 { pinmux(19), 8, 0 }, /* GP8[0] */
296 { pinmux(19), 8, 1 },
297 { pinmux(19), 8, 0 },
298 { pinmux(18), 8, 7 },
299 { pinmux(18), 8, 6 },
300 { pinmux(18), 8, 5 },
301 { pinmux(18), 8, 4 },
302 { pinmux(18), 8, 3 },
303 { pinmux(18), 8, 2 },
305 #endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
306 #else /* !CONFIG_SOC_DA8XX */
307 #define davinci_configure_pin_mux(a, b)
308 #endif /* CONFIG_SOC_DA8XX */
310 int gpio_request(unsigned int gpio, const char *label)
312 if (gpio >= MAX_NUM_GPIOS)
315 if (gpio_registry[gpio].is_registered)
318 gpio_registry[gpio].is_registered = 1;
319 strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE);
320 gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0;
322 davinci_configure_pin_mux(&gpio_pinmux[gpio], 1);
327 int gpio_free(unsigned int gpio)
329 if (gpio >= MAX_NUM_GPIOS)
332 if (!gpio_registry[gpio].is_registered)
335 gpio_registry[gpio].is_registered = 0;
336 gpio_registry[gpio].name[0] = '\0';
337 /* Do not configure as input or change pin mux here */
342 static int _gpio_direction_output(struct davinci_gpio *bank, unsigned int gpio, int value)
344 clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
345 gpio_set_value(gpio, value);
349 static int _gpio_direction_input(struct davinci_gpio *bank, unsigned int gpio)
351 setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio));
355 static int _gpio_get_value(struct davinci_gpio *bank, unsigned int gpio)
358 ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio));
362 static int _gpio_set_value(struct davinci_gpio *bank, unsigned int gpio, int value)
365 bank->set_data = 1U << GPIO_BIT(gpio);
367 bank->clr_data = 1U << GPIO_BIT(gpio);
372 static int _gpio_get_dir(struct davinci_gpio *bank, unsigned int gpio)
374 return in_le32(&bank->dir) & (1U << GPIO_BIT(gpio));
377 #ifndef CONFIG_DM_GPIO
381 unsigned int gpio, dir, val;
382 struct davinci_gpio *bank;
384 for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) {
385 bank = GPIO_BANK(gpio);
386 dir = _gpio_get_dir(bank, gpio);
387 val = gpio_get_value(gpio);
389 printf("% 4d: %s: %d [%c] %s\n",
390 gpio, dir ? " in" : "out", val,
391 gpio_registry[gpio].is_registered ? 'x' : ' ',
392 gpio_registry[gpio].name);
396 int gpio_direction_input(unsigned int gpio)
398 struct davinci_gpio *bank;
400 bank = GPIO_BANK(gpio);
401 return _gpio_direction_input(bank, gpio);
404 int gpio_direction_output(unsigned int gpio, int value)
406 struct davinci_gpio *bank;
408 bank = GPIO_BANK(gpio);
409 return _gpio_direction_output(bank, gpio, value);
412 int gpio_get_value(unsigned int gpio)
414 struct davinci_gpio *bank;
416 bank = GPIO_BANK(gpio);
417 return _gpio_get_value(bank, gpio);
420 int gpio_set_value(unsigned int gpio, int value)
422 struct davinci_gpio *bank;
424 bank = GPIO_BANK(gpio);
425 return _gpio_set_value(bank, gpio, value);
428 #else /* CONFIG_DM_GPIO */
430 static struct davinci_gpio *davinci_get_gpio_bank(struct udevice *dev, unsigned int offset)
432 struct davinci_gpio_bank *bank = dev_get_priv(dev);
436 * The device tree is not broken into banks but the infrastructure is
437 * expecting it this way, so we'll first include the 0x10 offset, then
438 * calculate the bank manually based on the offset.
439 * Casting 'addr' as Unsigned long is needed to make the math work.
441 addr = ((unsigned long)(struct davinci_gpio *)bank->base) +
442 0x10 + (0x28 * (offset >> 5));
443 return (struct davinci_gpio *)addr;
446 static int davinci_gpio_direction_input(struct udevice *dev, unsigned int offset)
448 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
451 * Fetch the address based on GPIO, but only pass the masked low 32-bits
453 _gpio_direction_input(base, (offset & 0x1f));
457 static int davinci_gpio_direction_output(struct udevice *dev, unsigned int offset,
460 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
462 _gpio_direction_output(base, (offset & 0x1f), value);
466 static int davinci_gpio_get_value(struct udevice *dev, unsigned int offset)
468 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
470 return _gpio_get_value(base, (offset & 0x1f));
473 static int davinci_gpio_set_value(struct udevice *dev, unsigned int offset,
476 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
478 _gpio_set_value(base, (offset & 0x1f), value);
483 static int davinci_gpio_get_function(struct udevice *dev, unsigned int offset)
486 struct davinci_gpio *base = davinci_get_gpio_bank(dev, offset);
488 dir = _gpio_get_dir(base, offset);
496 static int davinci_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
497 struct ofnode_phandle_args *args)
499 desc->offset = args->args[0];
501 if (args->args[1] & GPIO_ACTIVE_LOW)
502 desc->flags = GPIOD_ACTIVE_LOW;
508 static const struct dm_gpio_ops gpio_davinci_ops = {
509 .direction_input = davinci_gpio_direction_input,
510 .direction_output = davinci_gpio_direction_output,
511 .get_value = davinci_gpio_get_value,
512 .set_value = davinci_gpio_set_value,
513 .get_function = davinci_gpio_get_function,
514 .xlate = davinci_gpio_xlate,
517 static int davinci_gpio_probe(struct udevice *dev)
519 struct davinci_gpio_bank *bank = dev_get_priv(dev);
520 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
521 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
522 const void *fdt = gd->fdt_blob;
523 int node = dev_of_offset(dev);
525 uc_priv->bank_name = plat->port_name;
526 uc_priv->gpio_count = fdtdec_get_int(fdt, node, "ti,ngpio", -1);
527 bank->base = (struct davinci_gpio *)plat->base;
531 static const struct udevice_id davinci_gpio_ids[] = {
532 { .compatible = "ti,dm6441-gpio" },
536 static int davinci_gpio_ofdata_to_platdata(struct udevice *dev)
538 struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
541 addr = devfdt_get_addr(dev);
542 if (addr == FDT_ADDR_T_NONE)
549 U_BOOT_DRIVER(gpio_davinci) = {
550 .name = "gpio_davinci",
552 .ops = &gpio_davinci_ops,
553 .ofdata_to_platdata = of_match_ptr(davinci_gpio_ofdata_to_platdata),
554 .of_match = davinci_gpio_ids,
555 .bind = dm_scan_fdt_dev,
556 .platdata_auto_alloc_size = sizeof(struct davinci_gpio_platdata),
557 .probe = davinci_gpio_probe,
558 .priv_auto_alloc_size = sizeof(struct davinci_gpio_bank),