1 // SPDX-License-Identifier: GPL-2.0+
3 * Atmel PIO4 device driver
5 * Copyright (C) 2015 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
12 #include <asm/arch/hardware.h>
14 #include <mach/gpio.h>
15 #include <mach/atmel_pio4.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
21 struct atmel_pio4_port *base = NULL;
25 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
28 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
31 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
34 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
37 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
45 static int atmel_pio4_config_io_func(u32 port, u32 pin,
48 struct atmel_pio4_port *port_base;
51 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
54 port_base = atmel_pio4_port_base(port);
62 writel(mask, &port_base->mskr);
63 writel(reg, &port_base->cfgr);
68 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config)
70 return atmel_pio4_config_io_func(port, pin,
71 ATMEL_PIO_CFGR_FUNC_GPIO,
75 int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config)
77 return atmel_pio4_config_io_func(port, pin,
78 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
82 int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config)
84 return atmel_pio4_config_io_func(port, pin,
85 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
89 int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config)
91 return atmel_pio4_config_io_func(port, pin,
92 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
96 int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config)
98 return atmel_pio4_config_io_func(port, pin,
99 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
103 int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config)
105 return atmel_pio4_config_io_func(port, pin,
106 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
110 int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config)
112 return atmel_pio4_config_io_func(port, pin,
113 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
117 int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config)
119 return atmel_pio4_config_io_func(port, pin,
120 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
124 int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
126 struct atmel_pio4_port *port_base;
129 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
132 port_base = atmel_pio4_port_base(port);
137 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
139 writel(mask, &port_base->mskr);
140 writel(reg, &port_base->cfgr);
143 writel(mask, &port_base->sodr);
145 writel(mask, &port_base->codr);
150 int atmel_pio4_get_pio_input(u32 port, u32 pin)
152 struct atmel_pio4_port *port_base;
155 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
158 port_base = atmel_pio4_port_base(port);
163 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
165 writel(mask, &port_base->mskr);
166 writel(reg, &port_base->cfgr);
168 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
171 #ifdef CONFIG_DM_GPIO
173 struct atmel_pioctrl_data {
177 struct atmel_pio4_platdata {
178 struct atmel_pio4_port *reg_base;
181 static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
184 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
185 struct atmel_pio4_port *port_base =
186 (struct atmel_pio4_port *)((u32)plat->reg_base +
187 ATMEL_PIO_BANK_OFFSET * bank);
192 static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
194 u32 bank = ATMEL_PIO_BANK(offset);
195 u32 line = ATMEL_PIO_LINE(offset);
196 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
197 u32 mask = BIT(line);
199 writel(mask, &port_base->mskr);
201 clrbits_le32(&port_base->cfgr,
202 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
207 static int atmel_pio4_direction_output(struct udevice *dev,
208 unsigned offset, int value)
210 u32 bank = ATMEL_PIO_BANK(offset);
211 u32 line = ATMEL_PIO_LINE(offset);
212 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
213 u32 mask = BIT(line);
215 writel(mask, &port_base->mskr);
217 clrsetbits_le32(&port_base->cfgr,
218 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
221 writel(mask, &port_base->sodr);
223 writel(mask, &port_base->codr);
228 static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
230 u32 bank = ATMEL_PIO_BANK(offset);
231 u32 line = ATMEL_PIO_LINE(offset);
232 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
233 u32 mask = BIT(line);
235 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
238 static int atmel_pio4_set_value(struct udevice *dev,
239 unsigned offset, int value)
241 u32 bank = ATMEL_PIO_BANK(offset);
242 u32 line = ATMEL_PIO_LINE(offset);
243 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
244 u32 mask = BIT(line);
247 writel(mask, &port_base->sodr);
249 writel(mask, &port_base->codr);
254 static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
256 u32 bank = ATMEL_PIO_BANK(offset);
257 u32 line = ATMEL_PIO_LINE(offset);
258 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
259 u32 mask = BIT(line);
261 writel(mask, &port_base->mskr);
263 return (readl(&port_base->cfgr) &
264 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
267 static const struct dm_gpio_ops atmel_pio4_ops = {
268 .direction_input = atmel_pio4_direction_input,
269 .direction_output = atmel_pio4_direction_output,
270 .get_value = atmel_pio4_get_value,
271 .set_value = atmel_pio4_set_value,
272 .get_function = atmel_pio4_get_function,
275 static int atmel_pio4_bind(struct udevice *dev)
277 return dm_scan_fdt_dev(dev);
280 static int atmel_pio4_probe(struct udevice *dev)
282 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
283 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
284 struct atmel_pioctrl_data *pioctrl_data;
286 fdt_addr_t addr_base;
290 ret = clk_get_by_index(dev, 0, &clk);
294 ret = clk_enable(&clk);
300 addr_base = devfdt_get_addr(dev);
301 if (addr_base == FDT_ADDR_T_NONE)
304 plat->reg_base = (struct atmel_pio4_port *)addr_base;
306 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
307 nbanks = pioctrl_data->nbanks;
309 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
311 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
317 * The number of banks can be different from a SoC to another one.
318 * We can have up to 16 banks.
320 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
324 static const struct udevice_id atmel_pio4_ids[] = {
326 .compatible = "atmel,sama5d2-gpio",
327 .data = (ulong)&atmel_sama5d2_pioctrl_data,
332 U_BOOT_DRIVER(gpio_atmel_pio4) = {
333 .name = "gpio_atmel_pio4",
335 .ops = &atmel_pio4_ops,
336 .probe = atmel_pio4_probe,
337 .bind = atmel_pio4_bind,
338 .of_match = atmel_pio4_ids,
339 .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),