2 # GPIO infrastructure and drivers
8 bool "Enable Driver Model for GPIO drivers"
11 Enable driver model for GPIO access. The standard GPIO
12 interface (gpio_get_value(), etc.) is then implemented by
13 the GPIO uclass. Drivers provide methods to query the
14 particular GPIOs that they provide. The uclass interface
15 is defined in include/asm-generic/gpio.h.
18 bool "Altera PIO driver"
21 Select this to enable PIO for Altera devices. Please find
22 details on the "Embedded Peripherals IP User Guide" of Altera.
25 bool "BCM6345 GPIO driver"
26 depends on DM_GPIO && ARCH_BMIPS
28 This driver supports the GPIO banks on BCM6345 SoCs.
31 bool "DWAPB GPIO driver"
32 depends on DM && DM_GPIO
35 Support for the Designware APB GPIO driver.
38 bool "AT91 PIO GPIO driver"
42 Say yes here to select AT91 PIO GPIO driver. AT91 PIO
43 controller manages up to 32 fully programmable input/output
44 lines. Each I/O line may be dedicated as a general-purpose
45 I/O or be assigned to a function of an embedded peripheral.
46 The assignment to a function of an embedded peripheral is
47 the responsibility of AT91 Pinctrl driver. This driver is
48 responsible for the general-purpose I/O.
51 bool "ATMEL PIO4 driver"
55 Say yes here to support the Atmel PIO4 driver.
56 The PIO4 is new version of Atmel PIO controller, which manages
57 up to 128 fully programmable input/output lines. Each I/O line
58 may be dedicated as a general purpose I/O or be assigned to
59 a function of an embedded peripheral.
61 config INTEL_BROADWELL_GPIO
62 bool "Intel Broadwell GPIO driver"
65 This driver supports Broadwell U devices which have an expanded
66 GPIO feature set. The difference is large enough to merit a separate
67 driver from the common Intel ICH6 driver. It supports a total of
68 95 GPIOs which can be configured from the device tree.
71 bool "i.MX7ULP RGPIO2P driver"
75 This driver supports i.MX7ULP Rapid GPIO2P controller.
78 bool "LPC32XX GPIO driver"
82 Support for the LPC32XX GPIO driver.
85 bool "Qualcomm GPIO driver"
89 Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
90 This controller have single bank (default name "soc"), every
91 gpio has it's own set of registers.
92 Only simple GPIO operations are supported (get/set, change of
93 direction and checking pin function).
99 bool "TI OMAP GPIO driver"
100 depends on ARCH_OMAP2PLUS
103 Support GPIO controllers on the TI OMAP3/4/5 and related (such as
104 AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs.
107 bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
108 depends on DM_GPIO && PMIC_PM8916
110 Support for GPIO pins and power/reset buttons found on
111 Qualcomm PM8916 PMIC.
112 Default name for GPIO bank is "pm8916".
113 Power and reset buttons are placed in "pm8916_key" bank and
114 have gpio numbers 0 and 1 respectively.
117 bool "PCF8575 I2C GPIO Expander driver"
118 depends on DM_GPIO && DM_I2C
120 Support for PCF8575 I2C 16-bit GPIO expander. Most of these
121 chips are from NXP and TI.
124 bool "Rockchip GPIO driver"
127 Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
128 a number of banks (different for each SoC type) each with 32 GPIOs.
129 The GPIOs for a device are defined in the device tree with one node
133 bool "Enable sandbox GPIO driver"
134 depends on SANDBOX && DM && DM_GPIO
136 This driver supports some simulated GPIOs which can be adjusted
137 using 'back door' functions like sandbox_gpio_set_value(). Then the
138 GPIOs can be inspected through the normal get_get_value()
139 interface. The purpose of this is to allow GPIOs to be used as
140 normal in sandbox, perhaps with test code actually driving the
141 behaviour of those GPIOs.
143 config SANDBOX_GPIO_COUNT
144 int "Number of sandbox GPIOs"
145 depends on SANDBOX_GPIO
148 The sandbox driver can support any number of GPIOs. Generally these
149 are specified using the device tree. But you can also have a number
150 of 'anonymous' GPIOs that do not belong to any device or bank.
151 Select a suitable value depending on your needs.
154 bool "Tegra20..210 GPIO driver"
157 Support for the GPIO controller contained in NVIDIA Tegra20 through
161 bool "Tegra186 GPIO driver"
164 Support for the GPIO controller contained in NVIDIA Tegra186. This
165 covers both the "main" and "AON" controller instances, even though
166 they have slightly different register layout.
170 depends on ARCH_UNIPHIER
172 Say yes here to support UniPhier GPIOs.
175 bool "Vybrid GPIO driver"
179 Say yes here to support Vybrid vf610 GPIOs.
182 bool "Microchip PIC32 GPIO driver"
183 depends on DM_GPIO && MACH_PIC32
186 Say yes here to support Microchip PIC32 GPIOs.
189 bool "ST STM32 GPIO driver"
190 depends on DM_GPIO && STM32
193 Device model driver support for STM32 GPIO controller. It should be
194 usable on many stm32 families like stm32f4 & stm32H7.
198 bool "Marvell MVEBU GPIO driver"
199 depends on DM_GPIO && ARCH_MVEBU
202 Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.
205 bool "Zynq GPIO driver"
206 depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
209 Supports GPIO access on Zynq SoC.
212 bool "74x164 serial-in/parallel-out 8-bits shift register"
215 Driver for 74x164 compatible serial-in/parallel-out 8-outputs
216 shift registers, such as 74lv165, 74hc595.
217 This driver can be used to provide access to more gpio outputs.
220 bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
223 Say yes here to provide access to several register-oriented
224 SMBus I/O expanders, made mostly by NXP or TI. Compatible
227 4 bits: pca9536, pca9537
229 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
230 pca9556, pca9557, pca9574, tca6408, xra1202
232 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
237 40 bits: pca9505, pca9698
239 Now, max 24 bits chips and PCA953X compatible chips are
243 bool "Freescale MPC85XX GPIO driver"
246 This driver supports the built-in GPIO controller of MPC85XX CPUs.
247 Each GPIO bank is identified by its own entry in the device tree,
250 gpio-controller@fc00 {
252 compatible = "fsl,pq3-gpio";
256 By default, each bank is assumed to have 32 GPIOs, but the ngpios
257 setting is honored, so the number of GPIOs for each bank is
258 configurable to match the actual GPIO count of the SoC (e.g. the
259 32/32/23 banks of the P1022 SoC).
261 Aside from the standard functions of input/output mode, and output
262 value setting, the open-drain feature, which can configure individual
263 GPIOs to work as open-drain outputs, is supported.
265 The driver has been tested on MPC85XX, but it is likely that other
266 PowerQUICC III devices will work as well.