1 // SPDX-License-Identifier: GPL-2.0+
3 * Take drivers/gpio/gpio-74x164.c as reference.
5 * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
7 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
16 #include <asm/global_data.h>
19 #include <dm/device_compat.h>
20 #include <dt-bindings/gpio/gpio.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * struct gen_74x164_chip - Data for 74Hx164
29 * @nregs: number of registers
30 * @buffer: buffer for chained chips
32 #define GEN_74X164_NUMBER_GPIOS 8
34 struct gen_74x164_priv {
38 * Since the nregs are chained, every byte sent will make
39 * the previous byte shift to the next register in the
40 * chain. Thus, the first byte sent will end up in the last
41 * register at the end of the transfer. So, to have a logical
42 * numbering, store the bytes in reverse order.
47 static int gen_74x164_write_conf(struct udevice *dev)
49 struct gen_74x164_priv *priv = dev_get_priv(dev);
52 ret = dm_spi_claim_bus(dev);
56 ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
57 SPI_XFER_BEGIN | SPI_XFER_END);
59 dm_spi_release_bus(dev);
64 static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
66 struct gen_74x164_priv *priv = dev_get_priv(dev);
67 uint bank = priv->nregs - 1 - offset / 8;
68 uint pin = offset % 8;
70 return (priv->buffer[bank] >> pin) & 0x1;
73 static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
76 struct gen_74x164_priv *priv = dev_get_priv(dev);
77 uint bank = priv->nregs - 1 - offset / 8;
78 uint pin = offset % 8;
82 priv->buffer[bank] |= 1 << pin;
84 priv->buffer[bank] &= ~(1 << pin);
86 ret = gen_74x164_write_conf(dev);
93 static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
98 static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
101 return gen_74x164_set_value(dev, offset, value);
104 static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
109 static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
110 struct ofnode_phandle_args *args)
112 desc->offset = args->args[0];
113 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
118 static const struct dm_gpio_ops gen_74x164_ops = {
119 .direction_input = gen_74x164_direction_input,
120 .direction_output = gen_74x164_direction_output,
121 .get_value = gen_74x164_get_value,
122 .set_value = gen_74x164_set_value,
123 .get_function = gen_74x164_get_function,
124 .xlate = gen_74x164_xlate,
127 static int gen_74x164_probe(struct udevice *dev)
129 struct gen_74x164_priv *priv = dev_get_priv(dev);
130 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
133 const void *fdt = gd->fdt_blob;
134 int node = dev_of_offset(dev);
136 snprintf(name, sizeof(name), "%s_", dev->name);
143 * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
145 priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
146 priv->buffer = calloc(priv->nregs, sizeof(u8));
152 ret = fdtdec_get_byte_array(fdt, node, "registers-default",
153 priv->buffer, priv->nregs);
155 dev_dbg(dev, "No registers-default property\n");
157 ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
158 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
160 dev_dbg(dev, "No oe-pins property\n");
163 uc_priv->bank_name = str;
164 uc_priv->gpio_count = priv->nregs * 8;
166 ret = gen_74x164_write_conf(dev);
170 dev_dbg(dev, "%s is ready\n", dev->name);
181 static const struct udevice_id gen_74x164_ids[] = {
182 { .compatible = "fairchild,74hc595" },
186 U_BOOT_DRIVER(74x164) = {
189 .ops = &gen_74x164_ops,
190 .probe = gen_74x164_probe,
191 .priv_auto = sizeof(struct gen_74x164_priv),
192 .of_match = gen_74x164_ids,