1 // SPDX-License-Identifier: GPL-2.0+
3 * Take drivers/gpio/gpio-74x164.c as reference.
5 * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
7 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
18 #include <dt-bindings/gpio/gpio.h>
21 DECLARE_GLOBAL_DATA_PTR;
24 * struct gen_74x164_chip - Data for 74Hx164
27 * @nregs: number of registers
28 * @buffer: buffer for chained chips
30 #define GEN_74X164_NUMBER_GPIOS 8
32 struct gen_74x164_priv {
36 * Since the nregs are chained, every byte sent will make
37 * the previous byte shift to the next register in the
38 * chain. Thus, the first byte sent will end up in the last
39 * register at the end of the transfer. So, to have a logical
40 * numbering, store the bytes in reverse order.
45 static int gen_74x164_write_conf(struct udevice *dev)
47 struct gen_74x164_priv *priv = dev_get_priv(dev);
50 ret = dm_spi_claim_bus(dev);
54 ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
55 SPI_XFER_BEGIN | SPI_XFER_END);
57 dm_spi_release_bus(dev);
62 static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
64 struct gen_74x164_priv *priv = dev_get_priv(dev);
65 uint bank = priv->nregs - 1 - offset / 8;
66 uint pin = offset % 8;
68 return (priv->buffer[bank] >> pin) & 0x1;
71 static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
74 struct gen_74x164_priv *priv = dev_get_priv(dev);
75 uint bank = priv->nregs - 1 - offset / 8;
76 uint pin = offset % 8;
80 priv->buffer[bank] |= 1 << pin;
82 priv->buffer[bank] &= ~(1 << pin);
84 ret = gen_74x164_write_conf(dev);
91 static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
96 static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
99 return gen_74x164_set_value(dev, offset, value);
102 static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
107 static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
108 struct ofnode_phandle_args *args)
110 desc->offset = args->args[0];
111 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
116 static const struct dm_gpio_ops gen_74x164_ops = {
117 .direction_input = gen_74x164_direction_input,
118 .direction_output = gen_74x164_direction_output,
119 .get_value = gen_74x164_get_value,
120 .set_value = gen_74x164_set_value,
121 .get_function = gen_74x164_get_function,
122 .xlate = gen_74x164_xlate,
125 static int gen_74x164_probe(struct udevice *dev)
127 struct gen_74x164_priv *priv = dev_get_priv(dev);
128 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
131 const void *fdt = gd->fdt_blob;
132 int node = dev_of_offset(dev);
134 snprintf(name, sizeof(name), "%s_", dev->name);
141 * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
143 priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
144 priv->buffer = calloc(priv->nregs, sizeof(u8));
150 ret = fdtdec_get_byte_array(fdt, node, "registers-default",
151 priv->buffer, priv->nregs);
153 dev_dbg(dev, "No registers-default property\n");
155 ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
156 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
158 dev_dbg(dev, "No oe-pins property\n");
161 uc_priv->bank_name = str;
162 uc_priv->gpio_count = priv->nregs * 8;
164 ret = gen_74x164_write_conf(dev);
168 dev_dbg(dev, "%s is ready\n", dev->name);
179 static const struct udevice_id gen_74x164_ids[] = {
180 { .compatible = "fairchild,74hc595" },
184 U_BOOT_DRIVER(74x164) = {
187 .ops = &gen_74x164_ops,
188 .probe = gen_74x164_probe,
189 .priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
190 .of_match = gen_74x164_ids,