arm: Remove aspenite board
[platform/kernel/u-boot.git] / drivers / gpio / 74x164_gpio.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Take drivers/gpio/gpio-74x164.c as reference.
4  *
5  * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
6  *
7  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
8  *
9  */
10
11 #include <common.h>
12 #include <errno.h>
13 #include <dm.h>
14 #include <fdtdec.h>
15 #include <malloc.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/io.h>
19 #include <dm/device_compat.h>
20 #include <dt-bindings/gpio/gpio.h>
21 #include <spi.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /*
26  * struct gen_74x164_chip - Data for 74Hx164
27  *
28  * @oe: OE pin
29  * @nregs: number of registers
30  * @buffer: buffer for chained chips
31  */
32 #define GEN_74X164_NUMBER_GPIOS 8
33
34 struct gen_74x164_priv {
35         struct gpio_desc oe;
36         u32 nregs;
37         /*
38          * Since the nregs are chained, every byte sent will make
39          * the previous byte shift to the next register in the
40          * chain. Thus, the first byte sent will end up in the last
41          * register at the end of the transfer. So, to have a logical
42          * numbering, store the bytes in reverse order.
43          */
44         u8 *buffer;
45 };
46
47 static int gen_74x164_write_conf(struct udevice *dev)
48 {
49         struct gen_74x164_priv *priv = dev_get_priv(dev);
50         int ret;
51
52         ret = dm_spi_claim_bus(dev);
53         if (ret)
54                 return ret;
55
56         ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
57                           SPI_XFER_BEGIN | SPI_XFER_END);
58
59         dm_spi_release_bus(dev);
60
61         return ret;
62 }
63
64 static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
65 {
66         struct gen_74x164_priv *priv = dev_get_priv(dev);
67         uint bank = priv->nregs - 1 - offset / 8;
68         uint pin = offset % 8;
69
70         return (priv->buffer[bank] >> pin) & 0x1;
71 }
72
73 static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
74                                 int value)
75 {
76         struct gen_74x164_priv *priv = dev_get_priv(dev);
77         uint bank = priv->nregs - 1 - offset / 8;
78         uint pin = offset % 8;
79         int ret;
80
81         if (value)
82                 priv->buffer[bank] |= 1 << pin;
83         else
84                 priv->buffer[bank] &= ~(1 << pin);
85
86         ret = gen_74x164_write_conf(dev);
87         if (ret)
88                 return ret;
89
90         return 0;
91 }
92
93 static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
94 {
95         return -ENOSYS;
96 }
97
98 static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
99                                       int value)
100 {
101         return gen_74x164_set_value(dev, offset, value);
102 }
103
104 static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
105 {
106         return GPIOF_OUTPUT;
107 }
108
109 static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
110                             struct ofnode_phandle_args *args)
111 {
112         desc->offset = args->args[0];
113         desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
114
115         return 0;
116 }
117
118 static const struct dm_gpio_ops gen_74x164_ops = {
119         .direction_input        = gen_74x164_direction_input,
120         .direction_output       = gen_74x164_direction_output,
121         .get_value              = gen_74x164_get_value,
122         .set_value              = gen_74x164_set_value,
123         .get_function           = gen_74x164_get_function,
124         .xlate                  = gen_74x164_xlate,
125 };
126
127 static int gen_74x164_probe(struct udevice *dev)
128 {
129         struct gen_74x164_priv *priv = dev_get_priv(dev);
130         struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
131         char *str, name[32];
132         int ret;
133         const void *fdt = gd->fdt_blob;
134         int node = dev_of_offset(dev);
135
136         snprintf(name, sizeof(name), "%s_", dev->name);
137         str = strdup(name);
138         if (!str)
139                 return -ENOMEM;
140
141         /*
142          * See Linux kernel:
143          * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
144          */
145         priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
146         priv->buffer = calloc(priv->nregs, sizeof(u8));
147         if (!priv->buffer) {
148                 ret = -ENOMEM;
149                 goto free_str;
150         }
151
152         ret = fdtdec_get_byte_array(fdt, node, "registers-default",
153                                     priv->buffer, priv->nregs);
154         if (ret)
155                 dev_dbg(dev, "No registers-default property\n");
156
157         ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
158                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
159         if (ret) {
160                 dev_dbg(dev, "No oe-pins property\n");
161         }
162
163         uc_priv->bank_name = str;
164         uc_priv->gpio_count = priv->nregs * 8;
165
166         ret = gen_74x164_write_conf(dev);
167         if (ret)
168                 goto free_buf;
169
170         dev_dbg(dev, "%s is ready\n", dev->name);
171
172         return 0;
173
174 free_buf:
175         free(priv->buffer);
176 free_str:
177         free(str);
178         return ret;
179 }
180
181 static const struct udevice_id gen_74x164_ids[] = {
182         { .compatible = "fairchild,74hc595" },
183         { }
184 };
185
186 U_BOOT_DRIVER(74x164) = {
187         .name           = "74x164",
188         .id             = UCLASS_GPIO,
189         .ops            = &gen_74x164_ops,
190         .probe          = gen_74x164_probe,
191         .priv_auto      = sizeof(struct gen_74x164_priv),
192         .of_match       = gen_74x164_ids,
193 };