drivers/fpga/zynqmppl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 - 2016, Xilinx, Inc,
   4  * Michal Simek <michal.simek@xilinx.com>
   5  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
   6  */
   7
   8 #include <console.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <zynqmppl.h>
  12 #include <zynqmp_firmware.h>
  13 #include <asm/cache.h>
  14 #include <linux/sizes.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <memalign.h>
  17
  18 #define DUMMY_WORD      0xffffffff
  19
  20 /* Xilinx binary format header */
  21 static const u32 bin_format[] = {
  22         DUMMY_WORD, /* Dummy words */
  23         DUMMY_WORD,
  24         DUMMY_WORD,
  25         DUMMY_WORD,
  26         DUMMY_WORD,
  27         DUMMY_WORD,
  28         DUMMY_WORD,
  29         DUMMY_WORD,
  30         DUMMY_WORD,
  31         DUMMY_WORD,
  32         DUMMY_WORD,
  33         DUMMY_WORD,
  34         DUMMY_WORD,
  35         DUMMY_WORD,
  36         DUMMY_WORD,
  37         DUMMY_WORD,
  38         0x000000bb, /* Sync word */
  39         0x11220044, /* Sync word */
  40         DUMMY_WORD,
  41         DUMMY_WORD,
  42         0xaa995566, /* Sync word */
  43 };
  44
  45 #define SWAP_NO         1
  46 #define SWAP_DONE       2
  47
  48 /*
  49  * Load the whole word from unaligned buffer
  50  * Keep in your mind that it is byte loading on little-endian system
  51  */
  52 static u32 load_word(const void *buf, u32 swap)
  53 {
  54         u32 word = 0;
  55         u8 *bitc = (u8 *)buf;
  56         int p;
  57
  58         if (swap == SWAP_NO) {
  59                 for (p = 0; p < 4; p++) {
  60                         word <<= 8;
  61                         word |= bitc[p];
  62                 }
  63         } else {
  64                 for (p = 3; p >= 0; p--) {
  65                         word <<= 8;
  66                         word |= bitc[p];
  67                 }
  68         }
  69
  70         return word;
  71 }
  72
  73 static u32 check_header(const void *buf)
  74 {
  75         u32 i, pattern;
  76         int swap = SWAP_NO;
  77         u32 *test = (u32 *)buf;
  78
  79         debug("%s: Let's check bitstream header\n", __func__);
  80
  81         /* Checking that passing bin is not a bitstream */
  82         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  83                 pattern = load_word(&test[i], swap);
  84
  85                 /*
  86                  * Bitstreams in binary format are swapped
  87                  * compare to regular bistream.
  88                  * Do not swap dummy word but if swap is done assume
  89                  * that parsing buffer is binary format
  90                  */
  91                 if ((__swab32(pattern) != DUMMY_WORD) &&
  92                     (__swab32(pattern) == bin_format[i])) {
  93                         swap = SWAP_DONE;
  94                         debug("%s: data swapped - let's swap\n", __func__);
  95                 }
  96
  97                 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  98                       &test[i], pattern, bin_format[i]);
  99         }
 100         debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
 101               buf, swap == SWAP_NO ? "without" : "with");
 102
 103         return swap;
 104 }
 105
 106 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 107 {
 108         u32 word, p = 0; /* possition */
 109
 110         /* Because buf doesn't need to be aligned let's read it by chars */
 111         for (p = 0; p < bsize; p++) {
 112                 word = load_word(&buf[p], SWAP_NO);
 113                 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
 114
 115                 /* Find the first bitstream dummy word */
 116                 if (word == DUMMY_WORD) {
 117                         debug("%s: Found dummy word at position %x/%px\n",
 118                               __func__, p, &buf[p]);
 119                         *swap = check_header(&buf[p]);
 120                         if (*swap) {
 121                                 /* FIXME add full bitstream checking here */
 122                                 return &buf[p];
 123                         }
 124                 }
 125                 /* Loop can be huge - support CTRL + C */
 126                 if (ctrlc())
 127                         return NULL;
 128         }
 129         return NULL;
 130 }
 131
 132 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
 133 {
 134         u32 *new_buf;
 135         u32 i;
 136
 137         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
 138                 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
 139
 140                 /*
 141                  * This might be dangerous but permits to flash if
 142                  * ARCH_DMA_MINALIGN is greater than header size
 143                  */
 144                 if (new_buf > (u32 *)buf) {
 145                         debug("%s: Aligned buffer is after buffer start\n",
 146                               __func__);
 147                         new_buf -= ARCH_DMA_MINALIGN;
 148                 }
 149                 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
 150                        buf, new_buf, swap);
 151
 152                 for (i = 0; i < (len/4); i++)
 153                         new_buf[i] = load_word(&buf[i], swap);
 154
 155                 buf = new_buf;
 156         } else if ((swap != SWAP_DONE) &&
 157                    (zynqmp_firmware_version() <= PMUFW_V1_0)) {
 158                 /* For bitstream which are aligned */
 159                 new_buf = buf;
 160
 161                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 162                        swap);
 163
 164                 for (i = 0; i < (len/4); i++)
 165                         new_buf[i] = load_word(&buf[i], swap);
 166         }
 167
 168         return (ulong)buf;
 169 }
 170
 171 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
 172                                    size_t bsize, u32 blocksize, u32 *swap)
 173 {
 174         ulong *buf_start;
 175         ulong diff;
 176
 177         buf_start = check_data((u8 *)buf, blocksize, swap);
 178
 179         if (!buf_start)
 180                 return FPGA_FAIL;
 181
 182         /* Check if data is postpone from start */
 183         diff = (ulong)buf_start - (ulong)buf;
 184         if (diff) {
 185                 printf("%s: Bitstream is not validated yet (diff %lx)\n",
 186                        __func__, diff);
 187                 return FPGA_FAIL;
 188         }
 189
 190         if ((ulong)buf < SZ_1M) {
 191                 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
 192                        __func__, buf);
 193                 return FPGA_FAIL;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 200                      bitstream_type bstype)
 201 {
 202         ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
 203         u32 swap = 0;
 204         ulong bin_buf;
 205         int ret;
 206         u32 buf_lo, buf_hi;
 207         u32 ret_payload[PAYLOAD_ARG_CNT];
 208         bool xilfpga_old = false;
 209
 210         if (zynqmp_firmware_version() <= PMUFW_V1_0) {
 211                 puts("WARN: PMUFW v1.0 or less is detected\n");
 212                 puts("WARN: Not all bitstream formats are supported\n");
 213                 puts("WARN: Please upgrade PMUFW\n");
 214                 xilfpga_old = true;
 215                 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
 216                         return FPGA_FAIL;
 217                 bsizeptr = (u32 *)&bsize;
 218                 flush_dcache_range((ulong)bsizeptr,
 219                                    (ulong)bsizeptr + sizeof(size_t));
 220                 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
 221         }
 222
 223         bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
 224
 225         debug("%s called!\n", __func__);
 226         flush_dcache_range(bin_buf, bin_buf + bsize);
 227
 228         buf_lo = (u32)bin_buf;
 229         buf_hi = upper_32_bits(bin_buf);
 230
 231         if (xilfpga_old)
 232                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 233                                         buf_hi, (u32)(uintptr_t)bsizeptr,
 234                                         bstype, ret_payload);
 235         else
 236                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 237                                         buf_hi, (u32)bsize, 0, ret_payload);
 238
 239         if (ret)
 240                 puts("PL FPGA LOAD fail\n");
 241
 242         return ret;
 243 }
 244
 245 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
 246 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
 247                         struct fpga_secure_info *fpga_sec_info)
 248 {
 249         int ret;
 250         u32 buf_lo, buf_hi;
 251         u32 ret_payload[PAYLOAD_ARG_CNT];
 252         u8 flag = 0;
 253
 254         flush_dcache_range((ulong)buf, (ulong)buf +
 255                            ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
 256
 257         if (!fpga_sec_info->encflag)
 258                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
 259
 260         if (fpga_sec_info->userkey_addr &&
 261             fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
 262                 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
 263                                    (ulong)fpga_sec_info->userkey_addr +
 264                                    ALIGN(KEY_PTR_LEN,
 265                                          CONFIG_SYS_CACHELINE_SIZE));
 266                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
 267         }
 268
 269         if (!fpga_sec_info->authflag)
 270                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
 271
 272         if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
 273                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
 274
 275         buf_lo = lower_32_bits((ulong)buf);
 276         buf_hi = upper_32_bits((ulong)buf);
 277
 278         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 279                                 buf_hi,
 280                          (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 281                          flag, ret_payload);
 282         if (ret)
 283                 puts("PL FPGA LOAD fail\n");
 284         else
 285                 puts("Bitstream successfully loaded\n");
 286
 287         return ret;
 288 }
 289 #endif
 290
 291 static int zynqmp_pcap_info(xilinx_desc *desc)
 292 {
 293         int ret;
 294         u32 ret_payload[PAYLOAD_ARG_CNT];
 295
 296         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
 297                                 0, ret_payload);
 298         if (!ret)
 299                 printf("PCAP status\t0x%x\n", ret_payload[1]);
 300
 301         return ret;
 302 }
 303
 304 struct xilinx_fpga_op zynqmp_op = {
 305         .load = zynqmp_load,
 306 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
 307         .loads = zynqmp_loads,
 308 #endif
 309         .info = zynqmp_pcap_info,
 310 };