drivers/fpga/zynqmppl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 - 2016, Xilinx, Inc,
   4  * Michal Simek <michal.simek@xilinx.com>
   5  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
   6  */
   7
   8 #include <console.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <zynqmppl.h>
  13 #include <zynqmp_firmware.h>
  14 #include <asm/cache.h>
  15 #include <linux/bitops.h>
  16 #include <linux/sizes.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <memalign.h>
  19
  20 #define DUMMY_WORD      0xffffffff
  21
  22 /* Xilinx binary format header */
  23 static const u32 bin_format[] = {
  24         DUMMY_WORD, /* Dummy words */
  25         DUMMY_WORD,
  26         DUMMY_WORD,
  27         DUMMY_WORD,
  28         DUMMY_WORD,
  29         DUMMY_WORD,
  30         DUMMY_WORD,
  31         DUMMY_WORD,
  32         DUMMY_WORD,
  33         DUMMY_WORD,
  34         DUMMY_WORD,
  35         DUMMY_WORD,
  36         DUMMY_WORD,
  37         DUMMY_WORD,
  38         DUMMY_WORD,
  39         DUMMY_WORD,
  40         0x000000bb, /* Sync word */
  41         0x11220044, /* Sync word */
  42         DUMMY_WORD,
  43         DUMMY_WORD,
  44         0xaa995566, /* Sync word */
  45 };
  46
  47 #define SWAP_NO         1
  48 #define SWAP_DONE       2
  49
  50 /*
  51  * Load the whole word from unaligned buffer
  52  * Keep in your mind that it is byte loading on little-endian system
  53  */
  54 static u32 load_word(const void *buf, u32 swap)
  55 {
  56         u32 word = 0;
  57         u8 *bitc = (u8 *)buf;
  58         int p;
  59
  60         if (swap == SWAP_NO) {
  61                 for (p = 0; p < 4; p++) {
  62                         word <<= 8;
  63                         word |= bitc[p];
  64                 }
  65         } else {
  66                 for (p = 3; p >= 0; p--) {
  67                         word <<= 8;
  68                         word |= bitc[p];
  69                 }
  70         }
  71
  72         return word;
  73 }
  74
  75 static u32 check_header(const void *buf)
  76 {
  77         u32 i, pattern;
  78         int swap = SWAP_NO;
  79         u32 *test = (u32 *)buf;
  80
  81         debug("%s: Let's check bitstream header\n", __func__);
  82
  83         /* Checking that passing bin is not a bitstream */
  84         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  85                 pattern = load_word(&test[i], swap);
  86
  87                 /*
  88                  * Bitstreams in binary format are swapped
  89                  * compare to regular bistream.
  90                  * Do not swap dummy word but if swap is done assume
  91                  * that parsing buffer is binary format
  92                  */
  93                 if ((__swab32(pattern) != DUMMY_WORD) &&
  94                     (__swab32(pattern) == bin_format[i])) {
  95                         swap = SWAP_DONE;
  96                         debug("%s: data swapped - let's swap\n", __func__);
  97                 }
  98
  99                 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
 100                       &test[i], pattern, bin_format[i]);
 101         }
 102         debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
 103               buf, swap == SWAP_NO ? "without" : "with");
 104
 105         return swap;
 106 }
 107
 108 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 109 {
 110         u32 word, p = 0; /* possition */
 111
 112         /* Because buf doesn't need to be aligned let's read it by chars */
 113         for (p = 0; p < bsize; p++) {
 114                 word = load_word(&buf[p], SWAP_NO);
 115                 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
 116
 117                 /* Find the first bitstream dummy word */
 118                 if (word == DUMMY_WORD) {
 119                         debug("%s: Found dummy word at position %x/%px\n",
 120                               __func__, p, &buf[p]);
 121                         *swap = check_header(&buf[p]);
 122                         if (*swap) {
 123                                 /* FIXME add full bitstream checking here */
 124                                 return &buf[p];
 125                         }
 126                 }
 127                 /* Loop can be huge - support CTRL + C */
 128                 if (ctrlc())
 129                         return NULL;
 130         }
 131         return NULL;
 132 }
 133
 134 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
 135 {
 136         u32 *new_buf;
 137         u32 i;
 138
 139         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
 140                 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
 141
 142                 /*
 143                  * This might be dangerous but permits to flash if
 144                  * ARCH_DMA_MINALIGN is greater than header size
 145                  */
 146                 if (new_buf > (u32 *)buf) {
 147                         debug("%s: Aligned buffer is after buffer start\n",
 148                               __func__);
 149                         new_buf -= ARCH_DMA_MINALIGN;
 150                 }
 151                 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
 152                        buf, new_buf, swap);
 153
 154                 for (i = 0; i < (len/4); i++)
 155                         new_buf[i] = load_word(&buf[i], swap);
 156
 157                 buf = new_buf;
 158         } else if ((swap != SWAP_DONE) &&
 159                    (zynqmp_firmware_version() <= PMUFW_V1_0)) {
 160                 /* For bitstream which are aligned */
 161                 new_buf = buf;
 162
 163                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 164                        swap);
 165
 166                 for (i = 0; i < (len/4); i++)
 167                         new_buf[i] = load_word(&buf[i], swap);
 168         }
 169
 170         return (ulong)buf;
 171 }
 172
 173 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
 174                                    size_t bsize, u32 blocksize, u32 *swap)
 175 {
 176         ulong *buf_start;
 177         ulong diff;
 178
 179         buf_start = check_data((u8 *)buf, blocksize, swap);
 180
 181         if (!buf_start)
 182                 return FPGA_FAIL;
 183
 184         /* Check if data is postpone from start */
 185         diff = (ulong)buf_start - (ulong)buf;
 186         if (diff) {
 187                 printf("%s: Bitstream is not validated yet (diff %lx)\n",
 188                        __func__, diff);
 189                 return FPGA_FAIL;
 190         }
 191
 192         if ((ulong)buf < SZ_1M) {
 193                 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
 194                        __func__, buf);
 195                 return FPGA_FAIL;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 202                      bitstream_type bstype)
 203 {
 204         ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
 205         u32 swap = 0;
 206         ulong bin_buf;
 207         int ret;
 208         u32 buf_lo, buf_hi;
 209         u32 ret_payload[PAYLOAD_ARG_CNT];
 210         bool xilfpga_old = false;
 211
 212         if (zynqmp_firmware_version() <= PMUFW_V1_0) {
 213                 puts("WARN: PMUFW v1.0 or less is detected\n");
 214                 puts("WARN: Not all bitstream formats are supported\n");
 215                 puts("WARN: Please upgrade PMUFW\n");
 216                 xilfpga_old = true;
 217                 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
 218                         return FPGA_FAIL;
 219                 bsizeptr = (u32 *)&bsize;
 220                 flush_dcache_range((ulong)bsizeptr,
 221                                    (ulong)bsizeptr + sizeof(size_t));
 222                 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
 223         }
 224
 225         bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
 226
 227         debug("%s called!\n", __func__);
 228         flush_dcache_range(bin_buf, bin_buf + bsize);
 229
 230         buf_lo = (u32)bin_buf;
 231         buf_hi = upper_32_bits(bin_buf);
 232
 233         if (xilfpga_old)
 234                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 235                                         buf_hi, (u32)(uintptr_t)bsizeptr,
 236                                         bstype, ret_payload);
 237         else
 238                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 239                                         buf_hi, (u32)bsize, 0, ret_payload);
 240
 241         if (ret)
 242                 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
 243
 244         return ret;
 245 }
 246
 247 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
 248 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
 249                         struct fpga_secure_info *fpga_sec_info)
 250 {
 251         int ret;
 252         u32 buf_lo, buf_hi;
 253         u32 ret_payload[PAYLOAD_ARG_CNT];
 254         u8 flag = 0;
 255
 256         flush_dcache_range((ulong)buf, (ulong)buf +
 257                            ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
 258
 259         if (!fpga_sec_info->encflag)
 260                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
 261
 262         if (fpga_sec_info->userkey_addr &&
 263             fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
 264                 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
 265                                    (ulong)fpga_sec_info->userkey_addr +
 266                                    ALIGN(KEY_PTR_LEN,
 267                                          CONFIG_SYS_CACHELINE_SIZE));
 268                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
 269         }
 270
 271         if (!fpga_sec_info->authflag)
 272                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
 273
 274         if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
 275                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
 276
 277         buf_lo = lower_32_bits((ulong)buf);
 278         buf_hi = upper_32_bits((ulong)buf);
 279
 280         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 281                                 buf_hi,
 282                          (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 283                          flag, ret_payload);
 284         if (ret)
 285                 puts("PL FPGA LOAD fail\n");
 286         else
 287                 puts("Bitstream successfully loaded\n");
 288
 289         return ret;
 290 }
 291 #endif
 292
 293 static int zynqmp_pcap_info(xilinx_desc *desc)
 294 {
 295         int ret;
 296         u32 ret_payload[PAYLOAD_ARG_CNT];
 297
 298         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
 299                                 0, ret_payload);
 300         if (!ret)
 301                 printf("PCAP status\t0x%x\n", ret_payload[1]);
 302
 303         return ret;
 304 }
 305
 306 struct xilinx_fpga_op zynqmp_op = {
 307         .load = zynqmp_load,
 308 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
 309         .loads = zynqmp_loads,
 310 #endif
 311         .info = zynqmp_pcap_info,
 312 };