1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017, National Instruments Corp.
4 * Copyright (c) 2017, Xilinx Inc
6 * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
10 #include <linux/clk.h>
12 #include <linux/kernel.h>
13 #include <linux/of_device.h>
14 #include <linux/module.h>
15 #include <linux/fpga/fpga-bridge.h>
17 #define CTRL_CMD_DECOUPLE BIT(0)
18 #define CTRL_CMD_COUPLE 0
21 struct xlnx_config_data {
25 struct xlnx_pr_decoupler_data {
26 const struct xlnx_config_data *ipconfig;
27 void __iomem *io_base;
31 static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
34 writel(val, d->io_base + offset);
37 static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
40 return readl(d->io_base + offset);
43 static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
46 struct xlnx_pr_decoupler_data *priv = bridge->priv;
48 err = clk_enable(priv->clk);
53 xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
55 xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
57 clk_disable(priv->clk);
62 static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
64 const struct xlnx_pr_decoupler_data *priv = bridge->priv;
68 err = clk_enable(priv->clk);
72 status = readl(priv->io_base);
74 clk_disable(priv->clk);
79 static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
80 .enable_set = xlnx_pr_decoupler_enable_set,
81 .enable_show = xlnx_pr_decoupler_enable_show,
85 static const struct xlnx_config_data decoupler_config = {
86 .name = "Xilinx PR Decoupler",
89 static const struct xlnx_config_data shutdown_config = {
90 .name = "Xilinx DFX AXI Shutdown Manager",
93 static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
94 { .compatible = "xlnx,pr-decoupler-1.00", .data = &decoupler_config },
95 { .compatible = "xlnx,pr-decoupler", .data = &decoupler_config },
96 { .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
97 .data = &shutdown_config },
98 { .compatible = "xlnx,dfx-axi-shutdown-manager",
99 .data = &shutdown_config },
102 MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
105 static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
107 struct device_node *np = pdev->dev.of_node;
108 struct xlnx_pr_decoupler_data *priv;
109 struct fpga_bridge *br;
111 struct resource *res;
113 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
118 const struct of_device_id *match;
120 match = of_match_node(xlnx_pr_decoupler_of_match, np);
121 if (match && match->data)
122 priv->ipconfig = match->data;
125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
126 priv->io_base = devm_ioremap_resource(&pdev->dev, res);
127 if (IS_ERR(priv->io_base))
128 return PTR_ERR(priv->io_base);
130 priv->clk = devm_clk_get(&pdev->dev, "aclk");
131 if (IS_ERR(priv->clk))
132 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
133 "input clock not found\n");
135 err = clk_prepare_enable(priv->clk);
137 dev_err(&pdev->dev, "unable to enable clock\n");
141 clk_disable(priv->clk);
143 br = fpga_bridge_register(&pdev->dev, priv->ipconfig->name,
144 &xlnx_pr_decoupler_br_ops, priv);
147 dev_err(&pdev->dev, "unable to register %s",
148 priv->ipconfig->name);
152 platform_set_drvdata(pdev, br);
157 clk_unprepare(priv->clk);
162 static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
164 struct fpga_bridge *bridge = platform_get_drvdata(pdev);
165 struct xlnx_pr_decoupler_data *p = bridge->priv;
167 fpga_bridge_unregister(bridge);
169 clk_unprepare(p->clk);
174 static struct platform_driver xlnx_pr_decoupler_driver = {
175 .probe = xlnx_pr_decoupler_probe,
176 .remove = xlnx_pr_decoupler_remove,
178 .name = "xlnx_pr_decoupler",
179 .of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
183 module_platform_driver(xlnx_pr_decoupler_driver);
185 MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
186 MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
187 MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
188 MODULE_LICENSE("GPL v2");