1 // SPDX-License-Identifier: GPL-2.0+
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * Keith Outwater, keith_outwater@mvis.com
7 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
11 * Configuration support for Xilinx Virtex2 devices. Based
12 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
15 #define LOG_CATEGORY UCLASS_FPGA
21 #include <linux/delay.h>
24 * If the SelectMap interface can be overrun by the processor, enable
25 * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
26 * configuration file and add board-specific support for checking BUSY status.
27 * By default, assume that the SelectMap interface cannot be overrun.
30 #ifndef CFG_FPGA_DELAY
31 #define CFG_FPGA_DELAY()
35 * Check for errors during configuration by default
37 #ifndef CFG_SYS_FPGA_CHECK_ERROR
38 #define CFG_SYS_FPGA_CHECK_ERROR
42 * The default timeout in mS for INIT_B to deassert after PROG_B has
43 * been deasserted. Per the latest Virtex II Handbook (page 347), the
44 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
45 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
46 * which yields 11.44 mS. So let's make it bigger in order to handle
47 * an XC2V1000, if anyone can ever get ahold of one.
49 #ifndef CFG_SYS_FPGA_WAIT_INIT
50 #define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
54 * The default timeout for waiting for BUSY to deassert during configuration.
55 * This is normally not necessary since for most reasonable configuration
56 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
58 #ifndef CFG_SYS_FPGA_WAIT_BUSY
59 #define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
62 /* Default timeout for waiting for FPGA to enter operational mode after
63 * configuration data has been written.
65 #ifndef CFG_SYS_FPGA_WAIT_CONFIG
66 #define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
69 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
70 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
72 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
73 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
75 static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
76 bitstream_type bstype, int flags)
78 int ret_val = FPGA_FAIL;
80 switch (desc->iface) {
82 log_debug("Launching Slave Serial Load\n");
83 ret_val = virtex2_ss_load(desc, buf, bsize);
87 log_debug("Launching Slave Parallel Load\n");
88 ret_val = virtex2_ssm_load(desc, buf, bsize);
92 printf("%s: Unsupported interface type, %d\n",
93 __func__, desc->iface);
98 static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
100 int ret_val = FPGA_FAIL;
102 switch (desc->iface) {
104 log_debug("Launching Slave Serial Dump\n");
105 ret_val = virtex2_ss_dump(desc, buf, bsize);
109 log_debug("Launching Slave Parallel Dump\n");
110 ret_val = virtex2_ssm_dump(desc, buf, bsize);
114 printf("%s: Unsupported interface type, %d\n",
115 __func__, desc->iface);
120 static int virtex2_info(xilinx_desc *desc)
126 * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
128 * 1. Set the FPGA's PROG_B line low.
129 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
130 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
131 * this process, a configuration error (most likely CRC failure) has
132 * ocurred. At this point a status word may be read from the
133 * SelectMap interface to determine the source of the problem (You
134 * could, for instance, put this in your 'abort' function handler).
135 * 4. After all data has been written, test the state of the FPGA
136 * INIT_B and DONE lines. If both are high, configuration has
137 * succeeded. Congratulations!
139 static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
143 log_debug("Start with interface functions @ 0x%p\n", fn);
146 printf("%s:%d: NULL Interface function table!\n",
151 /* Gotta split this one up (so the stack won't blow??) */
152 log_debug("Function Table:\n"
159 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
160 log_debug(" clock 0x%p\n"
168 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
169 fn->busy, fn->abort, fn->post);
171 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
172 printf("Initializing FPGA Device %d...\n", cookie);
175 * Run the pre configuration function if there is one.
181 * Assert the program line. The minimum pulse width for
182 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
183 * There is no maximum value for the pulse width. Check to make
184 * sure that INIT_B goes low after assertion of PROG_B
186 (*fn->pgm)(true, true, cookie);
190 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
191 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
192 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
193 (*fn->abort)(cookie);
196 } while (!(*fn->init)(cookie));
198 (*fn->pgm)(false, true, cookie);
201 (*fn->clk)(true, true, cookie);
204 * Start a timer and wait for INIT_B to go high
209 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
210 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
211 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
212 (*fn->abort)(cookie);
215 } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
218 (*fn->wr)(true, true, cookie);
220 (*fn->cs)(true, true, cookie);
226 static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
229 int ret_val = FPGA_SUCCESS;
234 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
238 (*fn->cs)(false, true, cookie);
240 (*fn->wr)(false, true, cookie);
242 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
247 * Check for successful configuration. FPGA INIT_B and DONE
248 * should both be high upon successful configuration. Continue pulsing
249 * clock with data set to all ones until DONE is asserted and for 8
250 * clock cycles afterwards.
254 if ((*fn->done)(cookie) == FPGA_SUCCESS &&
255 !((*fn->init)(cookie))) {
260 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
261 printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
262 __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
263 (*fn->abort)(cookie);
268 unsigned char dummy = 0xff;
269 (*fn->wbulkdata)(&dummy, 1, true, cookie);
271 (*fn->wdata)(0xff, true, cookie);
273 (*fn->clk)(false, true, cookie);
275 (*fn->clk)(true, true, cookie);
279 if (ret_val == FPGA_SUCCESS) {
280 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
281 printf("Initialization of FPGA device %d complete\n", cookie);
284 * Run the post configuration function if there is one.
289 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
290 printf("** Initialization of FPGA device %d FAILED\n",
297 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
299 int ret_val = FPGA_FAIL;
300 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
301 size_t bytecount = 0;
302 unsigned char *data = (unsigned char *)buf;
303 int cookie = desc->cookie;
305 ret_val = virtex2_slave_pre(fn, cookie);
306 if (ret_val != FPGA_SUCCESS)
310 * Load the data byte by byte
312 while (bytecount < bsize) {
313 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
315 (*fn->abort)(cookie);
320 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
321 log_debug("done went active early, bytecount = %zu\n",
326 #ifdef CFG_SYS_FPGA_CHECK_ERROR
327 if ((*fn->init)(cookie)) {
328 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
330 printf("%zu = buffer offset, %zu = buffer size\n",
332 (*fn->abort)(cookie);
337 (*fn->wdata)(data[bytecount++], true, cookie);
341 * Cycle the clock pin
343 (*fn->clk)(false, true, cookie);
345 (*fn->clk)(true, true, cookie);
347 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
349 while ((*fn->busy)(cookie)) {
350 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
351 printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
353 CFG_SYS_FPGA_WAIT_BUSY);
354 (*fn->abort)(cookie);
360 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
361 if (bytecount % (bsize / 40) == 0)
366 return virtex2_slave_post(fn, cookie);
370 * Read the FPGA configuration data
372 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
374 int ret_val = FPGA_FAIL;
375 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
378 unsigned char *data = (unsigned char *)buf;
379 size_t bytecount = 0;
380 int cookie = desc->cookie;
382 printf("Starting Dump of FPGA Device %d...\n", cookie);
384 (*fn->cs)(true, true, cookie);
385 (*fn->clk)(true, true, cookie);
387 while (bytecount < bsize) {
388 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
390 (*fn->abort)(cookie);
395 * Cycle the clock and read the data
397 (*fn->clk)(false, true, cookie);
398 (*fn->clk)(true, true, cookie);
399 (*fn->rdata)(&data[bytecount++], cookie);
400 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
401 if (bytecount % (bsize / 40) == 0)
407 * Deassert CS_B and cycle the clock to deselect the device.
409 (*fn->cs)(false, false, cookie);
410 (*fn->clk)(false, true, cookie);
411 (*fn->clk)(true, true, cookie);
413 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
418 printf("%s:%d: NULL Interface function table!\n",
424 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
426 int ret_val = FPGA_FAIL;
427 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
428 unsigned char *data = (unsigned char *)buf;
429 int cookie = desc->cookie;
431 ret_val = virtex2_slave_pre(fn, cookie);
432 if (ret_val != FPGA_SUCCESS)
436 /* Load the data in a single chunk */
437 (*fn->wbulkdata)(data, bsize, true, cookie);
439 size_t bytecount = 0;
442 * Load the data bit by bit
444 while (bytecount < bsize) {
445 unsigned char curr_data = data[bytecount++];
448 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
450 (*fn->abort) (cookie);
455 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
456 log_debug("done went active early, bytecount = %zu\n",
461 #ifdef CFG_SYS_FPGA_CHECK_ERROR
462 if ((*fn->init)(cookie)) {
463 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
465 printf("%zu = buffer offset, %zu = buffer size\n",
467 (*fn->abort)(cookie);
472 for (bit = 7; bit >= 0; --bit) {
473 unsigned char curr_bit = (curr_data >> bit) & 1;
474 (*fn->wdata)(curr_bit, true, cookie);
476 (*fn->clk)(false, true, cookie);
478 (*fn->clk)(true, true, cookie);
481 /* Slave serial never uses a busy pin */
483 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
484 if (bytecount % (bsize / 40) == 0)
490 return virtex2_slave_post(fn, cookie);
493 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
495 printf("%s: Slave Serial Dumping is unsupported\n", __func__);
499 /* vim: set ts=4 tw=78: */
501 struct xilinx_fpga_op virtex2_op = {
502 .load = virtex2_load,
503 .dump = virtex2_dump,
504 .info = virtex2_info,