1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2019, Xilinx, Inc,
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
10 #include <asm/arch/sys_proto.h>
13 #include <zynqmp_firmware.h>
14 #include <asm/cache.h>
16 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
20 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
21 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
22 memcpy(new_buf, buf, len);
29 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
30 bitstream_type bstype, int flags)
35 u32 ret_payload[PAYLOAD_ARG_CNT];
37 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
39 debug("%s called!\n", __func__);
40 flush_dcache_range(bin_buf, bin_buf + bsize);
42 buf_lo = lower_32_bits(bin_buf);
43 buf_hi = upper_32_bits(bin_buf);
45 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
46 buf_hi, 0, ret_payload);
48 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
53 struct xilinx_fpga_op versal_op = {