drivers/fpga/versalpl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2019, Xilinx, Inc,
   4  * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <memalign.h>
  11 #include <versalpl.h>
  12 #include <zynqmp_firmware.h>
  13
  14 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
  15 {
  16         ulong *new_buf;
  17
  18         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  19                 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  20                 memcpy(new_buf, buf, len);
  21                 buf = new_buf;
  22         }
  23
  24         return (ulong)buf;
  25 }
  26
  27 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
  28                        bitstream_type bstype)
  29 {
  30         ulong bin_buf;
  31         int ret;
  32         u32 buf_lo, buf_hi;
  33         u32 ret_payload[5];
  34
  35         bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
  36
  37         debug("%s called!\n", __func__);
  38         flush_dcache_range(bin_buf, bin_buf + bsize);
  39
  40         buf_lo = lower_32_bits(bin_buf);
  41         buf_hi = upper_32_bits(bin_buf);
  42
  43         ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
  44                                 buf_hi, 0, ret_payload);
  45         if (ret)
  46                 puts("PL FPGA LOAD fail\n");
  47
  48         return ret;
  49 }
  50
  51 struct xilinx_fpga_op versal_op = {
  52         .load = versal_load,
  53 };