drivers/fpga/spartan2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002
   4  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   5  */
   6
   7 #define LOG_CATEGORY UCLASS_FPGA
   8
   9 #include <common.h>             /* core U-Boot definitions */
  10 #include <log.h>
  11 #include <spartan2.h>           /* Spartan-II device family */
  12
  13 #undef CONFIG_SYS_FPGA_CHECK_BUSY
  14
  15 /* Note: The assumption is that we cannot possibly run fast enough to
  16  * overrun the device (the Slave Parallel mode can free run at 50MHz).
  17  * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  18  * the board config file to slow things down.
  19  */
  20 #ifndef CONFIG_FPGA_DELAY
  21 #define CONFIG_FPGA_DELAY()
  22 #endif
  23
  24 #ifndef CONFIG_SYS_FPGA_WAIT
  25 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100  /* 10 ms */
  26 #endif
  27
  28 static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
  29 static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  30 /* static int spartan2_sp_info(xilinx_desc *desc ); */
  31
  32 static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
  33 static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
  34 /* static int spartan2_ss_info(xilinx_desc *desc ); */
  35
  36 /* ------------------------------------------------------------------------- */
  37 /* Spartan-II Generic Implementation */
  38 static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize,
  39                          bitstream_type bstype, int flags)
  40 {
  41         int ret_val = FPGA_FAIL;
  42
  43         switch (desc->iface) {
  44         case slave_serial:
  45                 log_debug("Launching Slave Serial Load\n");
  46                 ret_val = spartan2_ss_load(desc, buf, bsize);
  47                 break;
  48
  49         case slave_parallel:
  50                 log_debug("Launching Slave Parallel Load\n");
  51                 ret_val = spartan2_sp_load(desc, buf, bsize);
  52                 break;
  53
  54         default:
  55                 printf ("%s: Unsupported interface type, %d\n",
  56                                 __FUNCTION__, desc->iface);
  57         }
  58
  59         return ret_val;
  60 }
  61
  62 static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  63 {
  64         int ret_val = FPGA_FAIL;
  65
  66         switch (desc->iface) {
  67         case slave_serial:
  68                 log_debug("Launching Slave Serial Dump\n");
  69                 ret_val = spartan2_ss_dump(desc, buf, bsize);
  70                 break;
  71
  72         case slave_parallel:
  73                 log_debug("Launching Slave Parallel Dump\n");
  74                 ret_val = spartan2_sp_dump(desc, buf, bsize);
  75                 break;
  76
  77         default:
  78                 printf ("%s: Unsupported interface type, %d\n",
  79                                 __FUNCTION__, desc->iface);
  80         }
  81
  82         return ret_val;
  83 }
  84
  85 static int spartan2_info(xilinx_desc *desc)
  86 {
  87         return FPGA_SUCCESS;
  88 }
  89
  90
  91 /* ------------------------------------------------------------------------- */
  92 /* Spartan-II Slave Parallel Generic Implementation */
  93
  94 static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
  95 {
  96         int ret_val = FPGA_FAIL;        /* assume the worst */
  97         xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
  98
  99         log_debug("start with interface functions @ 0x%p\n", fn);
 100
 101         if (fn) {
 102                 size_t bytecount = 0;
 103                 unsigned char *data = (unsigned char *) buf;
 104                 int cookie = desc->cookie;      /* make a local copy */
 105                 unsigned long ts;               /* timestamp */
 106
 107                 log_debug("Function Table:\n"
 108                           "ptr:\t0x%p\n"
 109                           "struct: 0x%p\n"
 110                           "pre: 0x%p\n"
 111                           "pgm:\t0x%p\n"
 112                           "init:\t0x%p\n"
 113                           "err:\t0x%p\n"
 114                           "clk:\t0x%p\n"
 115                           "cs:\t0x%p\n"
 116                           "wr:\t0x%p\n"
 117                           "read data:\t0x%p\n"
 118                           "write data:\t0x%p\n"
 119                           "busy:\t0x%p\n"
 120                           "abort:\t0x%p\n"
 121                           "post:\t0x%p\n\n",
 122                           &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
 123                           fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
 124                           fn->abort, fn->post);
 125
 126                 /*
 127                  * This code is designed to emulate the "Express Style"
 128                  * Continuous Data Loading in Slave Parallel Mode for
 129                  * the Spartan-II Family.
 130                  */
 131 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 132                 printf ("Loading FPGA Device %d...\n", cookie);
 133 #endif
 134                 /*
 135                  * Run the pre configuration function if there is one.
 136                  */
 137                 if (*fn->pre) {
 138                         (*fn->pre) (cookie);
 139                 }
 140
 141                 /* Establish the initial state */
 142                 (*fn->pgm) (true, true, cookie);        /* Assert the program, commit */
 143
 144                 /* Get ready for the burn */
 145                 CONFIG_FPGA_DELAY ();
 146                 (*fn->pgm) (false, true, cookie);       /* Deassert the program, commit */
 147
 148                 ts = get_timer (0);             /* get current time */
 149                 /* Now wait for INIT and BUSY to go high */
 150                 do {
 151                         CONFIG_FPGA_DELAY ();
 152                         if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 153                                 puts ("** Timeout waiting for INIT to clear.\n");
 154                                 (*fn->abort) (cookie);  /* abort the burn */
 155                                 return FPGA_FAIL;
 156                         }
 157                 } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 158
 159                 (*fn->wr) (true, true, cookie); /* Assert write, commit */
 160                 (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
 161                 (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 162
 163                 /* Load the data */
 164                 while (bytecount < bsize) {
 165                         /* XXX - do we check for an Ctrl-C press in here ??? */
 166                         /* XXX - Check the error bit? */
 167
 168                         (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
 169                         CONFIG_FPGA_DELAY ();
 170                         (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 171                         CONFIG_FPGA_DELAY ();
 172                         (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 173
 174 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
 175                         ts = get_timer (0);     /* get current time */
 176                         while ((*fn->busy) (cookie)) {
 177                                 /* XXX - we should have a check in here somewhere to
 178                                  * make sure we aren't busy forever... */
 179
 180                                 CONFIG_FPGA_DELAY ();
 181                                 (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 182                                 CONFIG_FPGA_DELAY ();
 183                                 (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 184
 185                                 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 186                                         puts ("** Timeout waiting for BUSY to clear.\n");
 187                                         (*fn->abort) (cookie);  /* abort the burn */
 188                                         return FPGA_FAIL;
 189                                 }
 190                         }
 191 #endif
 192
 193 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 194                         if (bytecount % (bsize / 40) == 0)
 195                                 putc ('.');             /* let them know we are alive */
 196 #endif
 197                 }
 198
 199                 CONFIG_FPGA_DELAY ();
 200                 (*fn->cs) (false, true, cookie);        /* Deassert the chip select */
 201                 (*fn->wr) (false, true, cookie);        /* Deassert the write pin */
 202
 203 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 204                 putc ('\n');                    /* terminate the dotted line */
 205 #endif
 206
 207                 /* now check for done signal */
 208                 ts = get_timer (0);             /* get current time */
 209                 ret_val = FPGA_SUCCESS;
 210                 while ((*fn->done) (cookie) == FPGA_FAIL) {
 211
 212                         CONFIG_FPGA_DELAY ();
 213                         (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 214                         CONFIG_FPGA_DELAY ();
 215                         (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 216
 217                         if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 218                                 puts ("** Timeout waiting for DONE to clear.\n");
 219                                 (*fn->abort) (cookie);  /* abort the burn */
 220                                 ret_val = FPGA_FAIL;
 221                                 break;
 222                         }
 223                 }
 224
 225                 /*
 226                  * Run the post configuration function if there is one.
 227                  */
 228                 if (*fn->post)
 229                         (*fn->post) (cookie);
 230
 231 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 232                 if (ret_val == FPGA_SUCCESS)
 233                         puts ("Done.\n");
 234                 else
 235                         puts ("Fail.\n");
 236 #endif
 237
 238         } else {
 239                 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 240         }
 241
 242         return ret_val;
 243 }
 244
 245 static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 246 {
 247         int ret_val = FPGA_FAIL;        /* assume the worst */
 248         xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
 249
 250         if (fn) {
 251                 unsigned char *data = (unsigned char *) buf;
 252                 size_t bytecount = 0;
 253                 int cookie = desc->cookie;      /* make a local copy */
 254
 255                 printf ("Starting Dump of FPGA Device %d...\n", cookie);
 256
 257                 (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
 258                 (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 259
 260                 /* dump the data */
 261                 while (bytecount < bsize) {
 262                         /* XXX - do we check for an Ctrl-C press in here ??? */
 263
 264                         (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 265                         (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 266                         (*fn->rdata) (&(data[bytecount++]), cookie);    /* read the data */
 267 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 268                         if (bytecount % (bsize / 40) == 0)
 269                                 putc ('.');             /* let them know we are alive */
 270 #endif
 271                 }
 272
 273                 (*fn->cs) (false, false, cookie);       /* Deassert the chip select */
 274                 (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 275                 (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 276
 277 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 278                 putc ('\n');                    /* terminate the dotted line */
 279 #endif
 280                 puts ("Done.\n");
 281
 282                 /* XXX - checksum the data? */
 283         } else {
 284                 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 285         }
 286
 287         return ret_val;
 288 }
 289
 290
 291 /* ------------------------------------------------------------------------- */
 292
 293 static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 294 {
 295         int ret_val = FPGA_FAIL;        /* assume the worst */
 296         xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
 297         int i;
 298         unsigned char val;
 299
 300         log_debug("start with interface functions @ 0x%p\n", fn);
 301
 302         if (fn) {
 303                 size_t bytecount = 0;
 304                 unsigned char *data = (unsigned char *) buf;
 305                 int cookie = desc->cookie;      /* make a local copy */
 306                 unsigned long ts;               /* timestamp */
 307
 308                 log_debug("Function Table:\n"
 309                           "ptr:\t0x%p\n"
 310                           "struct: 0x%p\n"
 311                           "pgm:\t0x%p\n"
 312                           "init:\t0x%p\n"
 313                           "clk:\t0x%p\n"
 314                           "wr:\t0x%p\n"
 315                           "done:\t0x%p\n\n",
 316                           &fn, fn, fn->pgm, fn->init,
 317                           fn->clk, fn->wr, fn->done);
 318 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 319                 printf ("Loading FPGA Device %d...\n", cookie);
 320 #endif
 321
 322                 /*
 323                  * Run the pre configuration function if there is one.
 324                  */
 325                 if (*fn->pre) {
 326                         (*fn->pre) (cookie);
 327                 }
 328
 329                 /* Establish the initial state */
 330                 (*fn->pgm) (true, true, cookie);        /* Assert the program, commit */
 331
 332                 /* Wait for INIT state (init low)                            */
 333                 ts = get_timer (0);             /* get current time */
 334                 do {
 335                         CONFIG_FPGA_DELAY ();
 336                         if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 337                                 puts ("** Timeout waiting for INIT to start.\n");
 338                                 return FPGA_FAIL;
 339                         }
 340                 } while (!(*fn->init) (cookie));
 341
 342                 /* Get ready for the burn */
 343                 CONFIG_FPGA_DELAY ();
 344                 (*fn->pgm) (false, true, cookie);       /* Deassert the program, commit */
 345
 346                 ts = get_timer (0);             /* get current time */
 347                 /* Now wait for INIT to go high */
 348                 do {
 349                         CONFIG_FPGA_DELAY ();
 350                         if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 351                                 puts ("** Timeout waiting for INIT to clear.\n");
 352                                 return FPGA_FAIL;
 353                         }
 354                 } while ((*fn->init) (cookie));
 355
 356                 /* Load the data */
 357                 while (bytecount < bsize) {
 358
 359                         /* Xilinx detects an error if INIT goes low (active)
 360                            while DONE is low (inactive) */
 361                         if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
 362                                 puts ("** CRC error during FPGA load.\n");
 363                                 return (FPGA_FAIL);
 364                         }
 365                         val = data [bytecount ++];
 366                         i = 8;
 367                         do {
 368                                 /* Deassert the clock */
 369                                 (*fn->clk) (false, true, cookie);
 370                                 CONFIG_FPGA_DELAY ();
 371                                 /* Write data */
 372                                 (*fn->wr) ((val & 0x80), true, cookie);
 373                                 CONFIG_FPGA_DELAY ();
 374                                 /* Assert the clock */
 375                                 (*fn->clk) (true, true, cookie);
 376                                 CONFIG_FPGA_DELAY ();
 377                                 val <<= 1;
 378                                 i --;
 379                         } while (i > 0);
 380
 381 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 382                         if (bytecount % (bsize / 40) == 0)
 383                                 putc ('.');             /* let them know we are alive */
 384 #endif
 385                 }
 386
 387                 CONFIG_FPGA_DELAY ();
 388
 389 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 390                 putc ('\n');                    /* terminate the dotted line */
 391 #endif
 392
 393                 /* now check for done signal */
 394                 ts = get_timer (0);             /* get current time */
 395                 ret_val = FPGA_SUCCESS;
 396                 (*fn->wr) (true, true, cookie);
 397
 398                 while (! (*fn->done) (cookie)) {
 399
 400                         CONFIG_FPGA_DELAY ();
 401                         (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
 402                         CONFIG_FPGA_DELAY ();
 403                         (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
 404
 405                         putc ('*');
 406
 407                         if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
 408                                 puts ("** Timeout waiting for DONE to clear.\n");
 409                                 ret_val = FPGA_FAIL;
 410                                 break;
 411                         }
 412                 }
 413                 putc ('\n');                    /* terminate the dotted line */
 414
 415                 /*
 416                  * Run the post configuration function if there is one.
 417                  */
 418                 if (*fn->post)
 419                         (*fn->post) (cookie);
 420
 421 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 422                 if (ret_val == FPGA_SUCCESS)
 423                         puts ("Done.\n");
 424                 else
 425                         puts ("Fail.\n");
 426 #endif
 427
 428         } else {
 429                 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
 430         }
 431
 432         return ret_val;
 433 }
 434
 435 static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 436 {
 437         /* Readback is only available through the Slave Parallel and         */
 438         /* boundary-scan interfaces.                                         */
 439         printf ("%s: Slave Serial Dumping is unavailable\n",
 440                         __FUNCTION__);
 441         return FPGA_FAIL;
 442 }
 443
 444 struct xilinx_fpga_op spartan2_op = {
 445         .load = spartan2_load,
 446         .dump = spartan2_dump,
 447         .info = spartan2_info,
 448 };