drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <log.h>
   7 #include <asm/global_data.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/reset_manager.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/arch/sdram.h>
  13 #include <asm/arch/misc.h>
  14 #include <altera.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <dm.h>
  17 #include <dm/ofnode.h>
  18 #include <errno.h>
  19 #include <fs_loader.h>
  20 #include <wait_bit.h>
  21 #include <watchdog.h>
  22 #include <linux/bitops.h>
  23 #include <linux/delay.h>
  24
  25 #define CFGWDTH_32      1
  26 #define MIN_BITSTREAM_SIZECHECK 230
  27 #define ENCRYPTION_OFFSET       69
  28 #define COMPRESSION_OFFSET      229
  29 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  30 #define FPGA_TIMEOUT_CNT        0x1000000
  31 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  32 #define DDR_BUFFER_SIZE         0x100000
  33
  34 /* When reading bitstream from a filesystem, the size of the first read is
  35  * changed so that the subsequent reads are aligned to this value. This value
  36  * was chosen so that in subsequent reads the fat fs driver doesn't have to
  37  * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
  38  */
  39 #define MAX_FIRST_LOAD_SIZE     0x2000
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static const struct socfpga_fpga_manager *fpga_manager_base =
  44                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  45
  46 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  47
  48 static uint32_t fpgamgr_get_msel(void)
  49 {
  50         u32 reg;
  51
  52         reg = readl(&fpga_manager_base->imgcfg_stat);
  53         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  54                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  55
  56         return reg;
  57 }
  58
  59 static void fpgamgr_set_cfgwdth(int width)
  60 {
  61         if (width)
  62                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  63                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  64         else
  65                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  66                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  67 }
  68
  69 int is_fpgamgr_user_mode(void)
  70 {
  71         return (readl(&fpga_manager_base->imgcfg_stat) &
  72                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  73 }
  74
  75 static int wait_for_user_mode(void)
  76 {
  77         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  78                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  79                 1, FPGA_TIMEOUT_MSEC, false);
  80 }
  81
  82 static int wait_for_fifo_empty(void)
  83 {
  84         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  85                 ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
  86                 1, FPGA_TIMEOUT_MSEC, false);
  87 }
  88
  89 int is_fpgamgr_early_user_mode(void)
  90 {
  91         return (readl(&fpga_manager_base->imgcfg_stat) &
  92                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  93 }
  94
  95 int fpgamgr_wait_early_user_mode(void)
  96 {
  97         u32 sync_data = 0xffffffff;
  98         u32 i = 0;
  99         unsigned start = get_timer(0);
 100         unsigned long cd_ratio;
 101
 102         /* Getting existing CDRATIO */
 103         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
 104                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
 105                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
 106
 107         /* Using CDRATIO_X1 for better compatibility */
 108         fpgamgr_set_cd_ratio(CDRATIO_x1);
 109
 110         while (!is_fpgamgr_early_user_mode()) {
 111                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
 112                         return -ETIMEDOUT;
 113                 fpgamgr_program_write((const long unsigned int *)&sync_data,
 114                                 sizeof(sync_data));
 115                 udelay(FPGA_TIMEOUT_MSEC);
 116                 i++;
 117         }
 118
 119         debug("FPGA: Additional %i sync word needed\n", i);
 120
 121         /* restoring original CDRATIO */
 122         fpgamgr_set_cd_ratio(cd_ratio);
 123
 124         return 0;
 125 }
 126
 127 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 128 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 129 {
 130         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 131                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 132
 133         /*
 134          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 135          * de-asserted, timeout at 1000ms
 136          */
 137         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 138                                  true, FPGA_TIMEOUT_MSEC, false);
 139 }
 140
 141 static int wait_for_f2s_nstatus_pin(unsigned long value)
 142 {
 143         /* Poll until f2s to specific value, timeout at 1000ms */
 144         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 145                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 146                 value, FPGA_TIMEOUT_MSEC, false);
 147 }
 148
 149 /* set CD ratio */
 150 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 151 {
 152         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 153                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 154
 155         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 156                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 157                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 158 }
 159
 160 /* get the MSEL value, verify we are set for FPP configuration mode */
 161 static int fpgamgr_verify_msel(void)
 162 {
 163         u32 msel = fpgamgr_get_msel();
 164
 165         if (msel & ~BIT(0)) {
 166                 printf("Fail: read msel=%d\n", msel);
 167                 return -EPERM;
 168         }
 169
 170         return 0;
 171 }
 172
 173 /*
 174  * Write cdratio and cdwidth based on whether the bitstream is compressed
 175  * and/or encoded
 176  */
 177 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 178                                        size_t rbf_size)
 179 {
 180         unsigned int cd_ratio;
 181         bool encrypt, compress;
 182
 183         /*
 184          * According to the bitstream specification,
 185          * both encryption and compression status are
 186          * in location before offset 230 of the buffer.
 187          */
 188         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 189                 return -EINVAL;
 190
 191         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 192         encrypt = encrypt != 0;
 193
 194         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 195         compress = !compress;
 196
 197         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 198         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 199         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 200              compress);
 201
 202         /*
 203          * from the register map description of cdratio in imgcfg_ctrl_02:
 204          *  Normal Configuration    : 32bit Passive Parallel
 205          *  Partial Reconfiguration : 16bit Passive Parallel
 206          */
 207
 208         /*
 209          * cd ratio is dependent on cfg width and whether the bitstream
 210          * is encrypted and/or compressed.
 211          *
 212          * | width | encr. | compr. | cd ratio |
 213          * |  16   |   0   |   0    |     1    |
 214          * |  16   |   0   |   1    |     4    |
 215          * |  16   |   1   |   0    |     2    |
 216          * |  16   |   1   |   1    |     4    |
 217          * |  32   |   0   |   0    |     1    |
 218          * |  32   |   0   |   1    |     8    |
 219          * |  32   |   1   |   0    |     4    |
 220          * |  32   |   1   |   1    |     8    |
 221          */
 222         if (!compress && !encrypt) {
 223                 cd_ratio = CDRATIO_x1;
 224         } else {
 225                 if (compress)
 226                         cd_ratio = CDRATIO_x4;
 227                 else
 228                         cd_ratio = CDRATIO_x2;
 229
 230                 /* if 32 bit, double the cd ratio (so register
 231                    field setting is incremented) */
 232                 if (cfg_width == CFGWDTH_32)
 233                         cd_ratio += 1;
 234         }
 235
 236         fpgamgr_set_cfgwdth(cfg_width);
 237         fpgamgr_set_cd_ratio(cd_ratio);
 238
 239         return 0;
 240 }
 241
 242 static int fpgamgr_reset(void)
 243 {
 244         unsigned long reg;
 245
 246         /* S2F_NCONFIG = 0 */
 247         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 248                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 249
 250         /* Wait for f2s_nstatus == 0 */
 251         if (wait_for_f2s_nstatus_pin(0))
 252                 return -ETIME;
 253
 254         /* S2F_NCONFIG = 1 */
 255         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 256                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 257
 258         /* Wait for f2s_nstatus == 1 */
 259         if (wait_for_f2s_nstatus_pin(1))
 260                 return -ETIME;
 261
 262         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 263         reg = readl(&fpga_manager_base->imgcfg_stat);
 264         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 265                 return -EPERM;
 266
 267         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 268                 return -EPERM;
 269
 270         return 0;
 271 }
 272
 273 /* Start the FPGA programming by initialize the FPGA Manager */
 274 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 275 {
 276         int ret;
 277
 278         /* Step 1 */
 279         if (fpgamgr_verify_msel())
 280                 return -EPERM;
 281
 282         /* Step 2 */
 283         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 284                 return -EPERM;
 285
 286         /*
 287          * Step 3:
 288          * Make sure no other external devices are trying to interfere with
 289          * programming:
 290          */
 291         if (wait_for_nconfig_pin_and_nstatus_pin())
 292                 return -ETIME;
 293
 294         /*
 295          * Step 4:
 296          * Deassert the signal drives from HPS
 297          *
 298          * S2F_NCE = 1
 299          * S2F_PR_REQUEST = 0
 300          * EN_CFG_CTRL = 0
 301          * EN_CFG_DATA = 0
 302          * S2F_NCONFIG = 1
 303          * S2F_NSTATUS_OE = 0
 304          * S2F_CONDONE_OE = 0
 305          */
 306         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 307                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 308
 309         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 310                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 311
 312         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 313                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 314                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 315
 316         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 317                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 318
 319         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 320                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 321                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 322
 323         /*
 324          * Step 5:
 325          * Enable overrides
 326          * S2F_NENABLE_CONFIG = 0
 327          * S2F_NENABLE_NCONFIG = 0
 328          */
 329         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 330                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 331         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 332                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 333
 334         /*
 335          * Disable driving signals that HPS doesn't need to drive.
 336          * S2F_NENABLE_NSTATUS = 1
 337          * S2F_NENABLE_CONDONE = 1
 338          */
 339         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 340                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 341                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 342
 343         /*
 344          * Step 6:
 345          * Drive chip select S2F_NCE = 0
 346          */
 347          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 348                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 349
 350         /* Step 7 */
 351         if (wait_for_nconfig_pin_and_nstatus_pin())
 352                 return -ETIME;
 353
 354         /* Step 8 */
 355         ret = fpgamgr_reset();
 356
 357         if (ret)
 358                 return ret;
 359
 360         /*
 361          * Step 9:
 362          * EN_CFG_CTRL and EN_CFG_DATA = 1
 363          */
 364         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 365                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 366                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 367
 368         return 0;
 369 }
 370
 371 /* Ensure the FPGA entering config done */
 372 static int fpgamgr_program_poll_cd(void)
 373 {
 374         unsigned long reg, i;
 375
 376         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 377                 reg = readl(&fpga_manager_base->imgcfg_stat);
 378                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 379                         return 0;
 380
 381                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 382                         printf("nstatus == 0 while waiting for condone\n");
 383                         return -EPERM;
 384                 }
 385                 schedule();
 386         }
 387
 388         if (i == FPGA_TIMEOUT_CNT)
 389                 return -ETIME;
 390
 391         return 0;
 392 }
 393
 394 /* Ensure the FPGA entering user mode */
 395 static int fpgamgr_program_poll_usermode(void)
 396 {
 397         unsigned long reg;
 398         int ret = 0;
 399
 400         if (fpgamgr_dclkcnt_set(0xf))
 401                 return -ETIME;
 402
 403         ret = wait_for_user_mode();
 404         if (ret < 0) {
 405                 printf("%s: Failed to enter user mode with ", __func__);
 406                 printf("error code %d\n", ret);
 407                 return ret;
 408         }
 409
 410         /*
 411          * Step 14:
 412          * Stop DATA path and Dclk
 413          * EN_CFG_CTRL and EN_CFG_DATA = 0
 414          */
 415         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 416                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 417                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 418
 419         /*
 420          * Step 15:
 421          * Disable overrides
 422          * S2F_NENABLE_CONFIG = 1
 423          * S2F_NENABLE_NCONFIG = 1
 424          */
 425         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 426                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 427         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 428                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 429
 430         /* Disable chip select S2F_NCE = 1 */
 431         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 432                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 433
 434         /*
 435          * Step 16:
 436          * Final check
 437          */
 438         reg = readl(&fpga_manager_base->imgcfg_stat);
 439         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 440                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 441             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 442                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 443             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 444                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 445                 return -EPERM;
 446
 447         return 0;
 448 }
 449
 450 int fpgamgr_program_finish(void)
 451 {
 452         /* Ensure the FPGA entering config done */
 453         int status = fpgamgr_program_poll_cd();
 454
 455         if (status) {
 456                 printf("FPGA: Poll CD failed with error code %d\n", status);
 457                 return -EPERM;
 458         }
 459
 460         /* Ensure the FPGA entering user mode */
 461         status = fpgamgr_program_poll_usermode();
 462         if (status) {
 463                 printf("FPGA: Poll usermode failed with error code %d\n",
 464                         status);
 465                 return -EPERM;
 466         }
 467
 468         printf("Full Configuration Succeeded.\n");
 469
 470         return 0;
 471 }
 472
 473 ofnode get_fpga_mgr_ofnode(ofnode from)
 474 {
 475         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 476 }
 477
 478 const char *get_fpga_filename(void)
 479 {
 480         const char *fpga_filename = NULL;
 481
 482         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 483
 484         if (ofnode_valid(fpgamgr_node))
 485                 fpga_filename = ofnode_read_string(fpgamgr_node,
 486                                                 "altr,bitstream");
 487
 488         return fpga_filename;
 489 }
 490
 491 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 492 {
 493         /*
 494          * Magic ID starting at:
 495          * -> 1st dword[15:0] in periph.rbf
 496          * -> 2nd dword[15:0] in core.rbf
 497          * Note: dword == 32 bits
 498          */
 499         u32 word_reading_max = 2;
 500         u32 i;
 501
 502         for (i = 0; i < word_reading_max; i++) {
 503                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 504                         rbf->security = unencrypted;
 505                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 506                         rbf->security = encrypted;
 507                 } else if (*(buffer + i + 1) ==
 508                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 509                         rbf->security = unencrypted;
 510                 } else if (*(buffer + i + 1) ==
 511                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 512                         rbf->security = encrypted;
 513                 } else {
 514                         rbf->security = invalid;
 515                         continue;
 516                 }
 517
 518                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 519                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 520                         rbf->section = periph_section;
 521                         break;
 522                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 523                         rbf->section = core_section;
 524                         break;
 525                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 526                         rbf->section = periph_section;
 527                         break;
 528                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 529                         rbf->section = core_section;
 530                         break;
 531                 }
 532
 533                 rbf->section = unknown;
 534                 break;
 535
 536                 schedule();
 537         }
 538 }
 539
 540 #ifdef CONFIG_FS_LOADER
 541 static int first_loading_rbf_to_buffer(struct udevice *dev,
 542                                 struct fpga_loadfs_info *fpga_loadfs,
 543                                 u32 *buffer, size_t *buffer_bsize,
 544                                 size_t *buffer_bsize_ori)
 545 {
 546         u32 *buffer_p = (u32 *)*buffer;
 547         u32 *loadable = buffer_p;
 548         size_t buffer_size = *buffer_bsize;
 549         size_t fit_size;
 550         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 551         const char *fpga_node_name = NULL;
 552         const char *uname = NULL;
 553
 554         /* Load image header into buffer */
 555         ret = request_firmware_into_buf(dev,
 556                                         fpga_loadfs->fpga_fsinfo->filename,
 557                                         buffer_p, sizeof(struct legacy_img_hdr),
 558                                         0);
 559         if (ret < 0) {
 560                 debug("FPGA: Failed to read image header from flash.\n");
 561                 return -ENOENT;
 562         }
 563
 564         if (image_get_magic((struct legacy_img_hdr *)buffer_p) != FDT_MAGIC) {
 565                 debug("FPGA: No FDT magic was found.\n");
 566                 return -EBADF;
 567         }
 568
 569         fit_size = fdt_totalsize(buffer_p);
 570
 571         if (fit_size > buffer_size) {
 572                 debug("FPGA: FIT image is larger than available buffer.\n");
 573                 debug("Please use FIT external data or increasing buffer.\n");
 574                 return -ENOMEM;
 575         }
 576
 577         /* Load entire FIT into buffer */
 578         ret = request_firmware_into_buf(dev,
 579                                         fpga_loadfs->fpga_fsinfo->filename,
 580                                         buffer_p, fit_size, 0);
 581         if (ret < 0)
 582                 return ret;
 583
 584         ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
 585         if (ret) {
 586                 debug("FPGA: No valid FIT image was found.\n");
 587                 return ret;
 588         }
 589
 590         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 591         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 592         if (confs_noffset < 0 || images_noffset < 0) {
 593                 debug("FPGA: No Configurations or images nodes were found.\n");
 594                 return -ENOENT;
 595         }
 596
 597         /* Get default configuration unit name from default property */
 598         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 599         if (confs_noffset < 0) {
 600                 debug("FPGA: No default configuration was found in config.\n");
 601                 return -ENOENT;
 602         }
 603
 604         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 605                                             FIT_FPGA_PROP);
 606         if (count < 0) {
 607                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 608                 return count;
 609         }
 610         debug("FPGA: FPGA node count: %d\n", count);
 611
 612         for (i = 0; i < count; i++) {
 613                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 614                                                              confs_noffset,
 615                                                              FIT_FPGA_PROP, i);
 616                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 617                 if (uname) {
 618                         debug("FPGA: %s\n", uname);
 619
 620                         if (strstr(uname, "fpga-periph") &&
 621                                 (!is_fpgamgr_early_user_mode() ||
 622                                 is_fpgamgr_user_mode() ||
 623                                 is_periph_program_force())) {
 624                                 fpga_node_name = uname;
 625                                 printf("FPGA: Start to program ");
 626                                 printf("peripheral/full bitstream ...\n");
 627                                 break;
 628                         } else if (strstr(uname, "fpga-core") &&
 629                                         (is_fpgamgr_early_user_mode() &&
 630                                         !is_fpgamgr_user_mode())) {
 631                                 fpga_node_name = uname;
 632                                 printf("FPGA: Start to program core ");
 633                                 printf("bitstream ...\n");
 634                                 break;
 635                         }
 636                 }
 637                 schedule();
 638         }
 639
 640         if (!fpga_node_name) {
 641                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 642                 return 1;
 643         }
 644
 645         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 646         if (images_noffset < 0) {
 647                 debug("FPGA: No node '%s' was found in FIT.\n",
 648                      fpga_node_name);
 649                 return -ENOENT;
 650         }
 651
 652         if (!fit_image_get_data_position(buffer_p, images_noffset,
 653                                         &rbf_offset)) {
 654                 debug("FPGA: Data position was found.\n");
 655         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 656                   &rbf_offset)) {
 657                 /*
 658                  * For FIT with external data, figure out where
 659                  * the external images start. This is the base
 660                  * for the data-offset properties in each image.
 661                  */
 662                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 663                 debug("FPGA: Data offset was found.\n");
 664         } else {
 665                 debug("FPGA: No data position/offset was found.\n");
 666                 return -ENOENT;
 667         }
 668
 669         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 670         if (ret < 0) {
 671                 debug("FPGA: No data size was found (err=%d).\n", ret);
 672                 return -ENOENT;
 673         }
 674
 675         if (gd->ram_size < rbf_size) {
 676                 debug("FPGA: Using default OCRAM buffer and size.\n");
 677         } else {
 678                 ret = fit_image_get_load(buffer_p, images_noffset,
 679                                         (ulong *)loadable);
 680                 if (ret < 0) {
 681                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 682                         debug("FPGA: No loadable was found.\n");
 683                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 684                              DEFAULT_DDR_LOAD_ADDRESS);
 685                 } else {
 686                         buffer_p = (u32 *)*loadable;
 687                         debug("FPGA: Found loadable address = 0x%x.\n",
 688                              *loadable);
 689                 }
 690
 691                 buffer_size = rbf_size;
 692                 *buffer_bsize_ori = DDR_BUFFER_SIZE;
 693         }
 694
 695         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 696               rbf_offset, rbf_size);
 697
 698         fpga_loadfs->remaining = rbf_size;
 699
 700         /*
 701          * Determine buffer size vs bitstream size, and calculating number of
 702          * chunk by chunk transfer is required due to smaller buffer size
 703          * compare to bitstream
 704          */
 705
 706         if (buffer_size > MAX_FIRST_LOAD_SIZE)
 707                 buffer_size = MAX_FIRST_LOAD_SIZE;
 708
 709         if (rbf_size <= buffer_size) {
 710                 /* Loading whole bitstream into buffer */
 711                 buffer_size = rbf_size;
 712                 fpga_loadfs->remaining = 0;
 713         } else {
 714                 buffer_size -= rbf_offset % buffer_size;
 715                 fpga_loadfs->remaining -= buffer_size;
 716         }
 717
 718         fpga_loadfs->offset = rbf_offset;
 719         /* Loading bitstream into buffer */
 720         ret = request_firmware_into_buf(dev,
 721                                         fpga_loadfs->fpga_fsinfo->filename,
 722                                         buffer_p, buffer_size,
 723                                         fpga_loadfs->offset);
 724         if (ret < 0) {
 725                 debug("FPGA: Failed to read bitstream from flash.\n");
 726                 return -ENOENT;
 727         }
 728
 729         /* Getting info about bitstream types */
 730         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 731
 732         /* Update next reading bitstream offset */
 733         fpga_loadfs->offset += buffer_size;
 734
 735         /* Update the final addr for bitstream */
 736         *buffer = (u32)buffer_p;
 737
 738         /* Update the size of bitstream to be programmed into FPGA */
 739         *buffer_bsize = buffer_size;
 740
 741         return 0;
 742 }
 743
 744 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 745                                         struct fpga_loadfs_info *fpga_loadfs,
 746                                         u32 *buffer, size_t *buffer_bsize)
 747 {
 748         int ret = 0;
 749         u32 *buffer_p = (u32 *)*buffer;
 750
 751         /* Read the bitstream chunk by chunk. */
 752         if (fpga_loadfs->remaining > *buffer_bsize) {
 753                 fpga_loadfs->remaining -= *buffer_bsize;
 754         } else {
 755                 *buffer_bsize = fpga_loadfs->remaining;
 756                 fpga_loadfs->remaining = 0;
 757         }
 758
 759         ret = request_firmware_into_buf(dev,
 760                                         fpga_loadfs->fpga_fsinfo->filename,
 761                                         buffer_p, *buffer_bsize,
 762                                         fpga_loadfs->offset);
 763         if (ret < 0) {
 764                 debug("FPGA: Failed to read bitstream from flash.\n");
 765                 return -ENOENT;
 766         }
 767
 768         /* Update next reading bitstream offset */
 769         fpga_loadfs->offset += *buffer_bsize;
 770
 771         return 0;
 772 }
 773
 774 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 775                         u32 offset)
 776 {
 777         struct fpga_loadfs_info fpga_loadfs;
 778         struct udevice *dev;
 779         int status, ret;
 780         u32 buffer = (uintptr_t)buf;
 781         size_t buffer_sizebytes = bsize;
 782         size_t buffer_sizebytes_ori = bsize;
 783         size_t total_sizeof_image = 0;
 784         ofnode node;
 785
 786         node = get_fpga_mgr_ofnode(ofnode_null());
 787         if (!ofnode_valid(node)) {
 788                 debug("FPGA: FPGA manager node was not found.\n");
 789                 return -ENOENT;
 790         }
 791
 792         ret = get_fs_loader(&dev);
 793         if (ret)
 794                 return ret;
 795
 796         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 797
 798         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 799         fpga_loadfs.offset = offset;
 800
 801         printf("FPGA: Checking FPGA configuration setting ...\n");
 802
 803         /*
 804          * Note: Both buffer and buffer_sizebytes values can be altered by
 805          * function below.
 806          */
 807         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 808                                            &buffer_sizebytes,
 809                                            &buffer_sizebytes_ori);
 810         if (ret == 1) {
 811                 printf("FPGA: Skipping configuration ...\n");
 812                 return 0;
 813         } else if (ret) {
 814                 return ret;
 815         }
 816
 817         if (fpga_loadfs.rbfinfo.section == core_section &&
 818                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 819                 debug("FPGA : Must be in Early Release mode to program ");
 820                 debug("core bitstream.\n");
 821                 return -EPERM;
 822         }
 823
 824         /* Disable all signals from HPS peripheral controller to FPGA */
 825         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 826
 827         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 828         socfpga_bridges_reset();
 829
 830         if (fpga_loadfs.rbfinfo.section == periph_section) {
 831                 /* Initialize the FPGA Manager */
 832                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 833                 if (status) {
 834                         debug("FPGA: Init with peripheral bitstream failed.\n");
 835                         return -EPERM;
 836                 }
 837         }
 838
 839         /* Transfer bitstream to FPGA Manager */
 840         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 841
 842         total_sizeof_image += buffer_sizebytes;
 843
 844         while (fpga_loadfs.remaining) {
 845                 ret = subsequent_loading_rbf_to_buffer(dev,
 846                                                         &fpga_loadfs,
 847                                                         &buffer,
 848                                                         &buffer_sizebytes_ori);
 849
 850                 if (ret)
 851                         return ret;
 852
 853                 /* Transfer data to FPGA Manager */
 854                 fpgamgr_program_write((void *)buffer,
 855                                         buffer_sizebytes_ori);
 856
 857                 total_sizeof_image += buffer_sizebytes_ori;
 858
 859                 schedule();
 860         }
 861         wait_for_fifo_empty();
 862
 863         if (fpga_loadfs.rbfinfo.section == periph_section) {
 864                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 865                         config_pins(gd->fdt_blob, "shared");
 866                         puts("FPGA: Early Release Succeeded.\n");
 867                 } else {
 868                         debug("FPGA: Failed to see Early Release.\n");
 869                         return -EIO;
 870                 }
 871
 872                 /* For monolithic bitstream */
 873                 if (is_fpgamgr_user_mode()) {
 874                         /* Ensure the FPGA entering config done */
 875                         status = fpgamgr_program_finish();
 876                         if (status)
 877                                 return status;
 878
 879                         config_pins(gd->fdt_blob, "fpga");
 880                         puts("FPGA: Enter user mode.\n");
 881                 }
 882         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 883                 /* Ensure the FPGA entering config done */
 884                 status = fpgamgr_program_finish();
 885                 if (status)
 886                         return status;
 887
 888                 config_pins(gd->fdt_blob, "fpga");
 889                 puts("FPGA: Enter user mode.\n");
 890         } else {
 891                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 892                 return -ENOEXEC;
 893         }
 894
 895         return (int)total_sizeof_image;
 896 }
 897
 898 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 899 {
 900         fpga_fs_info fpga_fsinfo;
 901
 902         fpga_fsinfo.filename = get_fpga_filename();
 903
 904         if (fpga_fsinfo.filename)
 905                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 906 }
 907 #endif
 908
 909 /* This function is used to load the core bitstream from the OCRAM. */
 910 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 911 {
 912         unsigned long status;
 913         struct rbf_info rbfinfo;
 914
 915         memset(&rbfinfo, 0, sizeof(rbfinfo));
 916
 917         /* Disable all signals from hps peripheral controller to fpga */
 918         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 919
 920         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 921         socfpga_bridges_reset();
 922
 923         /* Getting info about bitstream types */
 924         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 925
 926         if (rbfinfo.section == periph_section) {
 927                 /* Initialize the FPGA Manager */
 928                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 929                 if (status)
 930                         return status;
 931         }
 932
 933         if (rbfinfo.section == core_section &&
 934                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 935                 debug("FPGA : Must be in early release mode to program ");
 936                 debug("core bitstream.\n");
 937                 return -EPERM;
 938         }
 939
 940         /* Write the bitstream to FPGA Manager */
 941         fpgamgr_program_write(rbf_data, rbf_size);
 942
 943         status = fpgamgr_program_finish();
 944         if (status)
 945                 return status;
 946
 947         config_pins(gd->fdt_blob, "fpga");
 948         puts("FPGA: Enter user mode.\n");
 949
 950         return status;
 951 }