drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <asm/io.h>
   7 #include <asm/arch/fpga_manager.h>
   8 #include <asm/arch/reset_manager.h>
   9 #include <asm/arch/system_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/misc.h>
  12 #include <altera.h>
  13 #include <asm/arch/pinmux.h>
  14 #include <common.h>
  15 #include <dm/ofnode.h>
  16 #include <errno.h>
  17 #include <fs_loader.h>
  18 #include <wait_bit.h>
  19 #include <watchdog.h>
  20
  21 #define CFGWDTH_32      1
  22 #define MIN_BITSTREAM_SIZECHECK 230
  23 #define ENCRYPTION_OFFSET       69
  24 #define COMPRESSION_OFFSET      229
  25 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  26 #define FPGA_TIMEOUT_CNT        0x1000000
  27 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 static const struct socfpga_fpga_manager *fpga_manager_base =
  32                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  33
  34 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  35
  36 static uint32_t fpgamgr_get_msel(void)
  37 {
  38         u32 reg;
  39
  40         reg = readl(&fpga_manager_base->imgcfg_stat);
  41         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  42                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  43
  44         return reg;
  45 }
  46
  47 static void fpgamgr_set_cfgwdth(int width)
  48 {
  49         if (width)
  50                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  51                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  52         else
  53                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  54                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  55 }
  56
  57 int is_fpgamgr_user_mode(void)
  58 {
  59         return (readl(&fpga_manager_base->imgcfg_stat) &
  60                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  61 }
  62
  63 static int wait_for_user_mode(void)
  64 {
  65         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  66                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  67                 1, FPGA_TIMEOUT_MSEC, false);
  68 }
  69
  70 int is_fpgamgr_early_user_mode(void)
  71 {
  72         return (readl(&fpga_manager_base->imgcfg_stat) &
  73                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  74 }
  75
  76 int fpgamgr_wait_early_user_mode(void)
  77 {
  78         u32 sync_data = 0xffffffff;
  79         u32 i = 0;
  80         unsigned start = get_timer(0);
  81         unsigned long cd_ratio;
  82
  83         /* Getting existing CDRATIO */
  84         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  85                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  86                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  87
  88         /* Using CDRATIO_X1 for better compatibility */
  89         fpgamgr_set_cd_ratio(CDRATIO_x1);
  90
  91         while (!is_fpgamgr_early_user_mode()) {
  92                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  93                         return -ETIMEDOUT;
  94                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  95                                 sizeof(sync_data));
  96                 udelay(FPGA_TIMEOUT_MSEC);
  97                 i++;
  98         }
  99
 100         debug("FPGA: Additional %i sync word needed\n", i);
 101
 102         /* restoring original CDRATIO */
 103         fpgamgr_set_cd_ratio(cd_ratio);
 104
 105         return 0;
 106 }
 107
 108 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 109 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 110 {
 111         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 112                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 113
 114         /*
 115          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 116          * de-asserted, timeout at 1000ms
 117          */
 118         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 119                                  true, FPGA_TIMEOUT_MSEC, false);
 120 }
 121
 122 static int wait_for_f2s_nstatus_pin(unsigned long value)
 123 {
 124         /* Poll until f2s to specific value, timeout at 1000ms */
 125         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 126                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 127                 value, FPGA_TIMEOUT_MSEC, false);
 128 }
 129
 130 /* set CD ratio */
 131 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 132 {
 133         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 134                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 135
 136         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 137                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 138                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 139 }
 140
 141 /* get the MSEL value, verify we are set for FPP configuration mode */
 142 static int fpgamgr_verify_msel(void)
 143 {
 144         u32 msel = fpgamgr_get_msel();
 145
 146         if (msel & ~BIT(0)) {
 147                 printf("Fail: read msel=%d\n", msel);
 148                 return -EPERM;
 149         }
 150
 151         return 0;
 152 }
 153
 154 /*
 155  * Write cdratio and cdwidth based on whether the bitstream is compressed
 156  * and/or encoded
 157  */
 158 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 159                                        size_t rbf_size)
 160 {
 161         unsigned int cd_ratio;
 162         bool encrypt, compress;
 163
 164         /*
 165          * According to the bitstream specification,
 166          * both encryption and compression status are
 167          * in location before offset 230 of the buffer.
 168          */
 169         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 170                 return -EINVAL;
 171
 172         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 173         encrypt = encrypt != 0;
 174
 175         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 176         compress = !compress;
 177
 178         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 179         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 180         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 181              compress);
 182
 183         /*
 184          * from the register map description of cdratio in imgcfg_ctrl_02:
 185          *  Normal Configuration    : 32bit Passive Parallel
 186          *  Partial Reconfiguration : 16bit Passive Parallel
 187          */
 188
 189         /*
 190          * cd ratio is dependent on cfg width and whether the bitstream
 191          * is encrypted and/or compressed.
 192          *
 193          * | width | encr. | compr. | cd ratio |
 194          * |  16   |   0   |   0    |     1    |
 195          * |  16   |   0   |   1    |     4    |
 196          * |  16   |   1   |   0    |     2    |
 197          * |  16   |   1   |   1    |     4    |
 198          * |  32   |   0   |   0    |     1    |
 199          * |  32   |   0   |   1    |     8    |
 200          * |  32   |   1   |   0    |     4    |
 201          * |  32   |   1   |   1    |     8    |
 202          */
 203         if (!compress && !encrypt) {
 204                 cd_ratio = CDRATIO_x1;
 205         } else {
 206                 if (compress)
 207                         cd_ratio = CDRATIO_x4;
 208                 else
 209                         cd_ratio = CDRATIO_x2;
 210
 211                 /* if 32 bit, double the cd ratio (so register
 212                    field setting is incremented) */
 213                 if (cfg_width == CFGWDTH_32)
 214                         cd_ratio += 1;
 215         }
 216
 217         fpgamgr_set_cfgwdth(cfg_width);
 218         fpgamgr_set_cd_ratio(cd_ratio);
 219
 220         return 0;
 221 }
 222
 223 static int fpgamgr_reset(void)
 224 {
 225         unsigned long reg;
 226
 227         /* S2F_NCONFIG = 0 */
 228         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 229                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 230
 231         /* Wait for f2s_nstatus == 0 */
 232         if (wait_for_f2s_nstatus_pin(0))
 233                 return -ETIME;
 234
 235         /* S2F_NCONFIG = 1 */
 236         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 237                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 238
 239         /* Wait for f2s_nstatus == 1 */
 240         if (wait_for_f2s_nstatus_pin(1))
 241                 return -ETIME;
 242
 243         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 244         reg = readl(&fpga_manager_base->imgcfg_stat);
 245         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 246                 return -EPERM;
 247
 248         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 249                 return -EPERM;
 250
 251         return 0;
 252 }
 253
 254 /* Start the FPGA programming by initialize the FPGA Manager */
 255 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 256 {
 257         int ret;
 258
 259         /* Step 1 */
 260         if (fpgamgr_verify_msel())
 261                 return -EPERM;
 262
 263         /* Step 2 */
 264         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 265                 return -EPERM;
 266
 267         /*
 268          * Step 3:
 269          * Make sure no other external devices are trying to interfere with
 270          * programming:
 271          */
 272         if (wait_for_nconfig_pin_and_nstatus_pin())
 273                 return -ETIME;
 274
 275         /*
 276          * Step 4:
 277          * Deassert the signal drives from HPS
 278          *
 279          * S2F_NCE = 1
 280          * S2F_PR_REQUEST = 0
 281          * EN_CFG_CTRL = 0
 282          * EN_CFG_DATA = 0
 283          * S2F_NCONFIG = 1
 284          * S2F_NSTATUS_OE = 0
 285          * S2F_CONDONE_OE = 0
 286          */
 287         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 288                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 289
 290         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 291                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 292
 293         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 294                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 295                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 296
 297         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 298                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 299
 300         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 301                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 302                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 303
 304         /*
 305          * Step 5:
 306          * Enable overrides
 307          * S2F_NENABLE_CONFIG = 0
 308          * S2F_NENABLE_NCONFIG = 0
 309          */
 310         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 311                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 312         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 313                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 314
 315         /*
 316          * Disable driving signals that HPS doesn't need to drive.
 317          * S2F_NENABLE_NSTATUS = 1
 318          * S2F_NENABLE_CONDONE = 1
 319          */
 320         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 321                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 322                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 323
 324         /*
 325          * Step 6:
 326          * Drive chip select S2F_NCE = 0
 327          */
 328          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 329                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 330
 331         /* Step 7 */
 332         if (wait_for_nconfig_pin_and_nstatus_pin())
 333                 return -ETIME;
 334
 335         /* Step 8 */
 336         ret = fpgamgr_reset();
 337
 338         if (ret)
 339                 return ret;
 340
 341         /*
 342          * Step 9:
 343          * EN_CFG_CTRL and EN_CFG_DATA = 1
 344          */
 345         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 346                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 347                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 348
 349         return 0;
 350 }
 351
 352 /* Ensure the FPGA entering config done */
 353 static int fpgamgr_program_poll_cd(void)
 354 {
 355         unsigned long reg, i;
 356
 357         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 358                 reg = readl(&fpga_manager_base->imgcfg_stat);
 359                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 360                         return 0;
 361
 362                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 363                         printf("nstatus == 0 while waiting for condone\n");
 364                         return -EPERM;
 365                 }
 366                 WATCHDOG_RESET();
 367         }
 368
 369         if (i == FPGA_TIMEOUT_CNT)
 370                 return -ETIME;
 371
 372         return 0;
 373 }
 374
 375 /* Ensure the FPGA entering user mode */
 376 static int fpgamgr_program_poll_usermode(void)
 377 {
 378         unsigned long reg;
 379         int ret = 0;
 380
 381         if (fpgamgr_dclkcnt_set(0xf))
 382                 return -ETIME;
 383
 384         ret = wait_for_user_mode();
 385         if (ret < 0) {
 386                 printf("%s: Failed to enter user mode with ", __func__);
 387                 printf("error code %d\n", ret);
 388                 return ret;
 389         }
 390
 391         /*
 392          * Step 14:
 393          * Stop DATA path and Dclk
 394          * EN_CFG_CTRL and EN_CFG_DATA = 0
 395          */
 396         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 397                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 398                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 399
 400         /*
 401          * Step 15:
 402          * Disable overrides
 403          * S2F_NENABLE_CONFIG = 1
 404          * S2F_NENABLE_NCONFIG = 1
 405          */
 406         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 407                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 408         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 409                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 410
 411         /* Disable chip select S2F_NCE = 1 */
 412         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 413                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 414
 415         /*
 416          * Step 16:
 417          * Final check
 418          */
 419         reg = readl(&fpga_manager_base->imgcfg_stat);
 420         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 421                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 422             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 423                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 424             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 425                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 426                 return -EPERM;
 427
 428         return 0;
 429 }
 430
 431 int fpgamgr_program_finish(void)
 432 {
 433         /* Ensure the FPGA entering config done */
 434         int status = fpgamgr_program_poll_cd();
 435
 436         if (status) {
 437                 printf("FPGA: Poll CD failed with error code %d\n", status);
 438                 return -EPERM;
 439         }
 440
 441         /* Ensure the FPGA entering user mode */
 442         status = fpgamgr_program_poll_usermode();
 443         if (status) {
 444                 printf("FPGA: Poll usermode failed with error code %d\n",
 445                         status);
 446                 return -EPERM;
 447         }
 448
 449         printf("Full Configuration Succeeded.\n");
 450
 451         return 0;
 452 }
 453
 454 ofnode get_fpga_mgr_ofnode(ofnode from)
 455 {
 456         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 457 }
 458
 459 const char *get_fpga_filename(void)
 460 {
 461         const char *fpga_filename = NULL;
 462
 463         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 464
 465         if (ofnode_valid(fpgamgr_node))
 466                 fpga_filename = ofnode_read_string(fpgamgr_node,
 467                                                 "altr,bitstream");
 468
 469         return fpga_filename;
 470 }
 471
 472 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 473 {
 474         /*
 475          * Magic ID starting at:
 476          * -> 1st dword[15:0] in periph.rbf
 477          * -> 2nd dword[15:0] in core.rbf
 478          * Note: dword == 32 bits
 479          */
 480         u32 word_reading_max = 2;
 481         u32 i;
 482
 483         for (i = 0; i < word_reading_max; i++) {
 484                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 485                         rbf->security = unencrypted;
 486                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 487                         rbf->security = encrypted;
 488                 } else if (*(buffer + i + 1) ==
 489                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 490                         rbf->security = unencrypted;
 491                 } else if (*(buffer + i + 1) ==
 492                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 493                         rbf->security = encrypted;
 494                 } else {
 495                         rbf->security = invalid;
 496                         continue;
 497                 }
 498
 499                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 500                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 501                         rbf->section = periph_section;
 502                         break;
 503                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 504                         rbf->section = core_section;
 505                         break;
 506                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 507                         rbf->section = periph_section;
 508                         break;
 509                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 510                         rbf->section = core_section;
 511                         break;
 512                 }
 513
 514                 rbf->section = unknown;
 515                 break;
 516
 517                 WATCHDOG_RESET();
 518         }
 519 }
 520
 521 #ifdef CONFIG_FS_LOADER
 522 static int first_loading_rbf_to_buffer(struct udevice *dev,
 523                                 struct fpga_loadfs_info *fpga_loadfs,
 524                                 u32 *buffer, size_t *buffer_bsize)
 525 {
 526         u32 *buffer_p = (u32 *)*buffer;
 527         u32 *loadable = buffer_p;
 528         size_t buffer_size = *buffer_bsize;
 529         size_t fit_size;
 530         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 531         const char *fpga_node_name = NULL;
 532         const char *uname = NULL;
 533
 534         /* Load image header into buffer */
 535         ret = request_firmware_into_buf(dev,
 536                                         fpga_loadfs->fpga_fsinfo->filename,
 537                                         buffer_p, sizeof(struct image_header),
 538                                         0);
 539         if (ret < 0) {
 540                 debug("FPGA: Failed to read image header from flash.\n");
 541                 return -ENOENT;
 542         }
 543
 544         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 545                 debug("FPGA: No FDT magic was found.\n");
 546                 return -EBADF;
 547         }
 548
 549         fit_size = fdt_totalsize(buffer_p);
 550
 551         if (fit_size > buffer_size) {
 552                 debug("FPGA: FIT image is larger than available buffer.\n");
 553                 debug("Please use FIT external data or increasing buffer.\n");
 554                 return -ENOMEM;
 555         }
 556
 557         /* Load entire FIT into buffer */
 558         ret = request_firmware_into_buf(dev,
 559                                         fpga_loadfs->fpga_fsinfo->filename,
 560                                         buffer_p, fit_size, 0);
 561         if (ret < 0)
 562                 return ret;
 563
 564         ret = fit_check_format(buffer_p);
 565         if (!ret) {
 566                 debug("FPGA: No valid FIT image was found.\n");
 567                 return -EBADF;
 568         }
 569
 570         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 571         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 572         if (confs_noffset < 0 || images_noffset < 0) {
 573                 debug("FPGA: No Configurations or images nodes were found.\n");
 574                 return -ENOENT;
 575         }
 576
 577         /* Get default configuration unit name from default property */
 578         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 579         if (confs_noffset < 0) {
 580                 debug("FPGA: No default configuration was found in config.\n");
 581                 return -ENOENT;
 582         }
 583
 584         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 585                                             FIT_FPGA_PROP);
 586         if (count < 0) {
 587                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 588                 return count;
 589         }
 590         debug("FPGA: FPGA node count: %d\n", count);
 591
 592         for (i = 0; i < count; i++) {
 593                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 594                                                              confs_noffset,
 595                                                              FIT_FPGA_PROP, i);
 596                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 597                 if (uname) {
 598                         debug("FPGA: %s\n", uname);
 599
 600                         if (strstr(uname, "fpga-periph") &&
 601                                 (!is_fpgamgr_early_user_mode() ||
 602                                 is_fpgamgr_user_mode())) {
 603                                 fpga_node_name = uname;
 604                                 printf("FPGA: Start to program ");
 605                                 printf("peripheral/full bitstream ...\n");
 606                                 break;
 607                         } else if (strstr(uname, "fpga-core") &&
 608                                         (is_fpgamgr_early_user_mode() &&
 609                                         !is_fpgamgr_user_mode())) {
 610                                 fpga_node_name = uname;
 611                                 printf("FPGA: Start to program core ");
 612                                 printf("bitstream ...\n");
 613                                 break;
 614                         }
 615                 }
 616                 WATCHDOG_RESET();
 617         }
 618
 619         if (!fpga_node_name) {
 620                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 621                 return 1;
 622         }
 623
 624         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 625         if (images_noffset < 0) {
 626                 debug("FPGA: No node '%s' was found in FIT.\n",
 627                      fpga_node_name);
 628                 return -ENOENT;
 629         }
 630
 631         if (!fit_image_get_data_position(buffer_p, images_noffset,
 632                                         &rbf_offset)) {
 633                 debug("FPGA: Data position was found.\n");
 634         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 635                   &rbf_offset)) {
 636                 /*
 637                  * For FIT with external data, figure out where
 638                  * the external images start. This is the base
 639                  * for the data-offset properties in each image.
 640                  */
 641                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 642                 debug("FPGA: Data offset was found.\n");
 643         } else {
 644                 debug("FPGA: No data position/offset was found.\n");
 645                 return -ENOENT;
 646         }
 647
 648         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 649         if (ret < 0) {
 650                 debug("FPGA: No data size was found (err=%d).\n", ret);
 651                 return -ENOENT;
 652         }
 653
 654         if (gd->ram_size < rbf_size) {
 655                 debug("FPGA: Using default OCRAM buffer and size.\n");
 656         } else {
 657                 ret = fit_image_get_load(buffer_p, images_noffset,
 658                                         (ulong *)loadable);
 659                 if (ret < 0) {
 660                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 661                         debug("FPGA: No loadable was found.\n");
 662                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 663                              DEFAULT_DDR_LOAD_ADDRESS);
 664                 } else {
 665                         buffer_p = (u32 *)*loadable;
 666                         debug("FPGA: Found loadable address = 0x%x.\n",
 667                              *loadable);
 668                 }
 669
 670                 buffer_size = rbf_size;
 671         }
 672
 673         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 674               rbf_offset, rbf_size);
 675
 676         fpga_loadfs->remaining = rbf_size;
 677
 678         /*
 679          * Determine buffer size vs bitstream size, and calculating number of
 680          * chunk by chunk transfer is required due to smaller buffer size
 681          * compare to bitstream
 682          */
 683         if (rbf_size <= buffer_size) {
 684                 /* Loading whole bitstream into buffer */
 685                 buffer_size = rbf_size;
 686                 fpga_loadfs->remaining = 0;
 687         } else {
 688                 fpga_loadfs->remaining -= buffer_size;
 689         }
 690
 691         fpga_loadfs->offset = rbf_offset;
 692         /* Loading bitstream into buffer */
 693         ret = request_firmware_into_buf(dev,
 694                                         fpga_loadfs->fpga_fsinfo->filename,
 695                                         buffer_p, buffer_size,
 696                                         fpga_loadfs->offset);
 697         if (ret < 0) {
 698                 debug("FPGA: Failed to read bitstream from flash.\n");
 699                 return -ENOENT;
 700         }
 701
 702         /* Getting info about bitstream types */
 703         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 704
 705         /* Update next reading bitstream offset */
 706         fpga_loadfs->offset += buffer_size;
 707
 708         /* Update the final addr for bitstream */
 709         *buffer = (u32)buffer_p;
 710
 711         /* Update the size of bitstream to be programmed into FPGA */
 712         *buffer_bsize = buffer_size;
 713
 714         return 0;
 715 }
 716
 717 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 718                                         struct fpga_loadfs_info *fpga_loadfs,
 719                                         u32 *buffer, size_t *buffer_bsize)
 720 {
 721         int ret = 0;
 722         u32 *buffer_p = (u32 *)*buffer;
 723
 724         /* Read the bitstream chunk by chunk. */
 725         if (fpga_loadfs->remaining > *buffer_bsize) {
 726                 fpga_loadfs->remaining -= *buffer_bsize;
 727         } else {
 728                 *buffer_bsize = fpga_loadfs->remaining;
 729                 fpga_loadfs->remaining = 0;
 730         }
 731
 732         ret = request_firmware_into_buf(dev,
 733                                         fpga_loadfs->fpga_fsinfo->filename,
 734                                         buffer_p, *buffer_bsize,
 735                                         fpga_loadfs->offset);
 736         if (ret < 0) {
 737                 debug("FPGA: Failed to read bitstream from flash.\n");
 738                 return -ENOENT;
 739         }
 740
 741         /* Update next reading bitstream offset */
 742         fpga_loadfs->offset += *buffer_bsize;
 743
 744         return 0;
 745 }
 746
 747 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 748                         u32 offset)
 749 {
 750         struct fpga_loadfs_info fpga_loadfs;
 751         struct udevice *dev;
 752         int status, ret, size;
 753         u32 buffer = (uintptr_t)buf;
 754         size_t buffer_sizebytes = bsize;
 755         size_t buffer_sizebytes_ori = bsize;
 756         size_t total_sizeof_image = 0;
 757         ofnode node;
 758         const fdt32_t *phandle_p;
 759         u32 phandle;
 760
 761         node = get_fpga_mgr_ofnode(ofnode_null());
 762
 763         if (ofnode_valid(node)) {
 764                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 765                 if (!phandle_p) {
 766                         node = ofnode_path("/chosen");
 767                         if (!ofnode_valid(node)) {
 768                                 debug("FPGA: /chosen node was not found.\n");
 769                                 return -ENOENT;
 770                         }
 771
 772                         phandle_p = ofnode_get_property(node, "firmware-loader",
 773                                                        &size);
 774                         if (!phandle_p) {
 775                                 debug("FPGA: firmware-loader property was not");
 776                                 debug(" found.\n");
 777                                 return -ENOENT;
 778                         }
 779                 }
 780         } else {
 781                 debug("FPGA: FPGA manager node was not found.\n");
 782                 return -ENOENT;
 783         }
 784
 785         phandle = fdt32_to_cpu(*phandle_p);
 786         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 787                                              phandle, &dev);
 788         if (ret)
 789                 return ret;
 790
 791         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 792
 793         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 794         fpga_loadfs.offset = offset;
 795
 796         printf("FPGA: Checking FPGA configuration setting ...\n");
 797
 798         /*
 799          * Note: Both buffer and buffer_sizebytes values can be altered by
 800          * function below.
 801          */
 802         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 803                                            &buffer_sizebytes);
 804         if (ret == 1) {
 805                 printf("FPGA: Skipping configuration ...\n");
 806                 return 0;
 807         } else if (ret) {
 808                 return ret;
 809         }
 810
 811         if (fpga_loadfs.rbfinfo.section == core_section &&
 812                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 813                 debug("FPGA : Must be in Early Release mode to program ");
 814                 debug("core bitstream.\n");
 815                 return -EPERM;
 816         }
 817
 818         /* Disable all signals from HPS peripheral controller to FPGA */
 819         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 820
 821         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 822         socfpga_bridges_reset();
 823
 824         if (fpga_loadfs.rbfinfo.section == periph_section) {
 825                 /* Initialize the FPGA Manager */
 826                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 827                 if (status) {
 828                         debug("FPGA: Init with peripheral bitstream failed.\n");
 829                         return -EPERM;
 830                 }
 831         }
 832
 833         /* Transfer bitstream to FPGA Manager */
 834         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 835
 836         total_sizeof_image += buffer_sizebytes;
 837
 838         while (fpga_loadfs.remaining) {
 839                 ret = subsequent_loading_rbf_to_buffer(dev,
 840                                                         &fpga_loadfs,
 841                                                         &buffer,
 842                                                         &buffer_sizebytes_ori);
 843
 844                 if (ret)
 845                         return ret;
 846
 847                 /* Transfer data to FPGA Manager */
 848                 fpgamgr_program_write((void *)buffer,
 849                                         buffer_sizebytes_ori);
 850
 851                 total_sizeof_image += buffer_sizebytes_ori;
 852
 853                 WATCHDOG_RESET();
 854         }
 855
 856         if (fpga_loadfs.rbfinfo.section == periph_section) {
 857                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 858                         config_pins(gd->fdt_blob, "shared");
 859                         puts("FPGA: Early Release Succeeded.\n");
 860                 } else {
 861                         debug("FPGA: Failed to see Early Release.\n");
 862                         return -EIO;
 863                 }
 864
 865                 /* For monolithic bitstream */
 866                 if (is_fpgamgr_user_mode()) {
 867                         /* Ensure the FPGA entering config done */
 868                         status = fpgamgr_program_finish();
 869                         if (status)
 870                                 return status;
 871
 872                         config_pins(gd->fdt_blob, "fpga");
 873                         puts("FPGA: Enter user mode.\n");
 874                 }
 875         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 876                 /* Ensure the FPGA entering config done */
 877                 status = fpgamgr_program_finish();
 878                 if (status)
 879                         return status;
 880
 881                 config_pins(gd->fdt_blob, "fpga");
 882                 puts("FPGA: Enter user mode.\n");
 883         } else {
 884                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 885                 return -ENOEXEC;
 886         }
 887
 888         return (int)total_sizeof_image;
 889 }
 890
 891 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 892 {
 893         fpga_fs_info fpga_fsinfo;
 894
 895         fpga_fsinfo.filename = get_fpga_filename();
 896
 897         if (fpga_fsinfo.filename)
 898                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 899 }
 900 #endif
 901
 902 /* This function is used to load the core bitstream from the OCRAM. */
 903 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 904 {
 905         unsigned long status;
 906         struct rbf_info rbfinfo;
 907
 908         memset(&rbfinfo, 0, sizeof(rbfinfo));
 909
 910         /* Disable all signals from hps peripheral controller to fpga */
 911         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 912
 913         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 914         socfpga_bridges_reset();
 915
 916         /* Getting info about bitstream types */
 917         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 918
 919         if (rbfinfo.section == periph_section) {
 920                 /* Initialize the FPGA Manager */
 921                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 922                 if (status)
 923                         return status;
 924         }
 925
 926         if (rbfinfo.section == core_section &&
 927                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 928                 debug("FPGA : Must be in early release mode to program ");
 929                 debug("core bitstream.\n");
 930                 return -EPERM;
 931         }
 932
 933         /* Write the bitstream to FPGA Manager */
 934         fpgamgr_program_write(rbf_data, rbf_size);
 935
 936         status = fpgamgr_program_finish();
 937         if (status)
 938                 return status;
 939
 940         config_pins(gd->fdt_blob, "fpga");
 941         puts("FPGA: Enter user mode.\n");
 942
 943         return status;
 944 }