drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <log.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/fpga_manager.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/misc.h>
  13 #include <altera.h>
  14 #include <asm/arch/pinmux.h>
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <dm/ofnode.h>
  18 #include <errno.h>
  19 #include <fs_loader.h>
  20 #include <wait_bit.h>
  21 #include <watchdog.h>
  22 #include <linux/bitops.h>
  23 #include <linux/delay.h>
  24
  25 #define CFGWDTH_32      1
  26 #define MIN_BITSTREAM_SIZECHECK 230
  27 #define ENCRYPTION_OFFSET       69
  28 #define COMPRESSION_OFFSET      229
  29 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  30 #define FPGA_TIMEOUT_CNT        0x1000000
  31 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 static const struct socfpga_fpga_manager *fpga_manager_base =
  36                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  37
  38 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  39
  40 static uint32_t fpgamgr_get_msel(void)
  41 {
  42         u32 reg;
  43
  44         reg = readl(&fpga_manager_base->imgcfg_stat);
  45         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  46                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  47
  48         return reg;
  49 }
  50
  51 static void fpgamgr_set_cfgwdth(int width)
  52 {
  53         if (width)
  54                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  55                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  56         else
  57                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  58                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  59 }
  60
  61 int is_fpgamgr_user_mode(void)
  62 {
  63         return (readl(&fpga_manager_base->imgcfg_stat) &
  64                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  65 }
  66
  67 static int wait_for_user_mode(void)
  68 {
  69         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  70                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  71                 1, FPGA_TIMEOUT_MSEC, false);
  72 }
  73
  74 int is_fpgamgr_early_user_mode(void)
  75 {
  76         return (readl(&fpga_manager_base->imgcfg_stat) &
  77                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  78 }
  79
  80 int fpgamgr_wait_early_user_mode(void)
  81 {
  82         u32 sync_data = 0xffffffff;
  83         u32 i = 0;
  84         unsigned start = get_timer(0);
  85         unsigned long cd_ratio;
  86
  87         /* Getting existing CDRATIO */
  88         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  89                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  90                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  91
  92         /* Using CDRATIO_X1 for better compatibility */
  93         fpgamgr_set_cd_ratio(CDRATIO_x1);
  94
  95         while (!is_fpgamgr_early_user_mode()) {
  96                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  97                         return -ETIMEDOUT;
  98                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  99                                 sizeof(sync_data));
 100                 udelay(FPGA_TIMEOUT_MSEC);
 101                 i++;
 102         }
 103
 104         debug("FPGA: Additional %i sync word needed\n", i);
 105
 106         /* restoring original CDRATIO */
 107         fpgamgr_set_cd_ratio(cd_ratio);
 108
 109         return 0;
 110 }
 111
 112 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 113 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 114 {
 115         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 116                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 117
 118         /*
 119          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 120          * de-asserted, timeout at 1000ms
 121          */
 122         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 123                                  true, FPGA_TIMEOUT_MSEC, false);
 124 }
 125
 126 static int wait_for_f2s_nstatus_pin(unsigned long value)
 127 {
 128         /* Poll until f2s to specific value, timeout at 1000ms */
 129         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 130                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 131                 value, FPGA_TIMEOUT_MSEC, false);
 132 }
 133
 134 /* set CD ratio */
 135 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 136 {
 137         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 138                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 139
 140         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 141                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 142                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 143 }
 144
 145 /* get the MSEL value, verify we are set for FPP configuration mode */
 146 static int fpgamgr_verify_msel(void)
 147 {
 148         u32 msel = fpgamgr_get_msel();
 149
 150         if (msel & ~BIT(0)) {
 151                 printf("Fail: read msel=%d\n", msel);
 152                 return -EPERM;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /*
 159  * Write cdratio and cdwidth based on whether the bitstream is compressed
 160  * and/or encoded
 161  */
 162 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 163                                        size_t rbf_size)
 164 {
 165         unsigned int cd_ratio;
 166         bool encrypt, compress;
 167
 168         /*
 169          * According to the bitstream specification,
 170          * both encryption and compression status are
 171          * in location before offset 230 of the buffer.
 172          */
 173         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 174                 return -EINVAL;
 175
 176         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 177         encrypt = encrypt != 0;
 178
 179         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 180         compress = !compress;
 181
 182         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 183         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 184         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 185              compress);
 186
 187         /*
 188          * from the register map description of cdratio in imgcfg_ctrl_02:
 189          *  Normal Configuration    : 32bit Passive Parallel
 190          *  Partial Reconfiguration : 16bit Passive Parallel
 191          */
 192
 193         /*
 194          * cd ratio is dependent on cfg width and whether the bitstream
 195          * is encrypted and/or compressed.
 196          *
 197          * | width | encr. | compr. | cd ratio |
 198          * |  16   |   0   |   0    |     1    |
 199          * |  16   |   0   |   1    |     4    |
 200          * |  16   |   1   |   0    |     2    |
 201          * |  16   |   1   |   1    |     4    |
 202          * |  32   |   0   |   0    |     1    |
 203          * |  32   |   0   |   1    |     8    |
 204          * |  32   |   1   |   0    |     4    |
 205          * |  32   |   1   |   1    |     8    |
 206          */
 207         if (!compress && !encrypt) {
 208                 cd_ratio = CDRATIO_x1;
 209         } else {
 210                 if (compress)
 211                         cd_ratio = CDRATIO_x4;
 212                 else
 213                         cd_ratio = CDRATIO_x2;
 214
 215                 /* if 32 bit, double the cd ratio (so register
 216                    field setting is incremented) */
 217                 if (cfg_width == CFGWDTH_32)
 218                         cd_ratio += 1;
 219         }
 220
 221         fpgamgr_set_cfgwdth(cfg_width);
 222         fpgamgr_set_cd_ratio(cd_ratio);
 223
 224         return 0;
 225 }
 226
 227 static int fpgamgr_reset(void)
 228 {
 229         unsigned long reg;
 230
 231         /* S2F_NCONFIG = 0 */
 232         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 233                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 234
 235         /* Wait for f2s_nstatus == 0 */
 236         if (wait_for_f2s_nstatus_pin(0))
 237                 return -ETIME;
 238
 239         /* S2F_NCONFIG = 1 */
 240         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 241                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 242
 243         /* Wait for f2s_nstatus == 1 */
 244         if (wait_for_f2s_nstatus_pin(1))
 245                 return -ETIME;
 246
 247         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 248         reg = readl(&fpga_manager_base->imgcfg_stat);
 249         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 250                 return -EPERM;
 251
 252         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 253                 return -EPERM;
 254
 255         return 0;
 256 }
 257
 258 /* Start the FPGA programming by initialize the FPGA Manager */
 259 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 260 {
 261         int ret;
 262
 263         /* Step 1 */
 264         if (fpgamgr_verify_msel())
 265                 return -EPERM;
 266
 267         /* Step 2 */
 268         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 269                 return -EPERM;
 270
 271         /*
 272          * Step 3:
 273          * Make sure no other external devices are trying to interfere with
 274          * programming:
 275          */
 276         if (wait_for_nconfig_pin_and_nstatus_pin())
 277                 return -ETIME;
 278
 279         /*
 280          * Step 4:
 281          * Deassert the signal drives from HPS
 282          *
 283          * S2F_NCE = 1
 284          * S2F_PR_REQUEST = 0
 285          * EN_CFG_CTRL = 0
 286          * EN_CFG_DATA = 0
 287          * S2F_NCONFIG = 1
 288          * S2F_NSTATUS_OE = 0
 289          * S2F_CONDONE_OE = 0
 290          */
 291         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 292                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 293
 294         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 295                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 296
 297         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 298                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 299                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 300
 301         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 302                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 303
 304         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 305                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 306                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 307
 308         /*
 309          * Step 5:
 310          * Enable overrides
 311          * S2F_NENABLE_CONFIG = 0
 312          * S2F_NENABLE_NCONFIG = 0
 313          */
 314         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 315                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 316         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 317                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 318
 319         /*
 320          * Disable driving signals that HPS doesn't need to drive.
 321          * S2F_NENABLE_NSTATUS = 1
 322          * S2F_NENABLE_CONDONE = 1
 323          */
 324         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 325                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 326                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 327
 328         /*
 329          * Step 6:
 330          * Drive chip select S2F_NCE = 0
 331          */
 332          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 333                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 334
 335         /* Step 7 */
 336         if (wait_for_nconfig_pin_and_nstatus_pin())
 337                 return -ETIME;
 338
 339         /* Step 8 */
 340         ret = fpgamgr_reset();
 341
 342         if (ret)
 343                 return ret;
 344
 345         /*
 346          * Step 9:
 347          * EN_CFG_CTRL and EN_CFG_DATA = 1
 348          */
 349         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 350                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 351                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 352
 353         return 0;
 354 }
 355
 356 /* Ensure the FPGA entering config done */
 357 static int fpgamgr_program_poll_cd(void)
 358 {
 359         unsigned long reg, i;
 360
 361         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 362                 reg = readl(&fpga_manager_base->imgcfg_stat);
 363                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 364                         return 0;
 365
 366                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 367                         printf("nstatus == 0 while waiting for condone\n");
 368                         return -EPERM;
 369                 }
 370                 WATCHDOG_RESET();
 371         }
 372
 373         if (i == FPGA_TIMEOUT_CNT)
 374                 return -ETIME;
 375
 376         return 0;
 377 }
 378
 379 /* Ensure the FPGA entering user mode */
 380 static int fpgamgr_program_poll_usermode(void)
 381 {
 382         unsigned long reg;
 383         int ret = 0;
 384
 385         if (fpgamgr_dclkcnt_set(0xf))
 386                 return -ETIME;
 387
 388         ret = wait_for_user_mode();
 389         if (ret < 0) {
 390                 printf("%s: Failed to enter user mode with ", __func__);
 391                 printf("error code %d\n", ret);
 392                 return ret;
 393         }
 394
 395         /*
 396          * Step 14:
 397          * Stop DATA path and Dclk
 398          * EN_CFG_CTRL and EN_CFG_DATA = 0
 399          */
 400         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 401                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 402                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 403
 404         /*
 405          * Step 15:
 406          * Disable overrides
 407          * S2F_NENABLE_CONFIG = 1
 408          * S2F_NENABLE_NCONFIG = 1
 409          */
 410         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 411                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 412         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 413                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 414
 415         /* Disable chip select S2F_NCE = 1 */
 416         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 417                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 418
 419         /*
 420          * Step 16:
 421          * Final check
 422          */
 423         reg = readl(&fpga_manager_base->imgcfg_stat);
 424         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 425                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 426             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 427                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 428             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 429                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 430                 return -EPERM;
 431
 432         return 0;
 433 }
 434
 435 int fpgamgr_program_finish(void)
 436 {
 437         /* Ensure the FPGA entering config done */
 438         int status = fpgamgr_program_poll_cd();
 439
 440         if (status) {
 441                 printf("FPGA: Poll CD failed with error code %d\n", status);
 442                 return -EPERM;
 443         }
 444
 445         /* Ensure the FPGA entering user mode */
 446         status = fpgamgr_program_poll_usermode();
 447         if (status) {
 448                 printf("FPGA: Poll usermode failed with error code %d\n",
 449                         status);
 450                 return -EPERM;
 451         }
 452
 453         printf("Full Configuration Succeeded.\n");
 454
 455         return 0;
 456 }
 457
 458 ofnode get_fpga_mgr_ofnode(ofnode from)
 459 {
 460         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 461 }
 462
 463 const char *get_fpga_filename(void)
 464 {
 465         const char *fpga_filename = NULL;
 466
 467         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 468
 469         if (ofnode_valid(fpgamgr_node))
 470                 fpga_filename = ofnode_read_string(fpgamgr_node,
 471                                                 "altr,bitstream");
 472
 473         return fpga_filename;
 474 }
 475
 476 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 477 {
 478         /*
 479          * Magic ID starting at:
 480          * -> 1st dword[15:0] in periph.rbf
 481          * -> 2nd dword[15:0] in core.rbf
 482          * Note: dword == 32 bits
 483          */
 484         u32 word_reading_max = 2;
 485         u32 i;
 486
 487         for (i = 0; i < word_reading_max; i++) {
 488                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 489                         rbf->security = unencrypted;
 490                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 491                         rbf->security = encrypted;
 492                 } else if (*(buffer + i + 1) ==
 493                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 494                         rbf->security = unencrypted;
 495                 } else if (*(buffer + i + 1) ==
 496                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 497                         rbf->security = encrypted;
 498                 } else {
 499                         rbf->security = invalid;
 500                         continue;
 501                 }
 502
 503                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 504                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 505                         rbf->section = periph_section;
 506                         break;
 507                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 508                         rbf->section = core_section;
 509                         break;
 510                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 511                         rbf->section = periph_section;
 512                         break;
 513                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 514                         rbf->section = core_section;
 515                         break;
 516                 }
 517
 518                 rbf->section = unknown;
 519                 break;
 520
 521                 WATCHDOG_RESET();
 522         }
 523 }
 524
 525 #ifdef CONFIG_FS_LOADER
 526 static int first_loading_rbf_to_buffer(struct udevice *dev,
 527                                 struct fpga_loadfs_info *fpga_loadfs,
 528                                 u32 *buffer, size_t *buffer_bsize)
 529 {
 530         u32 *buffer_p = (u32 *)*buffer;
 531         u32 *loadable = buffer_p;
 532         size_t buffer_size = *buffer_bsize;
 533         size_t fit_size;
 534         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 535         const char *fpga_node_name = NULL;
 536         const char *uname = NULL;
 537
 538         /* Load image header into buffer */
 539         ret = request_firmware_into_buf(dev,
 540                                         fpga_loadfs->fpga_fsinfo->filename,
 541                                         buffer_p, sizeof(struct image_header),
 542                                         0);
 543         if (ret < 0) {
 544                 debug("FPGA: Failed to read image header from flash.\n");
 545                 return -ENOENT;
 546         }
 547
 548         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 549                 debug("FPGA: No FDT magic was found.\n");
 550                 return -EBADF;
 551         }
 552
 553         fit_size = fdt_totalsize(buffer_p);
 554
 555         if (fit_size > buffer_size) {
 556                 debug("FPGA: FIT image is larger than available buffer.\n");
 557                 debug("Please use FIT external data or increasing buffer.\n");
 558                 return -ENOMEM;
 559         }
 560
 561         /* Load entire FIT into buffer */
 562         ret = request_firmware_into_buf(dev,
 563                                         fpga_loadfs->fpga_fsinfo->filename,
 564                                         buffer_p, fit_size, 0);
 565         if (ret < 0)
 566                 return ret;
 567
 568         ret = fit_check_format(buffer_p);
 569         if (!ret) {
 570                 debug("FPGA: No valid FIT image was found.\n");
 571                 return -EBADF;
 572         }
 573
 574         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 575         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 576         if (confs_noffset < 0 || images_noffset < 0) {
 577                 debug("FPGA: No Configurations or images nodes were found.\n");
 578                 return -ENOENT;
 579         }
 580
 581         /* Get default configuration unit name from default property */
 582         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 583         if (confs_noffset < 0) {
 584                 debug("FPGA: No default configuration was found in config.\n");
 585                 return -ENOENT;
 586         }
 587
 588         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 589                                             FIT_FPGA_PROP);
 590         if (count < 0) {
 591                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 592                 return count;
 593         }
 594         debug("FPGA: FPGA node count: %d\n", count);
 595
 596         for (i = 0; i < count; i++) {
 597                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 598                                                              confs_noffset,
 599                                                              FIT_FPGA_PROP, i);
 600                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 601                 if (uname) {
 602                         debug("FPGA: %s\n", uname);
 603
 604                         if (strstr(uname, "fpga-periph") &&
 605                                 (!is_fpgamgr_early_user_mode() ||
 606                                 is_fpgamgr_user_mode())) {
 607                                 fpga_node_name = uname;
 608                                 printf("FPGA: Start to program ");
 609                                 printf("peripheral/full bitstream ...\n");
 610                                 break;
 611                         } else if (strstr(uname, "fpga-core") &&
 612                                         (is_fpgamgr_early_user_mode() &&
 613                                         !is_fpgamgr_user_mode())) {
 614                                 fpga_node_name = uname;
 615                                 printf("FPGA: Start to program core ");
 616                                 printf("bitstream ...\n");
 617                                 break;
 618                         }
 619                 }
 620                 WATCHDOG_RESET();
 621         }
 622
 623         if (!fpga_node_name) {
 624                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 625                 return 1;
 626         }
 627
 628         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 629         if (images_noffset < 0) {
 630                 debug("FPGA: No node '%s' was found in FIT.\n",
 631                      fpga_node_name);
 632                 return -ENOENT;
 633         }
 634
 635         if (!fit_image_get_data_position(buffer_p, images_noffset,
 636                                         &rbf_offset)) {
 637                 debug("FPGA: Data position was found.\n");
 638         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 639                   &rbf_offset)) {
 640                 /*
 641                  * For FIT with external data, figure out where
 642                  * the external images start. This is the base
 643                  * for the data-offset properties in each image.
 644                  */
 645                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 646                 debug("FPGA: Data offset was found.\n");
 647         } else {
 648                 debug("FPGA: No data position/offset was found.\n");
 649                 return -ENOENT;
 650         }
 651
 652         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 653         if (ret < 0) {
 654                 debug("FPGA: No data size was found (err=%d).\n", ret);
 655                 return -ENOENT;
 656         }
 657
 658         if (gd->ram_size < rbf_size) {
 659                 debug("FPGA: Using default OCRAM buffer and size.\n");
 660         } else {
 661                 ret = fit_image_get_load(buffer_p, images_noffset,
 662                                         (ulong *)loadable);
 663                 if (ret < 0) {
 664                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 665                         debug("FPGA: No loadable was found.\n");
 666                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 667                              DEFAULT_DDR_LOAD_ADDRESS);
 668                 } else {
 669                         buffer_p = (u32 *)*loadable;
 670                         debug("FPGA: Found loadable address = 0x%x.\n",
 671                              *loadable);
 672                 }
 673
 674                 buffer_size = rbf_size;
 675         }
 676
 677         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 678               rbf_offset, rbf_size);
 679
 680         fpga_loadfs->remaining = rbf_size;
 681
 682         /*
 683          * Determine buffer size vs bitstream size, and calculating number of
 684          * chunk by chunk transfer is required due to smaller buffer size
 685          * compare to bitstream
 686          */
 687         if (rbf_size <= buffer_size) {
 688                 /* Loading whole bitstream into buffer */
 689                 buffer_size = rbf_size;
 690                 fpga_loadfs->remaining = 0;
 691         } else {
 692                 fpga_loadfs->remaining -= buffer_size;
 693         }
 694
 695         fpga_loadfs->offset = rbf_offset;
 696         /* Loading bitstream into buffer */
 697         ret = request_firmware_into_buf(dev,
 698                                         fpga_loadfs->fpga_fsinfo->filename,
 699                                         buffer_p, buffer_size,
 700                                         fpga_loadfs->offset);
 701         if (ret < 0) {
 702                 debug("FPGA: Failed to read bitstream from flash.\n");
 703                 return -ENOENT;
 704         }
 705
 706         /* Getting info about bitstream types */
 707         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 708
 709         /* Update next reading bitstream offset */
 710         fpga_loadfs->offset += buffer_size;
 711
 712         /* Update the final addr for bitstream */
 713         *buffer = (u32)buffer_p;
 714
 715         /* Update the size of bitstream to be programmed into FPGA */
 716         *buffer_bsize = buffer_size;
 717
 718         return 0;
 719 }
 720
 721 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 722                                         struct fpga_loadfs_info *fpga_loadfs,
 723                                         u32 *buffer, size_t *buffer_bsize)
 724 {
 725         int ret = 0;
 726         u32 *buffer_p = (u32 *)*buffer;
 727
 728         /* Read the bitstream chunk by chunk. */
 729         if (fpga_loadfs->remaining > *buffer_bsize) {
 730                 fpga_loadfs->remaining -= *buffer_bsize;
 731         } else {
 732                 *buffer_bsize = fpga_loadfs->remaining;
 733                 fpga_loadfs->remaining = 0;
 734         }
 735
 736         ret = request_firmware_into_buf(dev,
 737                                         fpga_loadfs->fpga_fsinfo->filename,
 738                                         buffer_p, *buffer_bsize,
 739                                         fpga_loadfs->offset);
 740         if (ret < 0) {
 741                 debug("FPGA: Failed to read bitstream from flash.\n");
 742                 return -ENOENT;
 743         }
 744
 745         /* Update next reading bitstream offset */
 746         fpga_loadfs->offset += *buffer_bsize;
 747
 748         return 0;
 749 }
 750
 751 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 752                         u32 offset)
 753 {
 754         struct fpga_loadfs_info fpga_loadfs;
 755         struct udevice *dev;
 756         int status, ret, size;
 757         u32 buffer = (uintptr_t)buf;
 758         size_t buffer_sizebytes = bsize;
 759         size_t buffer_sizebytes_ori = bsize;
 760         size_t total_sizeof_image = 0;
 761         ofnode node;
 762         const fdt32_t *phandle_p;
 763         u32 phandle;
 764
 765         node = get_fpga_mgr_ofnode(ofnode_null());
 766
 767         if (ofnode_valid(node)) {
 768                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 769                 if (!phandle_p) {
 770                         node = ofnode_path("/chosen");
 771                         if (!ofnode_valid(node)) {
 772                                 debug("FPGA: /chosen node was not found.\n");
 773                                 return -ENOENT;
 774                         }
 775
 776                         phandle_p = ofnode_get_property(node, "firmware-loader",
 777                                                        &size);
 778                         if (!phandle_p) {
 779                                 debug("FPGA: firmware-loader property was not");
 780                                 debug(" found.\n");
 781                                 return -ENOENT;
 782                         }
 783                 }
 784         } else {
 785                 debug("FPGA: FPGA manager node was not found.\n");
 786                 return -ENOENT;
 787         }
 788
 789         phandle = fdt32_to_cpu(*phandle_p);
 790         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 791                                              phandle, &dev);
 792         if (ret)
 793                 return ret;
 794
 795         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 796
 797         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 798         fpga_loadfs.offset = offset;
 799
 800         printf("FPGA: Checking FPGA configuration setting ...\n");
 801
 802         /*
 803          * Note: Both buffer and buffer_sizebytes values can be altered by
 804          * function below.
 805          */
 806         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 807                                            &buffer_sizebytes);
 808         if (ret == 1) {
 809                 printf("FPGA: Skipping configuration ...\n");
 810                 return 0;
 811         } else if (ret) {
 812                 return ret;
 813         }
 814
 815         if (fpga_loadfs.rbfinfo.section == core_section &&
 816                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 817                 debug("FPGA : Must be in Early Release mode to program ");
 818                 debug("core bitstream.\n");
 819                 return -EPERM;
 820         }
 821
 822         /* Disable all signals from HPS peripheral controller to FPGA */
 823         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 824
 825         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 826         socfpga_bridges_reset();
 827
 828         if (fpga_loadfs.rbfinfo.section == periph_section) {
 829                 /* Initialize the FPGA Manager */
 830                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 831                 if (status) {
 832                         debug("FPGA: Init with peripheral bitstream failed.\n");
 833                         return -EPERM;
 834                 }
 835         }
 836
 837         /* Transfer bitstream to FPGA Manager */
 838         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 839
 840         total_sizeof_image += buffer_sizebytes;
 841
 842         while (fpga_loadfs.remaining) {
 843                 ret = subsequent_loading_rbf_to_buffer(dev,
 844                                                         &fpga_loadfs,
 845                                                         &buffer,
 846                                                         &buffer_sizebytes_ori);
 847
 848                 if (ret)
 849                         return ret;
 850
 851                 /* Transfer data to FPGA Manager */
 852                 fpgamgr_program_write((void *)buffer,
 853                                         buffer_sizebytes_ori);
 854
 855                 total_sizeof_image += buffer_sizebytes_ori;
 856
 857                 WATCHDOG_RESET();
 858         }
 859
 860         if (fpga_loadfs.rbfinfo.section == periph_section) {
 861                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 862                         config_pins(gd->fdt_blob, "shared");
 863                         puts("FPGA: Early Release Succeeded.\n");
 864                 } else {
 865                         debug("FPGA: Failed to see Early Release.\n");
 866                         return -EIO;
 867                 }
 868
 869                 /* For monolithic bitstream */
 870                 if (is_fpgamgr_user_mode()) {
 871                         /* Ensure the FPGA entering config done */
 872                         status = fpgamgr_program_finish();
 873                         if (status)
 874                                 return status;
 875
 876                         config_pins(gd->fdt_blob, "fpga");
 877                         puts("FPGA: Enter user mode.\n");
 878                 }
 879         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 880                 /* Ensure the FPGA entering config done */
 881                 status = fpgamgr_program_finish();
 882                 if (status)
 883                         return status;
 884
 885                 config_pins(gd->fdt_blob, "fpga");
 886                 puts("FPGA: Enter user mode.\n");
 887         } else {
 888                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 889                 return -ENOEXEC;
 890         }
 891
 892         return (int)total_sizeof_image;
 893 }
 894
 895 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 896 {
 897         fpga_fs_info fpga_fsinfo;
 898
 899         fpga_fsinfo.filename = get_fpga_filename();
 900
 901         if (fpga_fsinfo.filename)
 902                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 903 }
 904 #endif
 905
 906 /* This function is used to load the core bitstream from the OCRAM. */
 907 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 908 {
 909         unsigned long status;
 910         struct rbf_info rbfinfo;
 911
 912         memset(&rbfinfo, 0, sizeof(rbfinfo));
 913
 914         /* Disable all signals from hps peripheral controller to fpga */
 915         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 916
 917         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 918         socfpga_bridges_reset();
 919
 920         /* Getting info about bitstream types */
 921         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 922
 923         if (rbfinfo.section == periph_section) {
 924                 /* Initialize the FPGA Manager */
 925                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 926                 if (status)
 927                         return status;
 928         }
 929
 930         if (rbfinfo.section == core_section &&
 931                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 932                 debug("FPGA : Must be in early release mode to program ");
 933                 debug("core bitstream.\n");
 934                 return -EPERM;
 935         }
 936
 937         /* Write the bitstream to FPGA Manager */
 938         fpgamgr_program_write(rbf_data, rbf_size);
 939
 940         status = fpgamgr_program_finish();
 941         if (status)
 942                 return status;
 943
 944         config_pins(gd->fdt_blob, "fpga");
 945         puts("FPGA: Enter user mode.\n");
 946
 947         return status;
 948 }