drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <asm/io.h>
   6 #include <asm/arch/fpga_manager.h>
   7 #include <asm/arch/reset_manager.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <asm/arch/sdram.h>
  10 #include <asm/arch/misc.h>
  11 #include <altera.h>
  12 #include <asm/arch/pinmux.h>
  13 #include <common.h>
  14 #include <dm/ofnode.h>
  15 #include <errno.h>
  16 #include <fs_loader.h>
  17 #include <wait_bit.h>
  18 #include <watchdog.h>
  19
  20 #define CFGWDTH_32      1
  21 #define MIN_BITSTREAM_SIZECHECK 230
  22 #define ENCRYPTION_OFFSET       69
  23 #define COMPRESSION_OFFSET      229
  24 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  25 #define FPGA_TIMEOUT_CNT        0x1000000
  26 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static const struct socfpga_fpga_manager *fpga_manager_base =
  31                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  32
  33 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  34
  35 static uint32_t fpgamgr_get_msel(void)
  36 {
  37         u32 reg;
  38
  39         reg = readl(&fpga_manager_base->imgcfg_stat);
  40         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  41                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  42
  43         return reg;
  44 }
  45
  46 static void fpgamgr_set_cfgwdth(int width)
  47 {
  48         if (width)
  49                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  50                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  51         else
  52                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  53                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  54 }
  55
  56 int is_fpgamgr_user_mode(void)
  57 {
  58         return (readl(&fpga_manager_base->imgcfg_stat) &
  59                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  60 }
  61
  62 static int wait_for_user_mode(void)
  63 {
  64         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  65                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  66                 1, FPGA_TIMEOUT_MSEC, false);
  67 }
  68
  69 int is_fpgamgr_early_user_mode(void)
  70 {
  71         return (readl(&fpga_manager_base->imgcfg_stat) &
  72                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  73 }
  74
  75 int fpgamgr_wait_early_user_mode(void)
  76 {
  77         u32 sync_data = 0xffffffff;
  78         u32 i = 0;
  79         unsigned start = get_timer(0);
  80         unsigned long cd_ratio;
  81
  82         /* Getting existing CDRATIO */
  83         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  84                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  85                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  86
  87         /* Using CDRATIO_X1 for better compatibility */
  88         fpgamgr_set_cd_ratio(CDRATIO_x1);
  89
  90         while (!is_fpgamgr_early_user_mode()) {
  91                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  92                         return -ETIMEDOUT;
  93                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  94                                 sizeof(sync_data));
  95                 udelay(FPGA_TIMEOUT_MSEC);
  96                 i++;
  97         }
  98
  99         debug("FPGA: Additional %i sync word needed\n", i);
 100
 101         /* restoring original CDRATIO */
 102         fpgamgr_set_cd_ratio(cd_ratio);
 103
 104         return 0;
 105 }
 106
 107 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 108 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 109 {
 110         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 111                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 112
 113         /*
 114          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 115          * de-asserted, timeout at 1000ms
 116          */
 117         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 118                                  true, FPGA_TIMEOUT_MSEC, false);
 119 }
 120
 121 static int wait_for_f2s_nstatus_pin(unsigned long value)
 122 {
 123         /* Poll until f2s to specific value, timeout at 1000ms */
 124         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 125                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 126                 value, FPGA_TIMEOUT_MSEC, false);
 127 }
 128
 129 /* set CD ratio */
 130 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 131 {
 132         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 133                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 134
 135         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 136                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 137                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 138 }
 139
 140 /* get the MSEL value, verify we are set for FPP configuration mode */
 141 static int fpgamgr_verify_msel(void)
 142 {
 143         u32 msel = fpgamgr_get_msel();
 144
 145         if (msel & ~BIT(0)) {
 146                 printf("Fail: read msel=%d\n", msel);
 147                 return -EPERM;
 148         }
 149
 150         return 0;
 151 }
 152
 153 /*
 154  * Write cdratio and cdwidth based on whether the bitstream is compressed
 155  * and/or encoded
 156  */
 157 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 158                                        size_t rbf_size)
 159 {
 160         unsigned int cd_ratio;
 161         bool encrypt, compress;
 162
 163         /*
 164          * According to the bitstream specification,
 165          * both encryption and compression status are
 166          * in location before offset 230 of the buffer.
 167          */
 168         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 169                 return -EINVAL;
 170
 171         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 172         encrypt = encrypt != 0;
 173
 174         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 175         compress = !compress;
 176
 177         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 178         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 179         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 180              compress);
 181
 182         /*
 183          * from the register map description of cdratio in imgcfg_ctrl_02:
 184          *  Normal Configuration    : 32bit Passive Parallel
 185          *  Partial Reconfiguration : 16bit Passive Parallel
 186          */
 187
 188         /*
 189          * cd ratio is dependent on cfg width and whether the bitstream
 190          * is encrypted and/or compressed.
 191          *
 192          * | width | encr. | compr. | cd ratio |
 193          * |  16   |   0   |   0    |     1    |
 194          * |  16   |   0   |   1    |     4    |
 195          * |  16   |   1   |   0    |     2    |
 196          * |  16   |   1   |   1    |     4    |
 197          * |  32   |   0   |   0    |     1    |
 198          * |  32   |   0   |   1    |     8    |
 199          * |  32   |   1   |   0    |     4    |
 200          * |  32   |   1   |   1    |     8    |
 201          */
 202         if (!compress && !encrypt) {
 203                 cd_ratio = CDRATIO_x1;
 204         } else {
 205                 if (compress)
 206                         cd_ratio = CDRATIO_x4;
 207                 else
 208                         cd_ratio = CDRATIO_x2;
 209
 210                 /* if 32 bit, double the cd ratio (so register
 211                    field setting is incremented) */
 212                 if (cfg_width == CFGWDTH_32)
 213                         cd_ratio += 1;
 214         }
 215
 216         fpgamgr_set_cfgwdth(cfg_width);
 217         fpgamgr_set_cd_ratio(cd_ratio);
 218
 219         return 0;
 220 }
 221
 222 static int fpgamgr_reset(void)
 223 {
 224         unsigned long reg;
 225
 226         /* S2F_NCONFIG = 0 */
 227         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 228                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 229
 230         /* Wait for f2s_nstatus == 0 */
 231         if (wait_for_f2s_nstatus_pin(0))
 232                 return -ETIME;
 233
 234         /* S2F_NCONFIG = 1 */
 235         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 236                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 237
 238         /* Wait for f2s_nstatus == 1 */
 239         if (wait_for_f2s_nstatus_pin(1))
 240                 return -ETIME;
 241
 242         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 243         reg = readl(&fpga_manager_base->imgcfg_stat);
 244         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 245                 return -EPERM;
 246
 247         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 248                 return -EPERM;
 249
 250         return 0;
 251 }
 252
 253 /* Start the FPGA programming by initialize the FPGA Manager */
 254 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 255 {
 256         int ret;
 257
 258         /* Step 1 */
 259         if (fpgamgr_verify_msel())
 260                 return -EPERM;
 261
 262         /* Step 2 */
 263         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 264                 return -EPERM;
 265
 266         /*
 267          * Step 3:
 268          * Make sure no other external devices are trying to interfere with
 269          * programming:
 270          */
 271         if (wait_for_nconfig_pin_and_nstatus_pin())
 272                 return -ETIME;
 273
 274         /*
 275          * Step 4:
 276          * Deassert the signal drives from HPS
 277          *
 278          * S2F_NCE = 1
 279          * S2F_PR_REQUEST = 0
 280          * EN_CFG_CTRL = 0
 281          * EN_CFG_DATA = 0
 282          * S2F_NCONFIG = 1
 283          * S2F_NSTATUS_OE = 0
 284          * S2F_CONDONE_OE = 0
 285          */
 286         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 287                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 288
 289         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 290                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 291
 292         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 293                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 294                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 295
 296         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 297                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 298
 299         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 300                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 301                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 302
 303         /*
 304          * Step 5:
 305          * Enable overrides
 306          * S2F_NENABLE_CONFIG = 0
 307          * S2F_NENABLE_NCONFIG = 0
 308          */
 309         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 310                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 311         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 312                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 313
 314         /*
 315          * Disable driving signals that HPS doesn't need to drive.
 316          * S2F_NENABLE_NSTATUS = 1
 317          * S2F_NENABLE_CONDONE = 1
 318          */
 319         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 320                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 321                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 322
 323         /*
 324          * Step 6:
 325          * Drive chip select S2F_NCE = 0
 326          */
 327          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 328                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 329
 330         /* Step 7 */
 331         if (wait_for_nconfig_pin_and_nstatus_pin())
 332                 return -ETIME;
 333
 334         /* Step 8 */
 335         ret = fpgamgr_reset();
 336
 337         if (ret)
 338                 return ret;
 339
 340         /*
 341          * Step 9:
 342          * EN_CFG_CTRL and EN_CFG_DATA = 1
 343          */
 344         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 345                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 346                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 347
 348         return 0;
 349 }
 350
 351 /* Ensure the FPGA entering config done */
 352 static int fpgamgr_program_poll_cd(void)
 353 {
 354         unsigned long reg, i;
 355
 356         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 357                 reg = readl(&fpga_manager_base->imgcfg_stat);
 358                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 359                         return 0;
 360
 361                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 362                         printf("nstatus == 0 while waiting for condone\n");
 363                         return -EPERM;
 364                 }
 365                 WATCHDOG_RESET();
 366         }
 367
 368         if (i == FPGA_TIMEOUT_CNT)
 369                 return -ETIME;
 370
 371         return 0;
 372 }
 373
 374 /* Ensure the FPGA entering user mode */
 375 static int fpgamgr_program_poll_usermode(void)
 376 {
 377         unsigned long reg;
 378         int ret = 0;
 379
 380         if (fpgamgr_dclkcnt_set(0xf))
 381                 return -ETIME;
 382
 383         ret = wait_for_user_mode();
 384         if (ret < 0) {
 385                 printf("%s: Failed to enter user mode with ", __func__);
 386                 printf("error code %d\n", ret);
 387                 return ret;
 388         }
 389
 390         /*
 391          * Step 14:
 392          * Stop DATA path and Dclk
 393          * EN_CFG_CTRL and EN_CFG_DATA = 0
 394          */
 395         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 396                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 397                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 398
 399         /*
 400          * Step 15:
 401          * Disable overrides
 402          * S2F_NENABLE_CONFIG = 1
 403          * S2F_NENABLE_NCONFIG = 1
 404          */
 405         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 406                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 407         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 408                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 409
 410         /* Disable chip select S2F_NCE = 1 */
 411         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 412                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 413
 414         /*
 415          * Step 16:
 416          * Final check
 417          */
 418         reg = readl(&fpga_manager_base->imgcfg_stat);
 419         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 420                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 421             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 422                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 423             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 424                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 425                 return -EPERM;
 426
 427         return 0;
 428 }
 429
 430 int fpgamgr_program_finish(void)
 431 {
 432         /* Ensure the FPGA entering config done */
 433         int status = fpgamgr_program_poll_cd();
 434
 435         if (status) {
 436                 printf("FPGA: Poll CD failed with error code %d\n", status);
 437                 return -EPERM;
 438         }
 439
 440         /* Ensure the FPGA entering user mode */
 441         status = fpgamgr_program_poll_usermode();
 442         if (status) {
 443                 printf("FPGA: Poll usermode failed with error code %d\n",
 444                         status);
 445                 return -EPERM;
 446         }
 447
 448         printf("Full Configuration Succeeded.\n");
 449
 450         return 0;
 451 }
 452
 453 ofnode get_fpga_mgr_ofnode(ofnode from)
 454 {
 455         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 456 }
 457
 458 const char *get_fpga_filename(void)
 459 {
 460         const char *fpga_filename = NULL;
 461
 462         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 463
 464         if (ofnode_valid(fpgamgr_node))
 465                 fpga_filename = ofnode_read_string(fpgamgr_node,
 466                                                 "altr,bitstream");
 467
 468         return fpga_filename;
 469 }
 470
 471 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 472 {
 473         /*
 474          * Magic ID starting at:
 475          * -> 1st dword[15:0] in periph.rbf
 476          * -> 2nd dword[15:0] in core.rbf
 477          * Note: dword == 32 bits
 478          */
 479         u32 word_reading_max = 2;
 480         u32 i;
 481
 482         for (i = 0; i < word_reading_max; i++) {
 483                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 484                         rbf->security = unencrypted;
 485                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 486                         rbf->security = encrypted;
 487                 } else if (*(buffer + i + 1) ==
 488                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 489                         rbf->security = unencrypted;
 490                 } else if (*(buffer + i + 1) ==
 491                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 492                         rbf->security = encrypted;
 493                 } else {
 494                         rbf->security = invalid;
 495                         continue;
 496                 }
 497
 498                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 499                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 500                         rbf->section = periph_section;
 501                         break;
 502                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 503                         rbf->section = core_section;
 504                         break;
 505                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 506                         rbf->section = periph_section;
 507                         break;
 508                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 509                         rbf->section = core_section;
 510                         break;
 511                 }
 512
 513                 rbf->section = unknown;
 514                 break;
 515
 516                 WATCHDOG_RESET();
 517         }
 518 }
 519
 520 #ifdef CONFIG_FS_LOADER
 521 static int first_loading_rbf_to_buffer(struct udevice *dev,
 522                                 struct fpga_loadfs_info *fpga_loadfs,
 523                                 u32 *buffer, size_t *buffer_bsize)
 524 {
 525         u32 *buffer_p = (u32 *)*buffer;
 526         u32 *loadable = buffer_p;
 527         size_t buffer_size = *buffer_bsize;
 528         size_t fit_size;
 529         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 530         const char *fpga_node_name = NULL;
 531         const char *uname = NULL;
 532
 533         /* Load image header into buffer */
 534         ret = request_firmware_into_buf(dev,
 535                                         fpga_loadfs->fpga_fsinfo->filename,
 536                                         buffer_p, sizeof(struct image_header),
 537                                         0);
 538         if (ret < 0) {
 539                 debug("FPGA: Failed to read image header from flash.\n");
 540                 return -ENOENT;
 541         }
 542
 543         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 544                 debug("FPGA: No FDT magic was found.\n");
 545                 return -EBADF;
 546         }
 547
 548         fit_size = fdt_totalsize(buffer_p);
 549
 550         if (fit_size > buffer_size) {
 551                 debug("FPGA: FIT image is larger than available buffer.\n");
 552                 debug("Please use FIT external data or increasing buffer.\n");
 553                 return -ENOMEM;
 554         }
 555
 556         /* Load entire FIT into buffer */
 557         ret = request_firmware_into_buf(dev,
 558                                         fpga_loadfs->fpga_fsinfo->filename,
 559                                         buffer_p, fit_size, 0);
 560         if (ret < 0)
 561                 return ret;
 562
 563         ret = fit_check_format(buffer_p);
 564         if (!ret) {
 565                 debug("FPGA: No valid FIT image was found.\n");
 566                 return -EBADF;
 567         }
 568
 569         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 570         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 571         if (confs_noffset < 0 || images_noffset < 0) {
 572                 debug("FPGA: No Configurations or images nodes were found.\n");
 573                 return -ENOENT;
 574         }
 575
 576         /* Get default configuration unit name from default property */
 577         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 578         if (confs_noffset < 0) {
 579                 debug("FPGA: No default configuration was found in config.\n");
 580                 return -ENOENT;
 581         }
 582
 583         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 584                                             FIT_FPGA_PROP);
 585         if (count < 0) {
 586                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 587                 return count;
 588         }
 589         debug("FPGA: FPGA node count: %d\n", count);
 590
 591         for (i = 0; i < count; i++) {
 592                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 593                                                              confs_noffset,
 594                                                              FIT_FPGA_PROP, i);
 595                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 596                 if (uname) {
 597                         debug("FPGA: %s\n", uname);
 598
 599                         if (strstr(uname, "fpga-periph") &&
 600                                 (!is_fpgamgr_early_user_mode() ||
 601                                 is_fpgamgr_user_mode())) {
 602                                 fpga_node_name = uname;
 603                                 printf("FPGA: Start to program ");
 604                                 printf("peripheral/full bitstream ...\n");
 605                                 break;
 606                         } else if (strstr(uname, "fpga-core") &&
 607                                         (is_fpgamgr_early_user_mode() &&
 608                                         !is_fpgamgr_user_mode())) {
 609                                 fpga_node_name = uname;
 610                                 printf("FPGA: Start to program core ");
 611                                 printf("bitstream ...\n");
 612                                 break;
 613                         }
 614                 }
 615                 WATCHDOG_RESET();
 616         }
 617
 618         if (!fpga_node_name) {
 619                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 620                 return 1;
 621         }
 622
 623         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 624         if (images_noffset < 0) {
 625                 debug("FPGA: No node '%s' was found in FIT.\n",
 626                      fpga_node_name);
 627                 return -ENOENT;
 628         }
 629
 630         if (!fit_image_get_data_position(buffer_p, images_noffset,
 631                                         &rbf_offset)) {
 632                 debug("FPGA: Data position was found.\n");
 633         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 634                   &rbf_offset)) {
 635                 /*
 636                  * For FIT with external data, figure out where
 637                  * the external images start. This is the base
 638                  * for the data-offset properties in each image.
 639                  */
 640                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 641                 debug("FPGA: Data offset was found.\n");
 642         } else {
 643                 debug("FPGA: No data position/offset was found.\n");
 644                 return -ENOENT;
 645         }
 646
 647         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 648         if (ret < 0) {
 649                 debug("FPGA: No data size was found (err=%d).\n", ret);
 650                 return -ENOENT;
 651         }
 652
 653         if (gd->ram_size < rbf_size) {
 654                 debug("FPGA: Using default OCRAM buffer and size.\n");
 655         } else {
 656                 ret = fit_image_get_load(buffer_p, images_noffset,
 657                                         (ulong *)loadable);
 658                 if (ret < 0) {
 659                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 660                         debug("FPGA: No loadable was found.\n");
 661                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 662                              DEFAULT_DDR_LOAD_ADDRESS);
 663                 } else {
 664                         buffer_p = (u32 *)*loadable;
 665                         debug("FPGA: Found loadable address = 0x%x.\n",
 666                              *loadable);
 667                 }
 668
 669                 buffer_size = rbf_size;
 670         }
 671
 672         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 673               rbf_offset, rbf_size);
 674
 675         fpga_loadfs->remaining = rbf_size;
 676
 677         /*
 678          * Determine buffer size vs bitstream size, and calculating number of
 679          * chunk by chunk transfer is required due to smaller buffer size
 680          * compare to bitstream
 681          */
 682         if (rbf_size <= buffer_size) {
 683                 /* Loading whole bitstream into buffer */
 684                 buffer_size = rbf_size;
 685                 fpga_loadfs->remaining = 0;
 686         } else {
 687                 fpga_loadfs->remaining -= buffer_size;
 688         }
 689
 690         fpga_loadfs->offset = rbf_offset;
 691         /* Loading bitstream into buffer */
 692         ret = request_firmware_into_buf(dev,
 693                                         fpga_loadfs->fpga_fsinfo->filename,
 694                                         buffer_p, buffer_size,
 695                                         fpga_loadfs->offset);
 696         if (ret < 0) {
 697                 debug("FPGA: Failed to read bitstream from flash.\n");
 698                 return -ENOENT;
 699         }
 700
 701         /* Getting info about bitstream types */
 702         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 703
 704         /* Update next reading bitstream offset */
 705         fpga_loadfs->offset += buffer_size;
 706
 707         /* Update the final addr for bitstream */
 708         *buffer = (u32)buffer_p;
 709
 710         /* Update the size of bitstream to be programmed into FPGA */
 711         *buffer_bsize = buffer_size;
 712
 713         return 0;
 714 }
 715
 716 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 717                                         struct fpga_loadfs_info *fpga_loadfs,
 718                                         u32 *buffer, size_t *buffer_bsize)
 719 {
 720         int ret = 0;
 721         u32 *buffer_p = (u32 *)*buffer;
 722
 723         /* Read the bitstream chunk by chunk. */
 724         if (fpga_loadfs->remaining > *buffer_bsize) {
 725                 fpga_loadfs->remaining -= *buffer_bsize;
 726         } else {
 727                 *buffer_bsize = fpga_loadfs->remaining;
 728                 fpga_loadfs->remaining = 0;
 729         }
 730
 731         ret = request_firmware_into_buf(dev,
 732                                         fpga_loadfs->fpga_fsinfo->filename,
 733                                         buffer_p, *buffer_bsize,
 734                                         fpga_loadfs->offset);
 735         if (ret < 0) {
 736                 debug("FPGA: Failed to read bitstream from flash.\n");
 737                 return -ENOENT;
 738         }
 739
 740         /* Update next reading bitstream offset */
 741         fpga_loadfs->offset += *buffer_bsize;
 742
 743         return 0;
 744 }
 745
 746 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 747                         u32 offset)
 748 {
 749         struct fpga_loadfs_info fpga_loadfs;
 750         struct udevice *dev;
 751         int status, ret, size;
 752         u32 buffer = (uintptr_t)buf;
 753         size_t buffer_sizebytes = bsize;
 754         size_t buffer_sizebytes_ori = bsize;
 755         size_t total_sizeof_image = 0;
 756         ofnode node;
 757         const fdt32_t *phandle_p;
 758         u32 phandle;
 759
 760         node = get_fpga_mgr_ofnode(ofnode_null());
 761
 762         if (ofnode_valid(node)) {
 763                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 764                 if (!phandle_p) {
 765                         node = ofnode_path("/chosen");
 766                         if (!ofnode_valid(node)) {
 767                                 debug("FPGA: /chosen node was not found.\n");
 768                                 return -ENOENT;
 769                         }
 770
 771                         phandle_p = ofnode_get_property(node, "firmware-loader",
 772                                                        &size);
 773                         if (!phandle_p) {
 774                                 debug("FPGA: firmware-loader property was not");
 775                                 debug(" found.\n");
 776                                 return -ENOENT;
 777                         }
 778                 }
 779         } else {
 780                 debug("FPGA: FPGA manager node was not found.\n");
 781                 return -ENOENT;
 782         }
 783
 784         phandle = fdt32_to_cpu(*phandle_p);
 785         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 786                                              phandle, &dev);
 787         if (ret)
 788                 return ret;
 789
 790         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 791
 792         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 793         fpga_loadfs.offset = offset;
 794
 795         printf("FPGA: Checking FPGA configuration setting ...\n");
 796
 797         /*
 798          * Note: Both buffer and buffer_sizebytes values can be altered by
 799          * function below.
 800          */
 801         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 802                                            &buffer_sizebytes);
 803         if (ret == 1) {
 804                 printf("FPGA: Skipping configuration ...\n");
 805                 return 0;
 806         } else if (ret) {
 807                 return ret;
 808         }
 809
 810         if (fpga_loadfs.rbfinfo.section == core_section &&
 811                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 812                 debug("FPGA : Must be in Early Release mode to program ");
 813                 debug("core bitstream.\n");
 814                 return -EPERM;
 815         }
 816
 817         /* Disable all signals from HPS peripheral controller to FPGA */
 818         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 819
 820         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 821         socfpga_bridges_reset();
 822
 823         if (fpga_loadfs.rbfinfo.section == periph_section) {
 824                 /* Initialize the FPGA Manager */
 825                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 826                 if (status) {
 827                         debug("FPGA: Init with peripheral bitstream failed.\n");
 828                         return -EPERM;
 829                 }
 830         }
 831
 832         /* Transfer bitstream to FPGA Manager */
 833         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 834
 835         total_sizeof_image += buffer_sizebytes;
 836
 837         while (fpga_loadfs.remaining) {
 838                 ret = subsequent_loading_rbf_to_buffer(dev,
 839                                                         &fpga_loadfs,
 840                                                         &buffer,
 841                                                         &buffer_sizebytes_ori);
 842
 843                 if (ret)
 844                         return ret;
 845
 846                 /* Transfer data to FPGA Manager */
 847                 fpgamgr_program_write((void *)buffer,
 848                                         buffer_sizebytes_ori);
 849
 850                 total_sizeof_image += buffer_sizebytes_ori;
 851
 852                 WATCHDOG_RESET();
 853         }
 854
 855         if (fpga_loadfs.rbfinfo.section == periph_section) {
 856                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 857                         config_pins(gd->fdt_blob, "shared");
 858                         puts("FPGA: Early Release Succeeded.\n");
 859                 } else {
 860                         debug("FPGA: Failed to see Early Release.\n");
 861                         return -EIO;
 862                 }
 863
 864                 /* For monolithic bitstream */
 865                 if (is_fpgamgr_user_mode()) {
 866                         /* Ensure the FPGA entering config done */
 867                         status = fpgamgr_program_finish();
 868                         if (status)
 869                                 return status;
 870
 871                         config_pins(gd->fdt_blob, "fpga");
 872                         puts("FPGA: Enter user mode.\n");
 873                 }
 874         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 875                 /* Ensure the FPGA entering config done */
 876                 status = fpgamgr_program_finish();
 877                 if (status)
 878                         return status;
 879
 880                 config_pins(gd->fdt_blob, "fpga");
 881                 puts("FPGA: Enter user mode.\n");
 882         } else {
 883                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 884                 return -ENOEXEC;
 885         }
 886
 887         return (int)total_sizeof_image;
 888 }
 889
 890 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 891 {
 892         fpga_fs_info fpga_fsinfo;
 893
 894         fpga_fsinfo.filename = get_fpga_filename();
 895
 896         if (fpga_fsinfo.filename)
 897                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 898 }
 899 #endif
 900
 901 /* This function is used to load the core bitstream from the OCRAM. */
 902 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 903 {
 904         unsigned long status;
 905         struct rbf_info rbfinfo;
 906
 907         memset(&rbfinfo, 0, sizeof(rbfinfo));
 908
 909         /* Disable all signals from hps peripheral controller to fpga */
 910         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 911
 912         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 913         socfpga_bridges_reset();
 914
 915         /* Getting info about bitstream types */
 916         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 917
 918         if (rbfinfo.section == periph_section) {
 919                 /* Initialize the FPGA Manager */
 920                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 921                 if (status)
 922                         return status;
 923         }
 924
 925         if (rbfinfo.section == core_section &&
 926                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 927                 debug("FPGA : Must be in early release mode to program ");
 928                 debug("core bitstream.\n");
 929                 return -EPERM;
 930         }
 931
 932         /* Write the bitstream to FPGA Manager */
 933         fpgamgr_program_write(rbf_data, rbf_size);
 934
 935         status = fpgamgr_program_finish();
 936         if (status)
 937                 return status;
 938
 939         config_pins(gd->fdt_blob, "fpga");
 940         puts("FPGA: Enter user mode.\n");
 941
 942         return status;
 943 }