1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Intel Corporation <www.intel.com>
9 #include <asm/arch/mailbox_s10.h>
10 #include <linux/delay.h>
12 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
13 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
15 static const struct mbox_cfgstat_state {
17 const char *error_name;
18 } mbox_cfgstat_state[] = {
19 {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
20 {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
21 {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
22 {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
23 {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
24 {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
25 {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
26 {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
27 {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
28 {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
29 {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
30 {MBOX_RESP_ERROR, "Mailbox general error!"},
31 {-ETIMEDOUT, "I/O timeout error"},
32 {-1, "Unknown error!"}
35 #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
37 static const char *mbox_cfgstat_to_str(int err)
41 for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
42 if (mbox_cfgstat_state[i].err_no == err)
43 return mbox_cfgstat_state[i].error_name;
46 return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
50 * Add the ongoing transaction's command ID into pending list and return
51 * the command ID for next transfer.
53 static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
57 for (i = 0; i < list_size; i++) {
58 if (xfer_pending_list[i])
60 xfer_pending_list[i] = id;
61 debug("ID(%d) added to transaction pending list\n", id);
63 * Increment command ID for next transaction.
64 * Valid command ID (4 bits) is from 1 to 15.
74 * Check whether response ID match the command ID in the transfer
75 * pending list. If a match is found in the transfer pending list,
76 * it clears the transfer pending list and return the matched
79 static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
84 for (i = 0; i < list_size; i++) {
85 if (id != xfer_pending_list[i])
87 xfer_pending_list[i] = 0;
95 * Polling the FPGA configuration status.
96 * Return 0 for success, non-zero for error.
98 static int reconfig_status_polling_resp(void)
101 unsigned long start = get_timer(0);
104 ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
106 return 0; /* configuration success */
108 if (ret != MBOX_CFGSTAT_STATE_CONFIG)
111 if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
112 break; /* time out */
115 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
121 static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
122 u32 *resp_buf, u32 buf_size, u32 client_id)
124 u32 buf[MBOX_RESP_BUFFER_SIZE];
130 if (*resp_count < buf_size) {
131 u32 rcv_len_max = buf_size - *resp_count;
133 if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
134 rcv_len_max = MBOX_RESP_BUFFER_SIZE;
135 resp_len = mbox_rcv_resp(buf, rcv_len_max);
137 for (i = 0; i < resp_len; i++) {
138 resp_buf[(*w_index)++] = buf[i];
139 *w_index %= buf_size;
144 /* No response in buffer */
145 if (*resp_count == 0)
148 mbox_hdr = resp_buf[*r_index];
150 hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
152 /* Insufficient header length to return a mailbox header */
153 if ((*resp_count - 1) < hdr_len)
156 *r_index += (hdr_len + 1);
157 *r_index %= buf_size;
158 *resp_count -= (hdr_len + 1);
160 /* Make sure response belongs to us */
161 if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
167 /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
168 static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
169 u32 xfer_max, u32 buf_size_max)
171 u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
172 u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
182 debug("SDM xfer_max = %d\n", xfer_max);
183 debug("SDM buf_size_max = %x\n\n", buf_size_max);
185 memset(xfer_pending, 0, sizeof(xfer_pending));
187 while (rbf_size || xfer_count) {
188 if (!resp_err && rbf_size && xfer_count < xfer_max) {
189 args[0] = MBOX_ARG_DESC_COUNT(1);
190 args[1] = (u64)rbf_data;
191 if (rbf_size >= buf_size_max) {
192 args[2] = buf_size_max;
193 rbf_size -= buf_size_max;
194 rbf_data += buf_size_max;
196 args[2] = (u64)rbf_size;
200 resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
201 MBOX_CMD_INDIRECT, 3, args);
204 cmd_id = add_transfer(xfer_pending,
205 MBOX_RESP_BUFFER_SIZE,
210 u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
213 MBOX_RESP_BUFFER_SIZE,
214 MBOX_CLIENT_ID_UBOOT);
217 * If no valid response header found or
218 * non-zero length from RECONFIG_DATA
220 if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
223 /* Check for response's status */
225 resp_err = MBOX_RESP_ERR_GET(resp_hdr);
226 debug("Response error code: %08x\n", resp_err);
229 ret = get_and_clr_transfer(xfer_pending,
230 MBOX_RESP_BUFFER_SIZE,
231 MBOX_RESP_ID_GET(resp_hdr));
233 /* Claim and reuse the ID */
238 if (resp_err && !xfer_count)
247 * This is the interface used by FPGA driver.
248 * Return 0 for success, non-zero for error.
250 int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
256 debug("Sending MBOX_RECONFIG...\n");
257 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
258 NULL, 0, &resp_len, resp_buf);
260 puts("Failure in RECONFIG mailbox command!\n");
264 ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
266 printf("RECONFIG_DATA error: %08x, %s\n", ret,
267 mbox_cfgstat_to_str(ret));
271 /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
272 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
274 debug("Polling with MBOX_RECONFIG_STATUS...\n");
275 ret = reconfig_status_polling_resp();
277 printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
278 mbox_cfgstat_to_str(ret));
282 puts("FPGA reconfiguration OK!\n");