1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Texas Instruments System Control Interface (TISCI) Protocol
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
10 * Based on drivers/firmware/ti_sci.h from Linux.
17 /* Generic Messages */
18 #include <linux/bitops.h>
19 #define TI_SCI_MSG_ENABLE_WDT 0x0000
20 #define TI_SCI_MSG_WAKE_RESET 0x0001
21 #define TI_SCI_MSG_VERSION 0x0002
22 #define TI_SCI_MSG_WAKE_REASON 0x0003
23 #define TI_SCI_MSG_GOODBYE 0x0004
24 #define TI_SCI_MSG_SYS_RESET 0x0005
25 #define TI_SCI_MSG_BOARD_CONFIG 0x000b
26 #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c
27 #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d
28 #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e
29 #define TISCI_MSG_QUERY_MSMC 0x0020
32 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
33 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
34 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
37 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
38 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
39 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
40 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
41 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
42 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
43 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
44 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
46 /* Processor Control Messages */
47 #define TISCI_MSG_PROC_REQUEST 0xc000
48 #define TISCI_MSG_PROC_RELEASE 0xc001
49 #define TISCI_MSG_PROC_HANDOVER 0xc005
50 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
51 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
52 #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
53 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
54 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
56 /* Resource Management Requests */
57 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
59 /* NAVSS resource management */
60 /* Ringacc requests */
61 #define TI_SCI_MSG_RM_RING_CFG 0x1110
64 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
65 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
67 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
68 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
69 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
70 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
71 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
72 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
74 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
75 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
76 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
77 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
79 #define TISCI_MSG_FWL_SET 0x9000
80 #define TISCI_MSG_FWL_GET 0x9001
81 #define TISCI_MSG_FWL_CHANGE_OWNER 0x9002
84 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
85 * @type: Type of messages: One of TI_SCI_MSG* values
86 * @host: Host of the message
87 * @seq: Message identifier indicating a transfer sequence
88 * @flags: Flag for the message
90 struct ti_sci_msg_hdr {
94 #define TI_SCI_MSG_FLAG(val) (1 << (val))
95 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
96 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
97 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
98 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
99 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
100 /* Additional Flags */
105 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
106 * via secure transport.
107 * @checksum: crc16 checksum for the entire message
108 * @reserved: Reserved for future use.
110 struct ti_sci_secure_msg_hdr {
116 * struct ti_sci_msg_resp_version - Response for a message
117 * @hdr: Generic header
118 * @firmware_description: String describing the firmware
119 * @firmware_revision: Firmware revision
120 * @abi_major: Major version of the ABI that firmware supports
121 * @abi_minor: Minor version of the ABI that firmware supports
123 * In general, ABI version changes follow the rule that minor version increments
124 * are backward compatible. Major revision changes in ABI may not be
125 * backward compatible.
127 * Response to a generic message with message type TI_SCI_MSG_VERSION
129 struct ti_sci_msg_resp_version {
130 struct ti_sci_msg_hdr hdr;
131 char firmware_description[32];
132 u16 firmware_revision;
138 * struct ti_sci_msg_req_reboot - Reboot the SoC
139 * @hdr: Generic Header
140 * @domain: Domain to be reset, 0 for full SoC reboot.
142 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
145 struct ti_sci_msg_req_reboot {
146 struct ti_sci_msg_hdr hdr;
151 * struct ti_sci_msg_board_config - Board configuration message
152 * @hdr: Generic Header
153 * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board
155 * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board
157 * @boardcfg_size: Size of board configuration data object
158 * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic
161 struct ti_sci_msg_board_config {
162 struct ti_sci_msg_hdr hdr;
169 * struct ti_sci_msg_resp_query_msmc - Query msmc message response structure
170 * @hdr: Generic Header
171 * @msmc_start_low: Lower 32 bit of msmc start
172 * @msmc_start_high: Upper 32 bit of msmc start
173 * @msmc_end_low: Lower 32 bit of msmc end
174 * @msmc_end_high: Upper 32 bit of msmc end
176 * Response to a generic message with message type TISCI_MSG_QUERY_MSMC
178 struct ti_sci_msg_resp_query_msmc {
179 struct ti_sci_msg_hdr hdr;
187 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
188 * @hdr: Generic header
189 * @id: Indicates which device to modify
190 * @reserved: Reserved space in message, must be 0 for backward compatibility
191 * @state: The desired state of the device.
193 * Certain flags can also be set to alter the device state:
194 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
195 * The meaning of this flag will vary slightly from device to device and from
196 * SoC to SoC but it generally allows the device to wake the SoC out of deep
198 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
199 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
200 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
201 * If another host already has this device set to STATE_RETENTION or STATE_ON,
202 * the message will fail. Once successful, other hosts attempting to set
203 * STATE_RETENTION or STATE_ON will fail.
205 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
208 struct ti_sci_msg_req_set_device_state {
209 /* Additional hdr->flags options */
210 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
211 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
212 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
213 struct ti_sci_msg_hdr hdr;
217 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
218 #define MSG_DEVICE_SW_STATE_RETENTION 1
219 #define MSG_DEVICE_SW_STATE_ON 2
224 * struct ti_sci_msg_req_get_device_state - Request to get device.
225 * @hdr: Generic header
226 * @id: Device Identifier
228 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
231 struct ti_sci_msg_req_get_device_state {
232 struct ti_sci_msg_hdr hdr;
237 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
238 * @hdr: Generic header
239 * @context_loss_count: Indicates how many times the device has lost context. A
240 * driver can use this monotonic counter to determine if the device has
241 * lost context since the last time this message was exchanged.
242 * @resets: Programmed state of the reset lines.
243 * @programmed_state: The state as programmed by set_device.
244 * - Uses the MSG_DEVICE_SW_* macros
245 * @current_state: The actual state of the hardware.
247 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
249 struct ti_sci_msg_resp_get_device_state {
250 struct ti_sci_msg_hdr hdr;
251 u32 context_loss_count;
254 #define MSG_DEVICE_HW_STATE_OFF 0
255 #define MSG_DEVICE_HW_STATE_ON 1
256 #define MSG_DEVICE_HW_STATE_TRANS 2
261 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
262 * configuration of the device
263 * @hdr: Generic header
264 * @id: Indicates which device to modify
265 * @resets: A bit field of resets for the device. The meaning, behavior,
266 * and usage of the reset flags are device specific. 0 for a bit
267 * indicates releasing the reset represented by that bit while 1
268 * indicates keeping it held.
270 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
273 struct ti_sci_msg_req_set_device_resets {
274 struct ti_sci_msg_hdr hdr;
280 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
281 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
282 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
283 * via spread spectrum clocking.
284 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
285 * frequency to be changed while it is running so long as it
286 * is within the min/max limits.
287 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
288 * is only applicable to clock inputs on the SoC pseudo-device.
289 * @dev_id: Device identifier this request is for
290 * @clk_id: Clock identifier for the device for this request.
291 * Each device has it's own set of clock inputs. This indexes
292 * which clock input to modify.
293 * @request_state: Request the state for the clock to be set to.
294 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
295 * it can be disabled, regardless of the state of the device
296 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
297 * automatically manage the state of this clock. If the device
298 * is enabled, then the clock is enabled. If the device is set
299 * to off or retention, then the clock is internally set as not
300 * being required by the device.(default)
301 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
302 * regardless of the state of the device.
304 * Normally, all required clocks are managed by TISCI entity, this is used
305 * only for specific control *IF* required. Auto managed state is
306 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
307 * will explicitly control.
309 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
310 * ACK or NACK message.
312 struct ti_sci_msg_req_set_clock_state {
313 /* Additional hdr->flags options */
314 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
315 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
316 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
317 struct ti_sci_msg_hdr hdr;
320 #define MSG_CLOCK_SW_STATE_UNREQ 0
321 #define MSG_CLOCK_SW_STATE_AUTO 1
322 #define MSG_CLOCK_SW_STATE_REQ 2
327 * struct ti_sci_msg_req_get_clock_state - Request for clock state
328 * @hdr: Generic Header
329 * @dev_id: Device identifier this request is for
330 * @clk_id: Clock identifier for the device for this request.
331 * Each device has it's own set of clock inputs. This indexes
332 * which clock input to get state of.
334 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
337 struct ti_sci_msg_req_get_clock_state {
338 struct ti_sci_msg_hdr hdr;
344 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
345 * @hdr: Generic Header
346 * @programmed_state: Any programmed state of the clock. This is one of
347 * MSG_CLOCK_SW_STATE* values.
348 * @current_state: Current state of the clock. This is one of:
349 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
350 * MSG_CLOCK_HW_STATE_READY: Clock is ready
352 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
354 struct ti_sci_msg_resp_get_clock_state {
355 struct ti_sci_msg_hdr hdr;
357 #define MSG_CLOCK_HW_STATE_NOT_READY 0
358 #define MSG_CLOCK_HW_STATE_READY 1
363 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
364 * @hdr: Generic Header
365 * @dev_id: Device identifier this request is for
366 * @clk_id: Clock identifier for the device for this request.
367 * Each device has it's own set of clock inputs. This indexes
368 * which clock input to modify.
369 * @parent_id: The new clock parent is selectable by an index via this
372 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
373 * ACK / NACK message.
375 struct ti_sci_msg_req_set_clock_parent {
376 struct ti_sci_msg_hdr hdr;
383 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
384 * @hdr: Generic Header
385 * @dev_id: Device identifier this request is for
386 * @clk_id: Clock identifier for the device for this request.
387 * Each device has it's own set of clock inputs. This indexes
388 * which clock input to get the parent for.
390 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
392 struct ti_sci_msg_req_get_clock_parent {
393 struct ti_sci_msg_hdr hdr;
399 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
400 * @hdr: Generic Header
401 * @parent_id: The current clock parent
403 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
405 struct ti_sci_msg_resp_get_clock_parent {
406 struct ti_sci_msg_hdr hdr;
411 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
412 * @hdr: Generic header
413 * @dev_id: Device identifier this request is for
414 * @clk_id: Clock identifier for the device for this request.
416 * This request provides information about how many clock parent options
417 * are available for a given clock to a device. This is typically used
420 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
421 * message, or NACK in case of inability to satisfy request.
423 struct ti_sci_msg_req_get_clock_num_parents {
424 struct ti_sci_msg_hdr hdr;
430 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
431 * @hdr: Generic header
432 * @num_parents: Number of clock parents
434 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
436 struct ti_sci_msg_resp_get_clock_num_parents {
437 struct ti_sci_msg_hdr hdr;
442 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
443 * @hdr: Generic Header
444 * @dev_id: Device identifier this request is for
445 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
446 * allowable programmed frequency and does not account for clock
447 * tolerances and jitter.
448 * @target_freq_hz: The target clock frequency. A frequency will be found
449 * as close to this target frequency as possible.
450 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
451 * allowable programmed frequency and does not account for clock
452 * tolerances and jitter.
453 * @clk_id: Clock identifier for the device for this request.
455 * NOTE: Normally clock frequency management is automatically done by TISCI
456 * entity. In case of specific requests, TISCI evaluates capability to achieve
457 * requested frequency within provided range and responds with
460 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
461 * or NACK in case of inability to satisfy request.
463 struct ti_sci_msg_req_query_clock_freq {
464 struct ti_sci_msg_hdr hdr;
473 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
474 * @hdr: Generic Header
475 * @freq_hz: Frequency that is the best match in Hz.
477 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
478 * cannot be satisfied, the message will be of type NACK.
480 struct ti_sci_msg_resp_query_clock_freq {
481 struct ti_sci_msg_hdr hdr;
486 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
487 * @hdr: Generic Header
488 * @dev_id: Device identifier this request is for
489 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
490 * allowable programmed frequency and does not account for clock
491 * tolerances and jitter.
492 * @target_freq_hz: The target clock frequency. The clock will be programmed
493 * at a rate as close to this target frequency as possible.
494 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
495 * allowable programmed frequency and does not account for clock
496 * tolerances and jitter.
497 * @clk_id: Clock identifier for the device for this request.
499 * NOTE: Normally clock frequency management is automatically done by TISCI
500 * entity. In case of specific requests, TISCI evaluates capability to achieve
501 * requested range and responds with success/failure message.
503 * This sets the desired frequency for a clock within an allowable
504 * range. This message will fail on an enabled clock unless
505 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
506 * if other clocks have their frequency modified due to this message,
507 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
509 * Calling set frequency on a clock input to the SoC pseudo-device will
510 * inform the PMMC of that clock's frequency. Setting a frequency of
511 * zero will indicate the clock is disabled.
513 * Calling set frequency on clock outputs from the SoC pseudo-device will
514 * function similarly to setting the clock frequency on a device.
516 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
519 struct ti_sci_msg_req_set_clock_freq {
520 struct ti_sci_msg_hdr hdr;
529 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
530 * @hdr: Generic Header
531 * @dev_id: Device identifier this request is for
532 * @clk_id: Clock identifier for the device for this request.
534 * NOTE: Normally clock frequency management is automatically done by TISCI
535 * entity. In some cases, clock frequencies are configured by host.
537 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
538 * that the clock is currently at.
540 struct ti_sci_msg_req_get_clock_freq {
541 struct ti_sci_msg_hdr hdr;
547 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
548 * @hdr: Generic Header
549 * @freq_hz: Frequency that the clock is currently on, in Hz.
551 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
553 struct ti_sci_msg_resp_get_clock_freq {
554 struct ti_sci_msg_hdr hdr;
558 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
561 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
562 * range of resources.
563 * @hdr: Generic Header
564 * @type: Unique resource assignment type
565 * @subtype: Resource assignment subtype within the resource type.
566 * @secondary_host: Host processing entity to which the resources are
567 * allocated. This is required only when the destination
568 * host id id different from ti sci interface host id,
569 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
571 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
572 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
574 struct ti_sci_msg_req_get_resource_range {
575 struct ti_sci_msg_hdr hdr;
576 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
577 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
584 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
585 * @hdr: Generic Header
586 * @range_start: Start index of the resource range.
587 * @range_num: Number of resources in the range.
589 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
591 struct ti_sci_msg_resp_get_resource_range {
592 struct ti_sci_msg_hdr hdr;
597 #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
598 #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
599 #define TISCI_ADDR_HIGH_SHIFT 32
602 * struct ti_sci_msg_req_proc_request - Request a processor
604 * @hdr: Generic Header
605 * @processor_id: ID of processor
607 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
610 struct ti_sci_msg_req_proc_request {
611 struct ti_sci_msg_hdr hdr;
616 * struct ti_sci_msg_req_proc_release - Release a processor
618 * @hdr: Generic Header
619 * @processor_id: ID of processor
621 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
624 struct ti_sci_msg_req_proc_release {
625 struct ti_sci_msg_hdr hdr;
630 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
632 * @hdr: Generic Header
633 * @processor_id: ID of processor
634 * @host_id: New Host we want to give control to
636 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
639 struct ti_sci_msg_req_proc_handover {
640 struct ti_sci_msg_hdr hdr;
645 /* A53 Config Flags */
646 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
647 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
648 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
649 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
650 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
652 /* R5 Config Flags */
653 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
654 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
655 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
656 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
657 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
658 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
659 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
660 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
663 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
664 * @hdr: Generic Header
665 * @processor_id: ID of processor
666 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
667 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
668 * @config_flags_set: Optional Processor specific Config Flags to set.
669 * Setting a bit here implies required bit sets to 1.
670 * @config_flags_clear: Optional Processor specific Config Flags to clear.
671 * Setting a bit here implies required bit gets cleared.
673 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
676 struct ti_sci_msg_req_set_proc_boot_config {
677 struct ti_sci_msg_hdr hdr;
681 u32 config_flags_set;
682 u32 config_flags_clear;
685 /* R5 Control Flags */
686 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
689 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
690 * @hdr: Generic Header
691 * @processor_id: ID of processor
692 * @control_flags_set: Optional Processor specific Control Flags to set.
693 * Setting a bit here implies required bit sets to 1.
694 * @control_flags_clear:Optional Processor specific Control Flags to clear.
695 * Setting a bit here implies required bit gets cleared.
697 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
700 struct ti_sci_msg_req_set_proc_boot_ctrl {
701 struct ti_sci_msg_hdr hdr;
703 u32 control_flags_set;
704 u32 control_flags_clear;
708 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
709 * @hdr: Generic Header
710 * @cert_addr_low: Lower 32bit (Little Endian) of certificate
711 * @cert_addr_high: Higher 32bit (Little Endian) of certificate
713 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
716 struct ti_sci_msg_req_proc_auth_boot_image {
717 struct ti_sci_msg_hdr hdr;
722 struct ti_sci_msg_resp_proc_auth_boot_image {
723 struct ti_sci_msg_hdr hdr;
730 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
731 * @hdr: Generic Header
732 * @processor_id: ID of processor
734 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
735 * message, or NACK in case of inability to satisfy request.
737 struct ti_sci_msg_req_get_proc_boot_status {
738 struct ti_sci_msg_hdr hdr;
742 /* ARMv8 Status Flags */
743 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
744 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
746 /* R5 Status Flags */
747 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
748 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
749 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
750 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
753 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
754 * @hdr: Generic Header
755 * @processor_id: ID of processor
756 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
757 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
758 * @config_flags: Optional Processor specific Config Flags set.
759 * @control_flags: Optional Processor specific Control Flags.
760 * @status_flags: Optional Processor specific Status Flags set.
762 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
764 struct ti_sci_msg_resp_get_proc_boot_status {
765 struct ti_sci_msg_hdr hdr;
775 * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
777 * @hdr: Generic Header
778 * @processor_id: ID of processor
779 * @num_wait_iterations: Total number of iterations we will check before
780 * we will timeout and give up
781 * @num_match_iterations: How many iterations should we have continued
782 * status to account for status bits glitching.
783 * This is to make sure that match occurs for
784 * consecutive checks. This implies that the
785 * worst case should consider that the stable
786 * time should at the worst be num_wait_iterations
787 * num_match_iterations to prevent timeout.
788 * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
789 * between each status checks. This is the minimum
790 * duration, and overhead of register reads and
791 * checks are on top of this and can vary based on
793 * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
794 * before the very first check in the first
795 * iteration of status check loop. This is the
796 * minimum duration, and overhead of register
797 * reads and checks are.
798 * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
799 * status matching this field requested MUST be 1.
800 * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
801 * bits matching this field requested MUST be 1.
802 * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
803 * status matching this field requested MUST be 0.
804 * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
805 * bits matching this field requested MUST be 0.
807 * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
808 * message, or NACK in case of inability to satisfy request.
810 struct ti_sci_msg_req_wait_proc_boot_status {
811 struct ti_sci_msg_hdr hdr;
813 u8 num_wait_iterations;
814 u8 num_match_iterations;
815 u8 delay_per_iteration_us;
816 u8 delay_before_iterations_us;
817 u32 status_flags_1_set_all_wait;
818 u32 status_flags_1_set_any_wait;
819 u32 status_flags_1_clr_all_wait;
820 u32 status_flags_1_clr_any_wait;
824 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
826 * Configures the non-real-time registers of a Navigator Subsystem ring.
827 * @hdr: Generic Header
828 * @valid_params: Bitfield defining validity of ring configuration parameters.
829 * The ring configuration fields are not valid, and will not be used for
830 * ring configuration, if their corresponding valid bit is zero.
832 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
833 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
834 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
835 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
836 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
837 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
838 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
839 * @index: ring index to be configured.
840 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
841 * RING_BA_LO register
842 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
843 * RING_BA_HI register.
844 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
846 * @mode: Specifies the mode the ring is to be configured.
847 * @size: Specifies encoded ring element size. To calculate the encoded size use
848 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
850 * @order_id: Specifies the ring's bus order ID.
852 struct ti_sci_msg_rm_ring_cfg_req {
853 struct ti_sci_msg_hdr hdr;
866 * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
868 * @hdr: Generic Header
870 struct ti_sci_msg_rm_ring_cfg_resp {
871 struct ti_sci_msg_hdr hdr;
875 * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
877 * Gets the configuration of the non-real-time register fields of a ring. The
878 * host, or a supervisor of the host, who owns the ring must be the requesting
879 * host. The values of the non-real-time registers are returned in
880 * @ti_sci_msg_rm_ring_get_cfg_resp.
882 * @hdr: Generic Header
883 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
884 * @index: ring index.
886 struct ti_sci_msg_rm_ring_get_cfg_req {
887 struct ti_sci_msg_hdr hdr;
893 * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
895 * Response received by host processor after RM has handled
896 * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
897 * non-real-time register values.
899 * @hdr: Generic Header
900 * @addr_lo: Ring 32 LSBs of base address
901 * @addr_hi: Ring 16 MSBs of base address.
902 * @count: Ring number of elements.
904 * @size: encoded Ring element size
905 * @order_id: ing order ID.
907 struct ti_sci_msg_rm_ring_get_cfg_resp {
908 struct ti_sci_msg_hdr hdr;
918 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
920 * @hdr: Generic Header
921 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
922 * used to pair the source and destination threads.
923 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
925 * UDMAP transmit channels mapped to source threads will have their
926 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
929 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
930 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
931 * the destination thread is not greater than or equal to 0x8000.
933 * UDMAP receive channels mapped to destination threads will have their
934 * RCHAN_THRD_ID register programmed with the source thread if the pairing
937 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
940 struct ti_sci_msg_psil_pair {
941 struct ti_sci_msg_hdr hdr;
948 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
950 * @hdr: Generic Header
951 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
952 * used to unpair the source and destination threads.
953 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
955 * UDMAP transmit channels mapped to source threads will have their
956 * TCHAN_THRD_ID register cleared if the unpairing is successful.
958 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
959 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
960 * the destination thread is not greater than or equal to 0x8000.
962 * UDMAP receive channels mapped to destination threads will have their
963 * RCHAN_THRD_ID register cleared if the unpairing is successful.
965 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
968 struct ti_sci_msg_psil_unpair {
969 struct ti_sci_msg_hdr hdr;
976 * Configures a Navigator Subsystem UDMAP transmit channel
978 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
979 * transmit channel. The channel index must be assigned to the host defined
980 * in the TISCI header via the RM board configuration resource assignment
983 * @hdr: Generic Header
985 * @valid_params: Bitfield defining validity of tx channel configuration
986 * parameters. The tx channel configuration fields are not valid, and will not
987 * be used for ch configuration, if their corresponding valid bit is zero.
989 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
990 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
991 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
992 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
993 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
994 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
995 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
996 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
997 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
998 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
999 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
1000 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
1001 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
1002 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
1003 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
1004 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
1005 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
1007 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
1009 * @index: UDMAP transmit channel index.
1011 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
1012 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
1015 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
1016 * configuration to be programmed into the tx_filt_einfo field of the
1017 * channel's TCHAN_TCFG register.
1019 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
1020 * configuration to be programmed into the tx_filt_pswords field of the
1021 * channel's TCHAN_TCFG register.
1023 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
1024 * interpretation configuration to be programmed into the tx_atype field of
1025 * the channel's TCHAN_TCFG register.
1027 * @tx_chan_type: UDMAP transmit channel functional channel type and work
1028 * passing mechanism configuration to be programmed into the tx_chan_type
1029 * field of the channel's TCHAN_TCFG register.
1031 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
1032 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
1033 * TCHAN_TCFG register.
1035 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
1036 * fetch configuration to be programmed into the tx_fetch_size field of the
1037 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
1038 * word count that can pass through the channel for any allowed descriptor type.
1040 * @tx_credit_count: UDMAP transmit channel transfer request credit count
1041 * configuration to be programmed into the count field of the TCHAN_TCREDIT
1042 * register. Specifies how many credits for complete TRs are available.
1044 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
1045 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
1046 * completion queue must be assigned to the host, or a subordinate of the host,
1047 * requesting configuration of the transmit channel.
1049 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
1050 * into the priority field of the channel's TCHAN_TPRI_CTRL register.
1052 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
1053 * qos field of the channel's TCHAN_TPRI_CTRL register.
1055 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
1056 * the orderid field of the channel's TCHAN_TPRI_CTRL register.
1058 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
1059 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
1060 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
1061 * section of the TRM for restrictions regarding this parameter.
1063 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
1064 * configuration to be programmed into the priority field of the channel's
1065 * TCHAN_TST_SCHED register.
1067 * @tx_burst_size: UDMAP transmit channel burst size configuration to be
1068 * programmed into the tx_burst_size field of the TCHAN_TCFG register.
1070 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
1071 * programmed into the tdtype field of the TCHAN_TCFG register:
1072 * 0 - Return immediately
1073 * 1 - Wait for completion message from remote peer
1075 * @extended_ch_type: Valid for BCDMA.
1076 * 0 - the channel is split tx channel (tchan)
1077 * 1 - the channel is block copy channel (bchan)
1079 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
1080 struct ti_sci_msg_hdr hdr;
1097 u8 tx_sched_priority;
1100 u8 extended_ch_type;
1104 * Response to configuring a UDMAP transmit channel.
1106 * @hdr: Standard TISCI header
1108 struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
1109 struct ti_sci_msg_hdr hdr;
1113 * Configures a Navigator Subsystem UDMAP receive channel
1115 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1116 * receive channel. The channel index must be assigned to the host defined
1117 * in the TISCI header via the RM board configuration resource assignment
1120 * @hdr: Generic Header
1122 * @valid_params: Bitfield defining validity of rx channel configuration
1124 * The rx channel configuration fields are not valid, and will not be used for
1125 * ch configuration, if their corresponding valid bit is zero.
1127 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1128 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1129 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1130 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1131 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1132 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1133 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1134 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1135 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1136 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1137 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1138 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1139 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1141 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1143 * @index: UDMAP receive channel index.
1145 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1146 * fetch configuration to be programmed into the rx_fetch_size field of the
1147 * channel's RCHAN_RCFG register.
1149 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1150 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1151 * The specified completion queue must be assigned to the host, or a subordinate
1152 * of the host, requesting configuration of the receive channel.
1154 * @rx_priority: UDMAP receive channel receive priority value to be programmed
1155 * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1157 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1158 * qos field of the channel's RCHAN_RPRI_CTRL register.
1160 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1161 * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1163 * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1164 * configuration to be programmed into the priority field of the channel's
1165 * RCHAN_RST_SCHED register.
1167 * @flowid_start: UDMAP receive channel additional flows starting index
1168 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1169 * register. Specifies the starting index for flow IDs the receive channel is to
1170 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1171 * set as valid and configured together. The starting flow ID set by
1172 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1173 * of flows beyond the default flows statically mapped to receive channels.
1174 * The additional flows must be assigned to the host, or a subordinate of the
1175 * host, requesting configuration of the receive channel.
1177 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1178 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1179 * This field specifies how many flow IDs are in the additional contiguous range
1180 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
1181 * set as valid and configured together. Disabling the valid_params field bit
1182 * for flowid_cnt indicates no flow IDs other than the default are to be
1183 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1184 * cannot be greater than the number of receive flows in the receive channel's
1185 * Navigator Subsystem. The additional flows must be assigned to the host, or a
1186 * subordinate of the host, requesting configuration of the receive channel.
1188 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1189 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1192 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1193 * interpretation configuration to be programmed into the rx_atype field of the
1194 * channel's RCHAN_RCFG register.
1196 * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1197 * mechanism configuration to be programmed into the rx_chan_type field of the
1198 * channel's RCHAN_RCFG register.
1200 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1201 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1203 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1204 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1206 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1207 struct ti_sci_msg_hdr hdr;
1216 u8 rx_sched_priority;
1227 * Response to configuring a UDMAP receive channel.
1229 * @hdr: Standard TISCI header
1231 struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
1232 struct ti_sci_msg_hdr hdr;
1236 * Configures a Navigator Subsystem UDMAP receive flow
1238 * Configures a Navigator Subsystem UDMAP receive flow's registers.
1239 * Configuration does not include the flow registers which handle size-based
1240 * free descriptor queue routing.
1242 * The flow index must be assigned to the host defined in the TISCI header via
1243 * the RM board configuration resource assignment range list.
1245 * @hdr: Standard TISCI header
1248 * Bitfield defining validity of rx flow configuration parameters. The
1249 * rx flow configuration fields are not valid, and will not be used for flow
1250 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1251 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1252 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1253 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1254 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1255 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1256 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1257 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1258 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1259 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1260 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1261 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1262 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1263 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1264 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1265 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1266 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1267 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1268 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1269 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1271 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1274 * @flow_index: UDMAP receive flow index for non-optional configuration.
1276 * @rx_einfo_present:
1277 * UDMAP receive flow extended packet info present configuration to be
1278 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1280 * @rx_psinfo_present:
1281 * UDMAP receive flow PS words present configuration to be programmed into the
1282 * rx_psinfo_present field of the flow's RFLOW_RFA register.
1284 * @rx_error_handling:
1285 * UDMAP receive flow error handling configuration to be programmed into the
1286 * rx_error_handling field of the flow's RFLOW_RFA register.
1289 * UDMAP receive flow descriptor type configuration to be programmed into the
1290 * rx_desc_type field field of the flow's RFLOW_RFA register.
1293 * UDMAP receive flow start of packet offset configuration to be programmed
1294 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
1295 * section of the TRM for more information on this setting. Valid values for
1296 * this field are 0-255 bytes.
1299 * UDMAP receive flow destination queue configuration to be programmed into the
1300 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
1301 * destination queue must be valid within the Navigator Subsystem and must be
1302 * owned by the host, or a subordinate of the host, requesting allocation and
1303 * configuration of the receive flow.
1306 * UDMAP receive flow source tag high byte constant configuration to be
1307 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1308 * See the UDMAP section of the TRM for more information on this setting.
1311 * UDMAP receive flow source tag low byte constant configuration to be
1312 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1313 * See the UDMAP section of the TRM for more information on this setting.
1316 * UDMAP receive flow destination tag high byte constant configuration to be
1317 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1318 * See the UDMAP section of the TRM for more information on this setting.
1321 * UDMAP receive flow destination tag low byte constant configuration to be
1322 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1323 * See the UDMAP section of the TRM for more information on this setting.
1325 * @rx_src_tag_hi_sel:
1326 * UDMAP receive flow source tag high byte selector configuration to be
1327 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
1328 * the UDMAP section of the TRM for more information on this setting.
1330 * @rx_src_tag_lo_sel:
1331 * UDMAP receive flow source tag low byte selector configuration to be
1332 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
1333 * the UDMAP section of the TRM for more information on this setting.
1335 * @rx_dest_tag_hi_sel:
1336 * UDMAP receive flow destination tag high byte selector configuration to be
1337 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
1338 * the UDMAP section of the TRM for more information on this setting.
1340 * @rx_dest_tag_lo_sel:
1341 * UDMAP receive flow destination tag low byte selector configuration to be
1342 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
1343 * the UDMAP section of the TRM for more information on this setting.
1345 * @rx_fdq0_sz0_qnum:
1346 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1347 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
1348 * UDMAP section of the TRM for more information on this setting. The specified
1349 * free queue must be valid within the Navigator Subsystem and must be owned
1350 * by the host, or a subordinate of the host, requesting allocation and
1351 * configuration of the receive flow.
1354 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1355 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
1356 * UDMAP section of the TRM for more information on this setting. The specified
1357 * free queue must be valid within the Navigator Subsystem and must be owned
1358 * by the host, or a subordinate of the host, requesting allocation and
1359 * configuration of the receive flow.
1362 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1363 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
1364 * UDMAP section of the TRM for more information on this setting. The specified
1365 * free queue must be valid within the Navigator Subsystem and must be owned
1366 * by the host, or a subordinate of the host, requesting allocation and
1367 * configuration of the receive flow.
1370 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1371 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
1372 * UDMAP section of the TRM for more information on this setting. The specified
1373 * free queue must be valid within the Navigator Subsystem and must be owned
1374 * by the host, or a subordinate of the host, requesting allocation and
1375 * configuration of the receive flow.
1378 * UDMAP receive flow PS words location configuration to be programmed into the
1379 * rx_ps_location field of the flow's RFLOW_RFA register.
1381 struct ti_sci_msg_rm_udmap_flow_cfg_req {
1382 struct ti_sci_msg_hdr hdr;
1386 u8 rx_einfo_present;
1387 u8 rx_psinfo_present;
1388 u8 rx_error_handling;
1396 u8 rx_src_tag_hi_sel;
1397 u8 rx_src_tag_lo_sel;
1398 u8 rx_dest_tag_hi_sel;
1399 u8 rx_dest_tag_lo_sel;
1400 u16 rx_fdq0_sz0_qnum;
1408 * Response to configuring a Navigator Subsystem UDMAP receive flow
1410 * @hdr: Standard TISCI header
1412 struct ti_sci_msg_rm_udmap_flow_cfg_resp {
1413 struct ti_sci_msg_hdr hdr;
1416 #define FWL_MAX_PRIVID_SLOTS 3U
1419 * struct ti_sci_msg_fwl_set_firewall_region_req - Request for configuring the firewall permissions.
1421 * @hdr: Generic Header
1423 * @fwl_id: Firewall ID in question
1424 * @region: Region or channel number to set config info
1425 * This field is unused in case of a simple firewall and must be initialized
1426 * to zero. In case of a region based firewall, this field indicates the
1427 * region in question. (index starting from 0) In case of a channel based
1428 * firewall, this field indicates the channel in question (index starting
1430 * @n_permission_regs: Number of permission registers to set
1431 * @control: Contents of the firewall CONTROL register to set
1432 * @permissions: Contents of the firewall PERMISSION register to set
1433 * @start_address: Contents of the firewall START_ADDRESS register to set
1434 * @end_address: Contents of the firewall END_ADDRESS register to set
1437 struct ti_sci_msg_fwl_set_firewall_region_req {
1438 struct ti_sci_msg_hdr hdr;
1441 u32 n_permission_regs;
1443 u32 permissions[FWL_MAX_PRIVID_SLOTS];
1449 * struct ti_sci_msg_fwl_get_firewall_region_req - Request for retrieving the firewall permissions
1451 * @hdr: Generic Header
1453 * @fwl_id: Firewall ID in question
1454 * @region: Region or channel number to get config info
1455 * This field is unused in case of a simple firewall and must be initialized
1456 * to zero. In case of a region based firewall, this field indicates the
1457 * region in question (index starting from 0). In case of a channel based
1458 * firewall, this field indicates the channel in question (index starting
1460 * @n_permission_regs: Number of permission registers to retrieve
1462 struct ti_sci_msg_fwl_get_firewall_region_req {
1463 struct ti_sci_msg_hdr hdr;
1466 u32 n_permission_regs;
1470 * struct ti_sci_msg_fwl_get_firewall_region_resp - Response for retrieving the firewall permissions
1472 * @hdr: Generic Header
1474 * @fwl_id: Firewall ID in question
1475 * @region: Region or channel number to set config info This field is
1476 * unused in case of a simple firewall and must be initialized to zero. In
1477 * case of a region based firewall, this field indicates the region in
1478 * question. (index starting from 0) In case of a channel based firewall, this
1479 * field indicates the channel in question (index starting from 0)
1480 * @n_permission_regs: Number of permission registers retrieved
1481 * @control: Contents of the firewall CONTROL register
1482 * @permissions: Contents of the firewall PERMISSION registers
1483 * @start_address: Contents of the firewall START_ADDRESS register This is not applicable for channelized firewalls.
1484 * @end_address: Contents of the firewall END_ADDRESS register This is not applicable for channelized firewalls.
1486 struct ti_sci_msg_fwl_get_firewall_region_resp {
1487 struct ti_sci_msg_hdr hdr;
1490 u32 n_permission_regs;
1492 u32 permissions[FWL_MAX_PRIVID_SLOTS];
1498 * struct ti_sci_msg_fwl_change_owner_info_req - Request for a firewall owner change
1500 * @hdr: Generic Header
1502 * @fwl_id: Firewall ID in question
1503 * @region: Region or channel number if applicable
1504 * @owner_index: New owner index to transfer ownership to
1506 struct ti_sci_msg_fwl_change_owner_info_req {
1507 struct ti_sci_msg_hdr hdr;
1514 * struct ti_sci_msg_fwl_change_owner_info_resp - Response for a firewall owner change
1516 * @hdr: Generic Header
1518 * @fwl_id: Firewall ID specified in request
1519 * @region: Region or channel number specified in request
1520 * @owner_index: Owner index specified in request
1521 * @owner_privid: New owner priv-ID returned by DMSC.
1522 * @owner_permission_bits: New owner permission bits returned by DMSC.
1524 struct ti_sci_msg_fwl_change_owner_info_resp {
1525 struct ti_sci_msg_hdr hdr;
1530 u16 owner_permission_bits;
1533 #endif /* __TI_SCI_H */