drivers/firmware/qcom_scm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2015 Linaro Ltd.
   4  */
   5 #include <linux/platform_device.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/completion.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/export.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/interconnect.h>
  13 #include <linux/module.h>
  14 #include <linux/types.h>
  15 #include <linux/firmware/qcom/qcom_scm.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/clk.h>
  21 #include <linux/reset-controller.h>
  22 #include <linux/arm-smccc.h>
  23
  24 #include "qcom_scm.h"
  25
  26 static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
  27 module_param(download_mode, bool, 0);
  28
  29 struct qcom_scm {
  30         struct device *dev;
  31         struct clk *core_clk;
  32         struct clk *iface_clk;
  33         struct clk *bus_clk;
  34         struct icc_path *path;
  35         struct completion waitq_comp;
  36         struct reset_controller_dev reset;
  37
  38         /* control access to the interconnect path */
  39         struct mutex scm_bw_lock;
  40         int scm_vote_count;
  41
  42         u64 dload_mode_addr;
  43 };
  44
  45 struct qcom_scm_current_perm_info {
  46         __le32 vmid;
  47         __le32 perm;
  48         __le64 ctx;
  49         __le32 ctx_size;
  50         __le32 unused;
  51 };
  52
  53 struct qcom_scm_mem_map_info {
  54         __le64 mem_addr;
  55         __le64 mem_size;
  56 };
  57
  58 /* Each bit configures cold/warm boot address for one of the 4 CPUs */
  59 static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
  60         0, BIT(0), BIT(3), BIT(5)
  61 };
  62 static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
  63         BIT(2), BIT(1), BIT(4), BIT(6)
  64 };
  65
  66 #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE    BIT(0)
  67 #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL    BIT(1)
  68
  69 static const char * const qcom_scm_convention_names[] = {
  70         [SMC_CONVENTION_UNKNOWN] = "unknown",
  71         [SMC_CONVENTION_ARM_32] = "smc arm 32",
  72         [SMC_CONVENTION_ARM_64] = "smc arm 64",
  73         [SMC_CONVENTION_LEGACY] = "smc legacy",
  74 };
  75
  76 static struct qcom_scm *__scm;
  77
  78 static int qcom_scm_clk_enable(void)
  79 {
  80         int ret;
  81
  82         ret = clk_prepare_enable(__scm->core_clk);
  83         if (ret)
  84                 goto bail;
  85
  86         ret = clk_prepare_enable(__scm->iface_clk);
  87         if (ret)
  88                 goto disable_core;
  89
  90         ret = clk_prepare_enable(__scm->bus_clk);
  91         if (ret)
  92                 goto disable_iface;
  93
  94         return 0;
  95
  96 disable_iface:
  97         clk_disable_unprepare(__scm->iface_clk);
  98 disable_core:
  99         clk_disable_unprepare(__scm->core_clk);
 100 bail:
 101         return ret;
 102 }
 103
 104 static void qcom_scm_clk_disable(void)
 105 {
 106         clk_disable_unprepare(__scm->core_clk);
 107         clk_disable_unprepare(__scm->iface_clk);
 108         clk_disable_unprepare(__scm->bus_clk);
 109 }
 110
 111 static int qcom_scm_bw_enable(void)
 112 {
 113         int ret = 0;
 114
 115         if (!__scm->path)
 116                 return 0;
 117
 118         if (IS_ERR(__scm->path))
 119                 return -EINVAL;
 120
 121         mutex_lock(&__scm->scm_bw_lock);
 122         if (!__scm->scm_vote_count) {
 123                 ret = icc_set_bw(__scm->path, 0, UINT_MAX);
 124                 if (ret < 0) {
 125                         dev_err(__scm->dev, "failed to set bandwidth request\n");
 126                         goto err_bw;
 127                 }
 128         }
 129         __scm->scm_vote_count++;
 130 err_bw:
 131         mutex_unlock(&__scm->scm_bw_lock);
 132
 133         return ret;
 134 }
 135
 136 static void qcom_scm_bw_disable(void)
 137 {
 138         if (IS_ERR_OR_NULL(__scm->path))
 139                 return;
 140
 141         mutex_lock(&__scm->scm_bw_lock);
 142         if (__scm->scm_vote_count-- == 1)
 143                 icc_set_bw(__scm->path, 0, 0);
 144         mutex_unlock(&__scm->scm_bw_lock);
 145 }
 146
 147 enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN;
 148 static DEFINE_SPINLOCK(scm_query_lock);
 149
 150 static enum qcom_scm_convention __get_convention(void)
 151 {
 152         unsigned long flags;
 153         struct qcom_scm_desc desc = {
 154                 .svc = QCOM_SCM_SVC_INFO,
 155                 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
 156                 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
 157                                            QCOM_SCM_INFO_IS_CALL_AVAIL) |
 158                            (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
 159                 .arginfo = QCOM_SCM_ARGS(1),
 160                 .owner = ARM_SMCCC_OWNER_SIP,
 161         };
 162         struct qcom_scm_res res;
 163         enum qcom_scm_convention probed_convention;
 164         int ret;
 165         bool forced = false;
 166
 167         if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN))
 168                 return qcom_scm_convention;
 169
 170         /*
 171          * Device isn't required as there is only one argument - no device
 172          * needed to dma_map_single to secure world
 173          */
 174         probed_convention = SMC_CONVENTION_ARM_64;
 175         ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true);
 176         if (!ret && res.result[0] == 1)
 177                 goto found;
 178
 179         /*
 180          * Some SC7180 firmwares didn't implement the
 181          * QCOM_SCM_INFO_IS_CALL_AVAIL call, so we fallback to forcing ARM_64
 182          * calling conventions on these firmwares. Luckily we don't make any
 183          * early calls into the firmware on these SoCs so the device pointer
 184          * will be valid here to check if the compatible matches.
 185          */
 186         if (of_device_is_compatible(__scm ? __scm->dev->of_node : NULL, "qcom,scm-sc7180")) {
 187                 forced = true;
 188                 goto found;
 189         }
 190
 191         probed_convention = SMC_CONVENTION_ARM_32;
 192         ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true);
 193         if (!ret && res.result[0] == 1)
 194                 goto found;
 195
 196         probed_convention = SMC_CONVENTION_LEGACY;
 197 found:
 198         spin_lock_irqsave(&scm_query_lock, flags);
 199         if (probed_convention != qcom_scm_convention) {
 200                 qcom_scm_convention = probed_convention;
 201                 pr_info("qcom_scm: convention: %s%s\n",
 202                         qcom_scm_convention_names[qcom_scm_convention],
 203                         forced ? " (forced)" : "");
 204         }
 205         spin_unlock_irqrestore(&scm_query_lock, flags);
 206
 207         return qcom_scm_convention;
 208 }
 209
 210 /**
 211  * qcom_scm_call() - Invoke a syscall in the secure world
 212  * @dev:        device
 213  * @desc:       Descriptor structure containing arguments and return values
 214  * @res:        Structure containing results from SMC/HVC call
 215  *
 216  * Sends a command to the SCM and waits for the command to finish processing.
 217  * This should *only* be called in pre-emptible context.
 218  */
 219 static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
 220                          struct qcom_scm_res *res)
 221 {
 222         might_sleep();
 223         switch (__get_convention()) {
 224         case SMC_CONVENTION_ARM_32:
 225         case SMC_CONVENTION_ARM_64:
 226                 return scm_smc_call(dev, desc, res, false);
 227         case SMC_CONVENTION_LEGACY:
 228                 return scm_legacy_call(dev, desc, res);
 229         default:
 230                 pr_err("Unknown current SCM calling convention.\n");
 231                 return -EINVAL;
 232         }
 233 }
 234
 235 /**
 236  * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
 237  * @dev:        device
 238  * @desc:       Descriptor structure containing arguments and return values
 239  * @res:        Structure containing results from SMC/HVC call
 240  *
 241  * Sends a command to the SCM and waits for the command to finish processing.
 242  * This can be called in atomic context.
 243  */
 244 static int qcom_scm_call_atomic(struct device *dev,
 245                                 const struct qcom_scm_desc *desc,
 246                                 struct qcom_scm_res *res)
 247 {
 248         switch (__get_convention()) {
 249         case SMC_CONVENTION_ARM_32:
 250         case SMC_CONVENTION_ARM_64:
 251                 return scm_smc_call(dev, desc, res, true);
 252         case SMC_CONVENTION_LEGACY:
 253                 return scm_legacy_call_atomic(dev, desc, res);
 254         default:
 255                 pr_err("Unknown current SCM calling convention.\n");
 256                 return -EINVAL;
 257         }
 258 }
 259
 260 static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
 261                                          u32 cmd_id)
 262 {
 263         int ret;
 264         struct qcom_scm_desc desc = {
 265                 .svc = QCOM_SCM_SVC_INFO,
 266                 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
 267                 .owner = ARM_SMCCC_OWNER_SIP,
 268         };
 269         struct qcom_scm_res res;
 270
 271         desc.arginfo = QCOM_SCM_ARGS(1);
 272         switch (__get_convention()) {
 273         case SMC_CONVENTION_ARM_32:
 274         case SMC_CONVENTION_ARM_64:
 275                 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
 276                                 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
 277                 break;
 278         case SMC_CONVENTION_LEGACY:
 279                 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
 280                 break;
 281         default:
 282                 pr_err("Unknown SMC convention being used\n");
 283                 return false;
 284         }
 285
 286         ret = qcom_scm_call(dev, &desc, &res);
 287
 288         return ret ? false : !!res.result[0];
 289 }
 290
 291 static int qcom_scm_set_boot_addr(void *entry, const u8 *cpu_bits)
 292 {
 293         int cpu;
 294         unsigned int flags = 0;
 295         struct qcom_scm_desc desc = {
 296                 .svc = QCOM_SCM_SVC_BOOT,
 297                 .cmd = QCOM_SCM_BOOT_SET_ADDR,
 298                 .arginfo = QCOM_SCM_ARGS(2),
 299                 .owner = ARM_SMCCC_OWNER_SIP,
 300         };
 301
 302         for_each_present_cpu(cpu) {
 303                 if (cpu >= QCOM_SCM_BOOT_MAX_CPUS)
 304                         return -EINVAL;
 305                 flags |= cpu_bits[cpu];
 306         }
 307
 308         desc.args[0] = flags;
 309         desc.args[1] = virt_to_phys(entry);
 310
 311         return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
 312 }
 313
 314 static int qcom_scm_set_boot_addr_mc(void *entry, unsigned int flags)
 315 {
 316         struct qcom_scm_desc desc = {
 317                 .svc = QCOM_SCM_SVC_BOOT,
 318                 .cmd = QCOM_SCM_BOOT_SET_ADDR_MC,
 319                 .owner = ARM_SMCCC_OWNER_SIP,
 320                 .arginfo = QCOM_SCM_ARGS(6),
 321                 .args = {
 322                         virt_to_phys(entry),
 323                         /* Apply to all CPUs in all affinity levels */
 324                         ~0ULL, ~0ULL, ~0ULL, ~0ULL,
 325                         flags,
 326                 },
 327         };
 328
 329         /* Need a device for DMA of the additional arguments */
 330         if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY)
 331                 return -EOPNOTSUPP;
 332
 333         return qcom_scm_call(__scm->dev, &desc, NULL);
 334 }
 335
 336 /**
 337  * qcom_scm_set_warm_boot_addr() - Set the warm boot address for all cpus
 338  * @entry: Entry point function for the cpus
 339  *
 340  * Set the Linux entry point for the SCM to transfer control to when coming
 341  * out of a power down. CPU power down may be executed on cpuidle or hotplug.
 342  */
 343 int qcom_scm_set_warm_boot_addr(void *entry)
 344 {
 345         if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT))
 346                 /* Fallback to old SCM call */
 347                 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits);
 348         return 0;
 349 }
 350 EXPORT_SYMBOL_GPL(qcom_scm_set_warm_boot_addr);
 351
 352 /**
 353  * qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus
 354  * @entry: Entry point function for the cpus
 355  */
 356 int qcom_scm_set_cold_boot_addr(void *entry)
 357 {
 358         if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT))
 359                 /* Fallback to old SCM call */
 360                 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits);
 361         return 0;
 362 }
 363 EXPORT_SYMBOL_GPL(qcom_scm_set_cold_boot_addr);
 364
 365 /**
 366  * qcom_scm_cpu_power_down() - Power down the cpu
 367  * @flags:      Flags to flush cache
 368  *
 369  * This is an end point to power down cpu. If there was a pending interrupt,
 370  * the control would return from this function, otherwise, the cpu jumps to the
 371  * warm boot entry point set for this cpu upon reset.
 372  */
 373 void qcom_scm_cpu_power_down(u32 flags)
 374 {
 375         struct qcom_scm_desc desc = {
 376                 .svc = QCOM_SCM_SVC_BOOT,
 377                 .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
 378                 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
 379                 .arginfo = QCOM_SCM_ARGS(1),
 380                 .owner = ARM_SMCCC_OWNER_SIP,
 381         };
 382
 383         qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
 384 }
 385 EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down);
 386
 387 int qcom_scm_set_remote_state(u32 state, u32 id)
 388 {
 389         struct qcom_scm_desc desc = {
 390                 .svc = QCOM_SCM_SVC_BOOT,
 391                 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
 392                 .arginfo = QCOM_SCM_ARGS(2),
 393                 .args[0] = state,
 394                 .args[1] = id,
 395                 .owner = ARM_SMCCC_OWNER_SIP,
 396         };
 397         struct qcom_scm_res res;
 398         int ret;
 399
 400         ret = qcom_scm_call(__scm->dev, &desc, &res);
 401
 402         return ret ? : res.result[0];
 403 }
 404 EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
 405
 406 static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
 407 {
 408         struct qcom_scm_desc desc = {
 409                 .svc = QCOM_SCM_SVC_BOOT,
 410                 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
 411                 .arginfo = QCOM_SCM_ARGS(2),
 412                 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
 413                 .owner = ARM_SMCCC_OWNER_SIP,
 414         };
 415
 416         desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
 417
 418         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 419 }
 420
 421 static void qcom_scm_set_download_mode(bool enable)
 422 {
 423         bool avail;
 424         int ret = 0;
 425
 426         avail = __qcom_scm_is_call_available(__scm->dev,
 427                                              QCOM_SCM_SVC_BOOT,
 428                                              QCOM_SCM_BOOT_SET_DLOAD_MODE);
 429         if (avail) {
 430                 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
 431         } else if (__scm->dload_mode_addr) {
 432                 ret = qcom_scm_io_writel(__scm->dload_mode_addr,
 433                                 enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
 434         } else {
 435                 dev_err(__scm->dev,
 436                         "No available mechanism for setting download mode\n");
 437         }
 438
 439         if (ret)
 440                 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
 441 }
 442
 443 /**
 444  * qcom_scm_pas_init_image() - Initialize peripheral authentication service
 445  *                             state machine for a given peripheral, using the
 446  *                             metadata
 447  * @peripheral: peripheral id
 448  * @metadata:   pointer to memory containing ELF header, program header table
 449  *              and optional blob of data used for authenticating the metadata
 450  *              and the rest of the firmware
 451  * @size:       size of the metadata
 452  * @ctx:        optional metadata context
 453  *
 454  * Return: 0 on success.
 455  *
 456  * Upon successful return, the PAS metadata context (@ctx) will be used to
 457  * track the metadata allocation, this needs to be released by invoking
 458  * qcom_scm_pas_metadata_release() by the caller.
 459  */
 460 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
 461                             struct qcom_scm_pas_metadata *ctx)
 462 {
 463         dma_addr_t mdata_phys;
 464         void *mdata_buf;
 465         int ret;
 466         struct qcom_scm_desc desc = {
 467                 .svc = QCOM_SCM_SVC_PIL,
 468                 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
 469                 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
 470                 .args[0] = peripheral,
 471                 .owner = ARM_SMCCC_OWNER_SIP,
 472         };
 473         struct qcom_scm_res res;
 474
 475         /*
 476          * During the scm call memory protection will be enabled for the meta
 477          * data blob, so make sure it's physically contiguous, 4K aligned and
 478          * non-cachable to avoid XPU violations.
 479          */
 480         mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
 481                                        GFP_KERNEL);
 482         if (!mdata_buf) {
 483                 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
 484                 return -ENOMEM;
 485         }
 486         memcpy(mdata_buf, metadata, size);
 487
 488         ret = qcom_scm_clk_enable();
 489         if (ret)
 490                 goto out;
 491
 492         ret = qcom_scm_bw_enable();
 493         if (ret)
 494                 return ret;
 495
 496         desc.args[1] = mdata_phys;
 497
 498         ret = qcom_scm_call(__scm->dev, &desc, &res);
 499
 500         qcom_scm_bw_disable();
 501         qcom_scm_clk_disable();
 502
 503 out:
 504         if (ret < 0 || !ctx) {
 505                 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
 506         } else if (ctx) {
 507                 ctx->ptr = mdata_buf;
 508                 ctx->phys = mdata_phys;
 509                 ctx->size = size;
 510         }
 511
 512         return ret ? : res.result[0];
 513 }
 514 EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
 515
 516 /**
 517  * qcom_scm_pas_metadata_release() - release metadata context
 518  * @ctx:        metadata context
 519  */
 520 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx)
 521 {
 522         if (!ctx->ptr)
 523                 return;
 524
 525         dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys);
 526
 527         ctx->ptr = NULL;
 528         ctx->phys = 0;
 529         ctx->size = 0;
 530 }
 531 EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
 532
 533 /**
 534  * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
 535  *                            for firmware loading
 536  * @peripheral: peripheral id
 537  * @addr:       start address of memory area to prepare
 538  * @size:       size of the memory area to prepare
 539  *
 540  * Returns 0 on success.
 541  */
 542 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
 543 {
 544         int ret;
 545         struct qcom_scm_desc desc = {
 546                 .svc = QCOM_SCM_SVC_PIL,
 547                 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
 548                 .arginfo = QCOM_SCM_ARGS(3),
 549                 .args[0] = peripheral,
 550                 .args[1] = addr,
 551                 .args[2] = size,
 552                 .owner = ARM_SMCCC_OWNER_SIP,
 553         };
 554         struct qcom_scm_res res;
 555
 556         ret = qcom_scm_clk_enable();
 557         if (ret)
 558                 return ret;
 559
 560         ret = qcom_scm_bw_enable();
 561         if (ret)
 562                 return ret;
 563
 564         ret = qcom_scm_call(__scm->dev, &desc, &res);
 565         qcom_scm_bw_disable();
 566         qcom_scm_clk_disable();
 567
 568         return ret ? : res.result[0];
 569 }
 570 EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
 571
 572 /**
 573  * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
 574  *                                 and reset the remote processor
 575  * @peripheral: peripheral id
 576  *
 577  * Return 0 on success.
 578  */
 579 int qcom_scm_pas_auth_and_reset(u32 peripheral)
 580 {
 581         int ret;
 582         struct qcom_scm_desc desc = {
 583                 .svc = QCOM_SCM_SVC_PIL,
 584                 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
 585                 .arginfo = QCOM_SCM_ARGS(1),
 586                 .args[0] = peripheral,
 587                 .owner = ARM_SMCCC_OWNER_SIP,
 588         };
 589         struct qcom_scm_res res;
 590
 591         ret = qcom_scm_clk_enable();
 592         if (ret)
 593                 return ret;
 594
 595         ret = qcom_scm_bw_enable();
 596         if (ret)
 597                 return ret;
 598
 599         ret = qcom_scm_call(__scm->dev, &desc, &res);
 600         qcom_scm_bw_disable();
 601         qcom_scm_clk_disable();
 602
 603         return ret ? : res.result[0];
 604 }
 605 EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
 606
 607 /**
 608  * qcom_scm_pas_shutdown() - Shut down the remote processor
 609  * @peripheral: peripheral id
 610  *
 611  * Returns 0 on success.
 612  */
 613 int qcom_scm_pas_shutdown(u32 peripheral)
 614 {
 615         int ret;
 616         struct qcom_scm_desc desc = {
 617                 .svc = QCOM_SCM_SVC_PIL,
 618                 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
 619                 .arginfo = QCOM_SCM_ARGS(1),
 620                 .args[0] = peripheral,
 621                 .owner = ARM_SMCCC_OWNER_SIP,
 622         };
 623         struct qcom_scm_res res;
 624
 625         ret = qcom_scm_clk_enable();
 626         if (ret)
 627                 return ret;
 628
 629         ret = qcom_scm_bw_enable();
 630         if (ret)
 631                 return ret;
 632
 633         ret = qcom_scm_call(__scm->dev, &desc, &res);
 634
 635         qcom_scm_bw_disable();
 636         qcom_scm_clk_disable();
 637
 638         return ret ? : res.result[0];
 639 }
 640 EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
 641
 642 /**
 643  * qcom_scm_pas_supported() - Check if the peripheral authentication service is
 644  *                            available for the given peripherial
 645  * @peripheral: peripheral id
 646  *
 647  * Returns true if PAS is supported for this peripheral, otherwise false.
 648  */
 649 bool qcom_scm_pas_supported(u32 peripheral)
 650 {
 651         int ret;
 652         struct qcom_scm_desc desc = {
 653                 .svc = QCOM_SCM_SVC_PIL,
 654                 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
 655                 .arginfo = QCOM_SCM_ARGS(1),
 656                 .args[0] = peripheral,
 657                 .owner = ARM_SMCCC_OWNER_SIP,
 658         };
 659         struct qcom_scm_res res;
 660
 661         if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
 662                                           QCOM_SCM_PIL_PAS_IS_SUPPORTED))
 663                 return false;
 664
 665         ret = qcom_scm_call(__scm->dev, &desc, &res);
 666
 667         return ret ? false : !!res.result[0];
 668 }
 669 EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
 670
 671 static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 672 {
 673         struct qcom_scm_desc desc = {
 674                 .svc = QCOM_SCM_SVC_PIL,
 675                 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
 676                 .arginfo = QCOM_SCM_ARGS(2),
 677                 .args[0] = reset,
 678                 .args[1] = 0,
 679                 .owner = ARM_SMCCC_OWNER_SIP,
 680         };
 681         struct qcom_scm_res res;
 682         int ret;
 683
 684         ret = qcom_scm_call(__scm->dev, &desc, &res);
 685
 686         return ret ? : res.result[0];
 687 }
 688
 689 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
 690                                      unsigned long idx)
 691 {
 692         if (idx != 0)
 693                 return -EINVAL;
 694
 695         return __qcom_scm_pas_mss_reset(__scm->dev, 1);
 696 }
 697
 698 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
 699                                        unsigned long idx)
 700 {
 701         if (idx != 0)
 702                 return -EINVAL;
 703
 704         return __qcom_scm_pas_mss_reset(__scm->dev, 0);
 705 }
 706
 707 static const struct reset_control_ops qcom_scm_pas_reset_ops = {
 708         .assert = qcom_scm_pas_reset_assert,
 709         .deassert = qcom_scm_pas_reset_deassert,
 710 };
 711
 712 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
 713 {
 714         struct qcom_scm_desc desc = {
 715                 .svc = QCOM_SCM_SVC_IO,
 716                 .cmd = QCOM_SCM_IO_READ,
 717                 .arginfo = QCOM_SCM_ARGS(1),
 718                 .args[0] = addr,
 719                 .owner = ARM_SMCCC_OWNER_SIP,
 720         };
 721         struct qcom_scm_res res;
 722         int ret;
 723
 724
 725         ret = qcom_scm_call_atomic(__scm->dev, &desc, &res);
 726         if (ret >= 0)
 727                 *val = res.result[0];
 728
 729         return ret < 0 ? ret : 0;
 730 }
 731 EXPORT_SYMBOL_GPL(qcom_scm_io_readl);
 732
 733 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
 734 {
 735         struct qcom_scm_desc desc = {
 736                 .svc = QCOM_SCM_SVC_IO,
 737                 .cmd = QCOM_SCM_IO_WRITE,
 738                 .arginfo = QCOM_SCM_ARGS(2),
 739                 .args[0] = addr,
 740                 .args[1] = val,
 741                 .owner = ARM_SMCCC_OWNER_SIP,
 742         };
 743
 744         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
 745 }
 746 EXPORT_SYMBOL_GPL(qcom_scm_io_writel);
 747
 748 /**
 749  * qcom_scm_restore_sec_cfg_available() - Check if secure environment
 750  * supports restore security config interface.
 751  *
 752  * Return true if restore-cfg interface is supported, false if not.
 753  */
 754 bool qcom_scm_restore_sec_cfg_available(void)
 755 {
 756         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
 757                                             QCOM_SCM_MP_RESTORE_SEC_CFG);
 758 }
 759 EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available);
 760
 761 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
 762 {
 763         struct qcom_scm_desc desc = {
 764                 .svc = QCOM_SCM_SVC_MP,
 765                 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
 766                 .arginfo = QCOM_SCM_ARGS(2),
 767                 .args[0] = device_id,
 768                 .args[1] = spare,
 769                 .owner = ARM_SMCCC_OWNER_SIP,
 770         };
 771         struct qcom_scm_res res;
 772         int ret;
 773
 774         ret = qcom_scm_call(__scm->dev, &desc, &res);
 775
 776         return ret ? : res.result[0];
 777 }
 778 EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg);
 779
 780 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
 781 {
 782         struct qcom_scm_desc desc = {
 783                 .svc = QCOM_SCM_SVC_MP,
 784                 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
 785                 .arginfo = QCOM_SCM_ARGS(1),
 786                 .args[0] = spare,
 787                 .owner = ARM_SMCCC_OWNER_SIP,
 788         };
 789         struct qcom_scm_res res;
 790         int ret;
 791
 792         ret = qcom_scm_call(__scm->dev, &desc, &res);
 793
 794         if (size)
 795                 *size = res.result[0];
 796
 797         return ret ? : res.result[1];
 798 }
 799 EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_size);
 800
 801 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
 802 {
 803         struct qcom_scm_desc desc = {
 804                 .svc = QCOM_SCM_SVC_MP,
 805                 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
 806                 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
 807                                          QCOM_SCM_VAL),
 808                 .args[0] = addr,
 809                 .args[1] = size,
 810                 .args[2] = spare,
 811                 .owner = ARM_SMCCC_OWNER_SIP,
 812         };
 813         int ret;
 814
 815         ret = qcom_scm_call(__scm->dev, &desc, NULL);
 816
 817         /* the pg table has been initialized already, ignore the error */
 818         if (ret == -EPERM)
 819                 ret = 0;
 820
 821         return ret;
 822 }
 823 EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_init);
 824
 825 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size)
 826 {
 827         struct qcom_scm_desc desc = {
 828                 .svc = QCOM_SCM_SVC_MP,
 829                 .cmd = QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE,
 830                 .arginfo = QCOM_SCM_ARGS(2),
 831                 .args[0] = size,
 832                 .args[1] = spare,
 833                 .owner = ARM_SMCCC_OWNER_SIP,
 834         };
 835
 836         return qcom_scm_call(__scm->dev, &desc, NULL);
 837 }
 838 EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size);
 839
 840 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
 841                                    u32 cp_nonpixel_start,
 842                                    u32 cp_nonpixel_size)
 843 {
 844         int ret;
 845         struct qcom_scm_desc desc = {
 846                 .svc = QCOM_SCM_SVC_MP,
 847                 .cmd = QCOM_SCM_MP_VIDEO_VAR,
 848                 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL,
 849                                          QCOM_SCM_VAL, QCOM_SCM_VAL),
 850                 .args[0] = cp_start,
 851                 .args[1] = cp_size,
 852                 .args[2] = cp_nonpixel_start,
 853                 .args[3] = cp_nonpixel_size,
 854                 .owner = ARM_SMCCC_OWNER_SIP,
 855         };
 856         struct qcom_scm_res res;
 857
 858         ret = qcom_scm_call(__scm->dev, &desc, &res);
 859
 860         return ret ? : res.result[0];
 861 }
 862 EXPORT_SYMBOL_GPL(qcom_scm_mem_protect_video_var);
 863
 864 static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
 865                                  size_t mem_sz, phys_addr_t src, size_t src_sz,
 866                                  phys_addr_t dest, size_t dest_sz)
 867 {
 868         int ret;
 869         struct qcom_scm_desc desc = {
 870                 .svc = QCOM_SCM_SVC_MP,
 871                 .cmd = QCOM_SCM_MP_ASSIGN,
 872                 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
 873                                          QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
 874                                          QCOM_SCM_VAL, QCOM_SCM_VAL),
 875                 .args[0] = mem_region,
 876                 .args[1] = mem_sz,
 877                 .args[2] = src,
 878                 .args[3] = src_sz,
 879                 .args[4] = dest,
 880                 .args[5] = dest_sz,
 881                 .args[6] = 0,
 882                 .owner = ARM_SMCCC_OWNER_SIP,
 883         };
 884         struct qcom_scm_res res;
 885
 886         ret = qcom_scm_call(dev, &desc, &res);
 887
 888         return ret ? : res.result[0];
 889 }
 890
 891 /**
 892  * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
 893  * @mem_addr: mem region whose ownership need to be reassigned
 894  * @mem_sz:   size of the region.
 895  * @srcvm:    vmid for current set of owners, each set bit in
 896  *            flag indicate a unique owner
 897  * @newvm:    array having new owners and corresponding permission
 898  *            flags
 899  * @dest_cnt: number of owners in next set.
 900  *
 901  * Return negative errno on failure or 0 on success with @srcvm updated.
 902  */
 903 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
 904                         u64 *srcvm,
 905                         const struct qcom_scm_vmperm *newvm,
 906                         unsigned int dest_cnt)
 907 {
 908         struct qcom_scm_current_perm_info *destvm;
 909         struct qcom_scm_mem_map_info *mem_to_map;
 910         phys_addr_t mem_to_map_phys;
 911         phys_addr_t dest_phys;
 912         dma_addr_t ptr_phys;
 913         size_t mem_to_map_sz;
 914         size_t dest_sz;
 915         size_t src_sz;
 916         size_t ptr_sz;
 917         int next_vm;
 918         __le32 *src;
 919         void *ptr;
 920         int ret, i, b;
 921         u64 srcvm_bits = *srcvm;
 922
 923         src_sz = hweight64(srcvm_bits) * sizeof(*src);
 924         mem_to_map_sz = sizeof(*mem_to_map);
 925         dest_sz = dest_cnt * sizeof(*destvm);
 926         ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
 927                         ALIGN(dest_sz, SZ_64);
 928
 929         ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
 930         if (!ptr)
 931                 return -ENOMEM;
 932
 933         /* Fill source vmid detail */
 934         src = ptr;
 935         i = 0;
 936         for (b = 0; b < BITS_PER_TYPE(u64); b++) {
 937                 if (srcvm_bits & BIT(b))
 938                         src[i++] = cpu_to_le32(b);
 939         }
 940
 941         /* Fill details of mem buff to map */
 942         mem_to_map = ptr + ALIGN(src_sz, SZ_64);
 943         mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
 944         mem_to_map->mem_addr = cpu_to_le64(mem_addr);
 945         mem_to_map->mem_size = cpu_to_le64(mem_sz);
 946
 947         next_vm = 0;
 948         /* Fill details of next vmid detail */
 949         destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
 950         dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
 951         for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
 952                 destvm->vmid = cpu_to_le32(newvm->vmid);
 953                 destvm->perm = cpu_to_le32(newvm->perm);
 954                 destvm->ctx = 0;
 955                 destvm->ctx_size = 0;
 956                 next_vm |= BIT(newvm->vmid);
 957         }
 958
 959         ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
 960                                     ptr_phys, src_sz, dest_phys, dest_sz);
 961         dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
 962         if (ret) {
 963                 dev_err(__scm->dev,
 964                         "Assign memory protection call failed %d\n", ret);
 965                 return -EINVAL;
 966         }
 967
 968         *srcvm = next_vm;
 969         return 0;
 970 }
 971 EXPORT_SYMBOL_GPL(qcom_scm_assign_mem);
 972
 973 /**
 974  * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
 975  */
 976 bool qcom_scm_ocmem_lock_available(void)
 977 {
 978         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
 979                                             QCOM_SCM_OCMEM_LOCK_CMD);
 980 }
 981 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available);
 982
 983 /**
 984  * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
 985  * region to the specified initiator
 986  *
 987  * @id:     tz initiator id
 988  * @offset: OCMEM offset
 989  * @size:   OCMEM size
 990  * @mode:   access mode (WIDE/NARROW)
 991  */
 992 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
 993                         u32 mode)
 994 {
 995         struct qcom_scm_desc desc = {
 996                 .svc = QCOM_SCM_SVC_OCMEM,
 997                 .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
 998                 .args[0] = id,
 999                 .args[1] = offset,
1000                 .args[2] = size,
1001                 .args[3] = mode,
1002                 .arginfo = QCOM_SCM_ARGS(4),
1003         };
1004
1005         return qcom_scm_call(__scm->dev, &desc, NULL);
1006 }
1007 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock);
1008
1009 /**
1010  * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
1011  * region from the specified initiator
1012  *
1013  * @id:     tz initiator id
1014  * @offset: OCMEM offset
1015  * @size:   OCMEM size
1016  */
1017 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
1018 {
1019         struct qcom_scm_desc desc = {
1020                 .svc = QCOM_SCM_SVC_OCMEM,
1021                 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
1022                 .args[0] = id,
1023                 .args[1] = offset,
1024                 .args[2] = size,
1025                 .arginfo = QCOM_SCM_ARGS(3),
1026         };
1027
1028         return qcom_scm_call(__scm->dev, &desc, NULL);
1029 }
1030 EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock);
1031
1032 /**
1033  * qcom_scm_ice_available() - Is the ICE key programming interface available?
1034  *
1035  * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and
1036  *         qcom_scm_ice_set_key() are available.
1037  */
1038 bool qcom_scm_ice_available(void)
1039 {
1040         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
1041                                             QCOM_SCM_ES_INVALIDATE_ICE_KEY) &&
1042                 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
1043                                              QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
1044 }
1045 EXPORT_SYMBOL_GPL(qcom_scm_ice_available);
1046
1047 /**
1048  * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
1049  * @index: the keyslot to invalidate
1050  *
1051  * The UFSHCI and eMMC standards define a standard way to do this, but it
1052  * doesn't work on these SoCs; only this SCM call does.
1053  *
1054  * It is assumed that the SoC has only one ICE instance being used, as this SCM
1055  * call doesn't specify which ICE instance the keyslot belongs to.
1056  *
1057  * Return: 0 on success; -errno on failure.
1058  */
1059 int qcom_scm_ice_invalidate_key(u32 index)
1060 {
1061         struct qcom_scm_desc desc = {
1062                 .svc = QCOM_SCM_SVC_ES,
1063                 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY,
1064                 .arginfo = QCOM_SCM_ARGS(1),
1065                 .args[0] = index,
1066                 .owner = ARM_SMCCC_OWNER_SIP,
1067         };
1068
1069         return qcom_scm_call(__scm->dev, &desc, NULL);
1070 }
1071 EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key);
1072
1073 /**
1074  * qcom_scm_ice_set_key() - Set an inline encryption key
1075  * @index: the keyslot into which to set the key
1076  * @key: the key to program
1077  * @key_size: the size of the key in bytes
1078  * @cipher: the encryption algorithm the key is for
1079  * @data_unit_size: the encryption data unit size, i.e. the size of each
1080  *                  individual plaintext and ciphertext.  Given in 512-byte
1081  *                  units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
1082  *
1083  * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
1084  * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline.
1085  *
1086  * The UFSHCI and eMMC standards define a standard way to do this, but it
1087  * doesn't work on these SoCs; only this SCM call does.
1088  *
1089  * It is assumed that the SoC has only one ICE instance being used, as this SCM
1090  * call doesn't specify which ICE instance the keyslot belongs to.
1091  *
1092  * Return: 0 on success; -errno on failure.
1093  */
1094 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
1095                          enum qcom_scm_ice_cipher cipher, u32 data_unit_size)
1096 {
1097         struct qcom_scm_desc desc = {
1098                 .svc = QCOM_SCM_SVC_ES,
1099                 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY,
1100                 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW,
1101                                          QCOM_SCM_VAL, QCOM_SCM_VAL,
1102                                          QCOM_SCM_VAL),
1103                 .args[0] = index,
1104                 .args[2] = key_size,
1105                 .args[3] = cipher,
1106                 .args[4] = data_unit_size,
1107                 .owner = ARM_SMCCC_OWNER_SIP,
1108         };
1109         void *keybuf;
1110         dma_addr_t key_phys;
1111         int ret;
1112
1113         /*
1114          * 'key' may point to vmalloc()'ed memory, but we need to pass a
1115          * physical address that's been properly flushed.  The sanctioned way to
1116          * do this is by using the DMA API.  But as is best practice for crypto
1117          * keys, we also must wipe the key after use.  This makes kmemdup() +
1118          * dma_map_single() not clearly correct, since the DMA API can use
1119          * bounce buffers.  Instead, just use dma_alloc_coherent().  Programming
1120          * keys is normally rare and thus not performance-critical.
1121          */
1122
1123         keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys,
1124                                     GFP_KERNEL);
1125         if (!keybuf)
1126                 return -ENOMEM;
1127         memcpy(keybuf, key, key_size);
1128         desc.args[1] = key_phys;
1129
1130         ret = qcom_scm_call(__scm->dev, &desc, NULL);
1131
1132         memzero_explicit(keybuf, key_size);
1133
1134         dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
1135         return ret;
1136 }
1137 EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key);
1138
1139 /**
1140  * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
1141  *
1142  * Return true if HDCP is supported, false if not.
1143  */
1144 bool qcom_scm_hdcp_available(void)
1145 {
1146         bool avail;
1147         int ret = qcom_scm_clk_enable();
1148
1149         if (ret)
1150                 return ret;
1151
1152         avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
1153                                                 QCOM_SCM_HDCP_INVOKE);
1154
1155         qcom_scm_clk_disable();
1156
1157         return avail;
1158 }
1159 EXPORT_SYMBOL_GPL(qcom_scm_hdcp_available);
1160
1161 /**
1162  * qcom_scm_hdcp_req() - Send HDCP request.
1163  * @req: HDCP request array
1164  * @req_cnt: HDCP request array count
1165  * @resp: response buffer passed to SCM
1166  *
1167  * Write HDCP register(s) through SCM.
1168  */
1169 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
1170 {
1171         int ret;
1172         struct qcom_scm_desc desc = {
1173                 .svc = QCOM_SCM_SVC_HDCP,
1174                 .cmd = QCOM_SCM_HDCP_INVOKE,
1175                 .arginfo = QCOM_SCM_ARGS(10),
1176                 .args = {
1177                         req[0].addr,
1178                         req[0].val,
1179                         req[1].addr,
1180                         req[1].val,
1181                         req[2].addr,
1182                         req[2].val,
1183                         req[3].addr,
1184                         req[3].val,
1185                         req[4].addr,
1186                         req[4].val
1187                 },
1188                 .owner = ARM_SMCCC_OWNER_SIP,
1189         };
1190         struct qcom_scm_res res;
1191
1192         if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
1193                 return -ERANGE;
1194
1195         ret = qcom_scm_clk_enable();
1196         if (ret)
1197                 return ret;
1198
1199         ret = qcom_scm_call(__scm->dev, &desc, &res);
1200         *resp = res.result[0];
1201
1202         qcom_scm_clk_disable();
1203
1204         return ret;
1205 }
1206 EXPORT_SYMBOL_GPL(qcom_scm_hdcp_req);
1207
1208 int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt)
1209 {
1210         struct qcom_scm_desc desc = {
1211                 .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
1212                 .cmd = QCOM_SCM_SMMU_PT_FORMAT,
1213                 .arginfo = QCOM_SCM_ARGS(3),
1214                 .args[0] = sec_id,
1215                 .args[1] = ctx_num,
1216                 .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */
1217                 .owner = ARM_SMCCC_OWNER_SIP,
1218         };
1219
1220         return qcom_scm_call(__scm->dev, &desc, NULL);
1221 }
1222 EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format);
1223
1224 int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
1225 {
1226         struct qcom_scm_desc desc = {
1227                 .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
1228                 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
1229                 .arginfo = QCOM_SCM_ARGS(2),
1230                 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
1231                 .args[1] = en,
1232                 .owner = ARM_SMCCC_OWNER_SIP,
1233         };
1234
1235
1236         return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
1237 }
1238 EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle);
1239
1240 bool qcom_scm_lmh_dcvsh_available(void)
1241 {
1242         return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
1243 }
1244 EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available);
1245
1246 int qcom_scm_lmh_profile_change(u32 profile_id)
1247 {
1248         struct qcom_scm_desc desc = {
1249                 .svc = QCOM_SCM_SVC_LMH,
1250                 .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE,
1251                 .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
1252                 .args[0] = profile_id,
1253                 .owner = ARM_SMCCC_OWNER_SIP,
1254         };
1255
1256         return qcom_scm_call(__scm->dev, &desc, NULL);
1257 }
1258 EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change);
1259
1260 int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
1261                        u64 limit_node, u32 node_id, u64 version)
1262 {
1263         dma_addr_t payload_phys;
1264         u32 *payload_buf;
1265         int ret, payload_size = 5 * sizeof(u32);
1266
1267         struct qcom_scm_desc desc = {
1268                 .svc = QCOM_SCM_SVC_LMH,
1269                 .cmd = QCOM_SCM_LMH_LIMIT_DCVSH,
1270                 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL,
1271                                         QCOM_SCM_VAL, QCOM_SCM_VAL),
1272                 .args[1] = payload_size,
1273                 .args[2] = limit_node,
1274                 .args[3] = node_id,
1275                 .args[4] = version,
1276                 .owner = ARM_SMCCC_OWNER_SIP,
1277         };
1278
1279         payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL);
1280         if (!payload_buf)
1281                 return -ENOMEM;
1282
1283         payload_buf[0] = payload_fn;
1284         payload_buf[1] = 0;
1285         payload_buf[2] = payload_reg;
1286         payload_buf[3] = 1;
1287         payload_buf[4] = payload_val;
1288
1289         desc.args[0] = payload_phys;
1290
1291         ret = qcom_scm_call(__scm->dev, &desc, NULL);
1292
1293         dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys);
1294         return ret;
1295 }
1296 EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
1297
1298 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1299 {
1300         struct device_node *tcsr;
1301         struct device_node *np = dev->of_node;
1302         struct resource res;
1303         u32 offset;
1304         int ret;
1305
1306         tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
1307         if (!tcsr)
1308                 return 0;
1309
1310         ret = of_address_to_resource(tcsr, 0, &res);
1311         of_node_put(tcsr);
1312         if (ret)
1313                 return ret;
1314
1315         ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
1316         if (ret < 0)
1317                 return ret;
1318
1319         *addr = res.start + offset;
1320
1321         return 0;
1322 }
1323
1324 /**
1325  * qcom_scm_is_available() - Checks if SCM is available
1326  */
1327 bool qcom_scm_is_available(void)
1328 {
1329         return !!__scm;
1330 }
1331 EXPORT_SYMBOL_GPL(qcom_scm_is_available);
1332
1333 static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx)
1334 {
1335         /* FW currently only supports a single wq_ctx (zero).
1336          * TODO: Update this logic to include dynamic allocation and lookup of
1337          * completion structs when FW supports more wq_ctx values.
1338          */
1339         if (wq_ctx != 0) {
1340                 dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n");
1341                 return -EINVAL;
1342         }
1343
1344         return 0;
1345 }
1346
1347 int qcom_scm_wait_for_wq_completion(u32 wq_ctx)
1348 {
1349         int ret;
1350
1351         ret = qcom_scm_assert_valid_wq_ctx(wq_ctx);
1352         if (ret)
1353                 return ret;
1354
1355         wait_for_completion(&__scm->waitq_comp);
1356
1357         return 0;
1358 }
1359
1360 static int qcom_scm_waitq_wakeup(struct qcom_scm *scm, unsigned int wq_ctx)
1361 {
1362         int ret;
1363
1364         ret = qcom_scm_assert_valid_wq_ctx(wq_ctx);
1365         if (ret)
1366                 return ret;
1367
1368         complete(&__scm->waitq_comp);
1369
1370         return 0;
1371 }
1372
1373 static irqreturn_t qcom_scm_irq_handler(int irq, void *data)
1374 {
1375         int ret;
1376         struct qcom_scm *scm = data;
1377         u32 wq_ctx, flags, more_pending = 0;
1378
1379         do {
1380                 ret = scm_get_wq_ctx(&wq_ctx, &flags, &more_pending);
1381                 if (ret) {
1382                         dev_err(scm->dev, "GET_WQ_CTX SMC call failed: %d\n", ret);
1383                         goto out;
1384                 }
1385
1386                 if (flags != QCOM_SMC_WAITQ_FLAG_WAKE_ONE &&
1387                     flags != QCOM_SMC_WAITQ_FLAG_WAKE_ALL) {
1388                         dev_err(scm->dev, "Invalid flags found for wq_ctx: %u\n", flags);
1389                         goto out;
1390                 }
1391
1392                 ret = qcom_scm_waitq_wakeup(scm, wq_ctx);
1393                 if (ret)
1394                         goto out;
1395         } while (more_pending);
1396
1397 out:
1398         return IRQ_HANDLED;
1399 }
1400
1401 static int qcom_scm_probe(struct platform_device *pdev)
1402 {
1403         struct qcom_scm *scm;
1404         int irq, ret;
1405
1406         scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
1407         if (!scm)
1408                 return -ENOMEM;
1409
1410         ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
1411         if (ret < 0)
1412                 return ret;
1413
1414         mutex_init(&scm->scm_bw_lock);
1415
1416         scm->path = devm_of_icc_get(&pdev->dev, NULL);
1417         if (IS_ERR(scm->path))
1418                 return dev_err_probe(&pdev->dev, PTR_ERR(scm->path),
1419                                      "failed to acquire interconnect path\n");
1420
1421         scm->core_clk = devm_clk_get_optional(&pdev->dev, "core");
1422         if (IS_ERR(scm->core_clk))
1423                 return PTR_ERR(scm->core_clk);
1424
1425         scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface");
1426         if (IS_ERR(scm->iface_clk))
1427                 return PTR_ERR(scm->iface_clk);
1428
1429         scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
1430         if (IS_ERR(scm->bus_clk))
1431                 return PTR_ERR(scm->bus_clk);
1432
1433         scm->reset.ops = &qcom_scm_pas_reset_ops;
1434         scm->reset.nr_resets = 1;
1435         scm->reset.of_node = pdev->dev.of_node;
1436         ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
1437         if (ret)
1438                 return ret;
1439
1440         /* vote for max clk rate for highest performance */
1441         ret = clk_set_rate(scm->core_clk, INT_MAX);
1442         if (ret)
1443                 return ret;
1444
1445         __scm = scm;
1446         __scm->dev = &pdev->dev;
1447
1448         init_completion(&__scm->waitq_comp);
1449
1450         irq = platform_get_irq_optional(pdev, 0);
1451         if (irq < 0) {
1452                 if (irq != -ENXIO)
1453                         return irq;
1454         } else {
1455                 ret = devm_request_threaded_irq(__scm->dev, irq, NULL, qcom_scm_irq_handler,
1456                                                 IRQF_ONESHOT, "qcom-scm", __scm);
1457                 if (ret < 0)
1458                         return dev_err_probe(scm->dev, ret, "Failed to request qcom-scm irq\n");
1459         }
1460
1461         __get_convention();
1462
1463         /*
1464          * If requested enable "download mode", from this point on warmboot
1465          * will cause the boot stages to enter download mode, unless
1466          * disabled below by a clean shutdown/reboot.
1467          */
1468         if (download_mode)
1469                 qcom_scm_set_download_mode(true);
1470
1471         return 0;
1472 }
1473
1474 static void qcom_scm_shutdown(struct platform_device *pdev)
1475 {
1476         /* Clean shutdown, disable download mode to allow normal restart */
1477         qcom_scm_set_download_mode(false);
1478 }
1479
1480 static const struct of_device_id qcom_scm_dt_match[] = {
1481         { .compatible = "qcom,scm" },
1482
1483         /* Legacy entries kept for backwards compatibility */
1484         { .compatible = "qcom,scm-apq8064" },
1485         { .compatible = "qcom,scm-apq8084" },
1486         { .compatible = "qcom,scm-ipq4019" },
1487         { .compatible = "qcom,scm-msm8953" },
1488         { .compatible = "qcom,scm-msm8974" },
1489         { .compatible = "qcom,scm-msm8996" },
1490         {}
1491 };
1492 MODULE_DEVICE_TABLE(of, qcom_scm_dt_match);
1493
1494 static struct platform_driver qcom_scm_driver = {
1495         .driver = {
1496                 .name   = "qcom_scm",
1497                 .of_match_table = qcom_scm_dt_match,
1498                 .suppress_bind_attrs = true,
1499         },
1500         .probe = qcom_scm_probe,
1501         .shutdown = qcom_scm_shutdown,
1502 };
1503
1504 static int __init qcom_scm_init(void)
1505 {
1506         return platform_driver_register(&qcom_scm_driver);
1507 }
1508 subsys_initcall(qcom_scm_init);
1509
1510 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver");
1511 MODULE_LICENSE("GPL v2");