drivers/firmware/qcom_scm-smc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <linux/io.h>
   6 #include <linux/errno.h>
   7 #include <linux/delay.h>
   8 #include <linux/mutex.h>
   9 #include <linux/slab.h>
  10 #include <linux/types.h>
  11 #include <linux/firmware/qcom/qcom_scm.h>
  12 #include <linux/arm-smccc.h>
  13 #include <linux/dma-mapping.h>
  14
  15 #include "qcom_scm.h"
  16
  17 /**
  18  * struct arm_smccc_args
  19  * @args:       The array of values used in registers in smc instruction
  20  */
  21 struct arm_smccc_args {
  22         unsigned long args[8];
  23 };
  24
  25 static DEFINE_MUTEX(qcom_scm_lock);
  26
  27 #define QCOM_SCM_EBUSY_WAIT_MS 30
  28 #define QCOM_SCM_EBUSY_MAX_RETRY 20
  29
  30 #define SCM_SMC_N_REG_ARGS      4
  31 #define SCM_SMC_FIRST_EXT_IDX   (SCM_SMC_N_REG_ARGS - 1)
  32 #define SCM_SMC_N_EXT_ARGS      (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
  33 #define SCM_SMC_FIRST_REG_IDX   2
  34 #define SCM_SMC_LAST_REG_IDX    (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
  35
  36 static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
  37                                struct arm_smccc_res *res)
  38 {
  39         unsigned long a0 = smc->args[0];
  40         struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
  41
  42         quirk.state.a6 = 0;
  43
  44         do {
  45                 arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
  46                                     smc->args[3], smc->args[4], smc->args[5],
  47                                     quirk.state.a6, smc->args[7], res, &quirk);
  48
  49                 if (res->a0 == QCOM_SCM_INTERRUPTED)
  50                         a0 = res->a0;
  51
  52         } while (res->a0 == QCOM_SCM_INTERRUPTED);
  53 }
  54
  55 static void fill_wq_resume_args(struct arm_smccc_args *resume, u32 smc_call_ctx)
  56 {
  57         memset(resume->args, 0, sizeof(resume->args[0]) * ARRAY_SIZE(resume->args));
  58
  59         resume->args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
  60                                         ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
  61                                         SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_RESUME));
  62
  63         resume->args[1] = QCOM_SCM_ARGS(1);
  64
  65         resume->args[2] = smc_call_ctx;
  66 }
  67
  68 int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending)
  69 {
  70         int ret;
  71         struct arm_smccc_res get_wq_res;
  72         struct arm_smccc_args get_wq_ctx = {0};
  73
  74         get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
  75                                 ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
  76                                 SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_WQ_CTX));
  77
  78         /* Guaranteed to return only success or error, no WAITQ_* */
  79         __scm_smc_do_quirk(&get_wq_ctx, &get_wq_res);
  80         ret = get_wq_res.a0;
  81         if (ret)
  82                 return ret;
  83
  84         *wq_ctx = get_wq_res.a1;
  85         *flags  = get_wq_res.a2;
  86         *more_pending = get_wq_res.a3;
  87
  88         return 0;
  89 }
  90
  91 static int __scm_smc_do_quirk_handle_waitq(struct device *dev, struct arm_smccc_args *waitq,
  92                                            struct arm_smccc_res *res)
  93 {
  94         int ret;
  95         u32 wq_ctx, smc_call_ctx;
  96         struct arm_smccc_args resume;
  97         struct arm_smccc_args *smc = waitq;
  98
  99         do {
 100                 __scm_smc_do_quirk(smc, res);
 101
 102                 if (res->a0 == QCOM_SCM_WAITQ_SLEEP) {
 103                         wq_ctx = res->a1;
 104                         smc_call_ctx = res->a2;
 105
 106                         ret = qcom_scm_wait_for_wq_completion(wq_ctx);
 107                         if (ret)
 108                                 return ret;
 109
 110                         fill_wq_resume_args(&resume, smc_call_ctx);
 111                         smc = &resume;
 112                 }
 113         } while (res->a0 == QCOM_SCM_WAITQ_SLEEP);
 114
 115         return 0;
 116 }
 117
 118 static int __scm_smc_do(struct device *dev, struct arm_smccc_args *smc,
 119                         struct arm_smccc_res *res, bool atomic)
 120 {
 121         int ret, retry_count = 0;
 122
 123         if (atomic) {
 124                 __scm_smc_do_quirk(smc, res);
 125                 return 0;
 126         }
 127
 128         do {
 129                 mutex_lock(&qcom_scm_lock);
 130
 131                 ret = __scm_smc_do_quirk_handle_waitq(dev, smc, res);
 132
 133                 mutex_unlock(&qcom_scm_lock);
 134
 135                 if (ret)
 136                         return ret;
 137
 138                 if (res->a0 == QCOM_SCM_V2_EBUSY) {
 139                         if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
 140                                 break;
 141                         msleep(QCOM_SCM_EBUSY_WAIT_MS);
 142                 }
 143         }  while (res->a0 == QCOM_SCM_V2_EBUSY);
 144
 145         return 0;
 146 }
 147
 148
 149 int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
 150                    enum qcom_scm_convention qcom_convention,
 151                    struct qcom_scm_res *res, bool atomic)
 152 {
 153         int arglen = desc->arginfo & 0xf;
 154         int i, ret;
 155         dma_addr_t args_phys = 0;
 156         void *args_virt = NULL;
 157         size_t alloc_len;
 158         gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
 159         u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
 160         u32 qcom_smccc_convention = (qcom_convention == SMC_CONVENTION_ARM_32) ?
 161                                     ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
 162         struct arm_smccc_res smc_res;
 163         struct arm_smccc_args smc = {0};
 164
 165         smc.args[0] = ARM_SMCCC_CALL_VAL(
 166                 smccc_call_type,
 167                 qcom_smccc_convention,
 168                 desc->owner,
 169                 SCM_SMC_FNID(desc->svc, desc->cmd));
 170         smc.args[1] = desc->arginfo;
 171         for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
 172                 smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
 173
 174         if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
 175                 alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
 176                 args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
 177
 178                 if (!args_virt)
 179                         return -ENOMEM;
 180
 181                 if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
 182                         __le32 *args = args_virt;
 183
 184                         for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
 185                                 args[i] = cpu_to_le32(desc->args[i +
 186                                                       SCM_SMC_FIRST_EXT_IDX]);
 187                 } else {
 188                         __le64 *args = args_virt;
 189
 190                         for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
 191                                 args[i] = cpu_to_le64(desc->args[i +
 192                                                       SCM_SMC_FIRST_EXT_IDX]);
 193                 }
 194
 195                 args_phys = dma_map_single(dev, args_virt, alloc_len,
 196                                            DMA_TO_DEVICE);
 197
 198                 if (dma_mapping_error(dev, args_phys)) {
 199                         kfree(args_virt);
 200                         return -ENOMEM;
 201                 }
 202
 203                 smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
 204         }
 205
 206         /* ret error check follows after args_virt cleanup*/
 207         ret = __scm_smc_do(dev, &smc, &smc_res, atomic);
 208
 209         if (args_virt) {
 210                 dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
 211                 kfree(args_virt);
 212         }
 213
 214         if (ret)
 215                 return ret;
 216
 217         if (res) {
 218                 res->result[0] = smc_res.a1;
 219                 res->result[1] = smc_res.a2;
 220                 res->result[2] = smc_res.a3;
 221         }
 222
 223         return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
 224
 225 }