drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49 #include <asm/system.h>
  50
  51 #ifdef CONFIG_PPC_PMAC
  52 #include <asm/pmac_feature.h>
  53 #endif
  54
  55 #include "core.h"
  56 #include "ohci.h"
  57
  58 #define DESCRIPTOR_OUTPUT_MORE          0
  59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  62 #define DESCRIPTOR_STATUS               (1 << 11)
  63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  64 #define DESCRIPTOR_PING                 (1 << 7)
  65 #define DESCRIPTOR_YY                   (1 << 6)
  66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  70 #define DESCRIPTOR_WAIT                 (3 << 0)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[0];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         int excess_bytes;
 174         void *header;
 175         size_t header_length;
 176
 177         u8 sync;
 178         u8 tags;
 179 };
 180
 181 #define CONFIG_ROM_SIZE 1024
 182
 183 struct fw_ohci {
 184         struct fw_card card;
 185
 186         __iomem char *registers;
 187         int node_id;
 188         int generation;
 189         int request_generation; /* for timestamping incoming requests */
 190         unsigned quirks;
 191         unsigned int pri_req_max;
 192         u32 bus_time;
 193         bool is_root;
 194         bool csr_state_setclear_abdicate;
 195         int n_ir;
 196         int n_it;
 197         /*
 198          * Spinlock for accessing fw_ohci data.  Never call out of
 199          * this driver with this lock held.
 200          */
 201         spinlock_t lock;
 202
 203         struct mutex phy_reg_mutex;
 204
 205         void *misc_buffer;
 206         dma_addr_t misc_buffer_bus;
 207
 208         struct ar_context ar_request_ctx;
 209         struct ar_context ar_response_ctx;
 210         struct context at_request_ctx;
 211         struct context at_response_ctx;
 212
 213         u32 it_context_support;
 214         u32 it_context_mask;     /* unoccupied IT contexts */
 215         struct iso_context *it_context_list;
 216         u64 ir_context_channels; /* unoccupied channels */
 217         u32 ir_context_support;
 218         u32 ir_context_mask;     /* unoccupied IR contexts */
 219         struct iso_context *ir_context_list;
 220         u64 mc_channels; /* channels in use by the multichannel IR context */
 221         bool mc_allocated;
 222
 223         __be32    *config_rom;
 224         dma_addr_t config_rom_bus;
 225         __be32    *next_config_rom;
 226         dma_addr_t next_config_rom_bus;
 227         __be32     next_header;
 228
 229         __le32    *self_id_cpu;
 230         dma_addr_t self_id_bus;
 231         struct work_struct bus_reset_work;
 232
 233         u32 self_id_buffer[512];
 234 };
 235
 236 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 237 {
 238         return container_of(card, struct fw_ohci, card);
 239 }
 240
 241 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 242 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 243 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 244 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 245 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 246 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 247
 248 #define CONTEXT_RUN     0x8000
 249 #define CONTEXT_WAKE    0x1000
 250 #define CONTEXT_DEAD    0x0800
 251 #define CONTEXT_ACTIVE  0x0400
 252
 253 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 254 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 255 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 256
 257 #define OHCI1394_REGISTER_SIZE          0x800
 258 #define OHCI1394_PCI_HCI_Control        0x40
 259 #define SELF_ID_BUF_SIZE                0x800
 260 #define OHCI_TCODE_PHY_PACKET           0x0e
 261 #define OHCI_VERSION_1_1                0x010010
 262
 263 static char ohci_driver_name[] = KBUILD_MODNAME;
 264
 265 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 266 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 267 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 268 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 269 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 270 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 271 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 272
 273 #define QUIRK_CYCLE_TIMER               1
 274 #define QUIRK_RESET_PACKET              2
 275 #define QUIRK_BE_HEADERS                4
 276 #define QUIRK_NO_1394A                  8
 277 #define QUIRK_NO_MSI                    16
 278 #define QUIRK_TI_SLLZ059                32
 279
 280 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 281 static const struct {
 282         unsigned short vendor, device, revision, flags;
 283 } ohci_quirks[] = {
 284         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 285                 QUIRK_CYCLE_TIMER},
 286
 287         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 288                 QUIRK_BE_HEADERS},
 289
 290         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 291                 QUIRK_NO_MSI},
 292
 293         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 294                 QUIRK_RESET_PACKET},
 295
 296         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 297                 QUIRK_NO_MSI},
 298
 299         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 300                 QUIRK_CYCLE_TIMER},
 301
 302         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 303                 QUIRK_NO_MSI},
 304
 305         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 306                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 307
 308         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 309                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 310
 311         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 312                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 313
 314         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 315                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 316
 317         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 318                 QUIRK_RESET_PACKET},
 319
 320         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 321                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 322 };
 323
 324 /* This overrides anything that was found in ohci_quirks[]. */
 325 static int param_quirks;
 326 module_param_named(quirks, param_quirks, int, 0644);
 327 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 328         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 329         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 330         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 331         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 332         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 333         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 334         ")");
 335
 336 #define OHCI_PARAM_DEBUG_AT_AR          1
 337 #define OHCI_PARAM_DEBUG_SELFIDS        2
 338 #define OHCI_PARAM_DEBUG_IRQS           4
 339 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 340
 341 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 342
 343 static int param_debug;
 344 module_param_named(debug, param_debug, int, 0644);
 345 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 346         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 347         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 348         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 349         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 350         ", or a combination, or all = -1)");
 351
 352 static void log_irqs(u32 evt)
 353 {
 354         if (likely(!(param_debug &
 355                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 356                 return;
 357
 358         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 359             !(evt & OHCI1394_busReset))
 360                 return;
 361
 362         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 363             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 364             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 365             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 366             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 367             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 368             evt & OHCI1394_isochRx              ? " IR"                 : "",
 369             evt & OHCI1394_isochTx              ? " IT"                 : "",
 370             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 371             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 372             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 373             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 374             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 375             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 376             evt & OHCI1394_busReset             ? " busReset"           : "",
 377             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 378                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 379                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 380                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 381                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 382                     OHCI1394_cycleInconsistent |
 383                     OHCI1394_regAccessFail | OHCI1394_busReset)
 384                                                 ? " ?"                  : "");
 385 }
 386
 387 static const char *speed[] = {
 388         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 389 };
 390 static const char *power[] = {
 391         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 392         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 393 };
 394 static const char port[] = { '.', '-', 'p', 'c', };
 395
 396 static char _p(u32 *s, int shift)
 397 {
 398         return port[*s >> shift & 3];
 399 }
 400
 401 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 402 {
 403         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 404                 return;
 405
 406         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 407                   self_id_count, generation, node_id);
 408
 409         for (; self_id_count--; ++s)
 410                 if ((*s & 1 << 23) == 0)
 411                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 412                             "%s gc=%d %s %s%s%s\n",
 413                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 414                             speed[*s >> 14 & 3], *s >> 16 & 63,
 415                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 416                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 417                 else
 418                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 419                             *s, *s >> 24 & 63,
 420                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 421                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 422 }
 423
 424 static const char *evts[] = {
 425         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 426         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 427         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 428         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 429         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 430         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 431         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 432         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 433         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 434         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 435         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 436         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 437         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 438         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 439         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 440         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 441         [0x20] = "pending/cancelled",
 442 };
 443 static const char *tcodes[] = {
 444         [0x0] = "QW req",               [0x1] = "BW req",
 445         [0x2] = "W resp",               [0x3] = "-reserved-",
 446         [0x4] = "QR req",               [0x5] = "BR req",
 447         [0x6] = "QR resp",              [0x7] = "BR resp",
 448         [0x8] = "cycle start",          [0x9] = "Lk req",
 449         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 450         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 451         [0xe] = "link internal",        [0xf] = "-reserved-",
 452 };
 453
 454 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 455 {
 456         int tcode = header[0] >> 4 & 0xf;
 457         char specific[12];
 458
 459         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 460                 return;
 461
 462         if (unlikely(evt >= ARRAY_SIZE(evts)))
 463                         evt = 0x1f;
 464
 465         if (evt == OHCI1394_evt_bus_reset) {
 466                 fw_notify("A%c evt_bus_reset, generation %d\n",
 467                     dir, (header[2] >> 16) & 0xff);
 468                 return;
 469         }
 470
 471         switch (tcode) {
 472         case 0x0: case 0x6: case 0x8:
 473                 snprintf(specific, sizeof(specific), " = %08x",
 474                          be32_to_cpu((__force __be32)header[3]));
 475                 break;
 476         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 477                 snprintf(specific, sizeof(specific), " %x,%x",
 478                          header[3] >> 16, header[3] & 0xffff);
 479                 break;
 480         default:
 481                 specific[0] = '\0';
 482         }
 483
 484         switch (tcode) {
 485         case 0xa:
 486                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 487                 break;
 488         case 0xe:
 489                 fw_notify("A%c %s, PHY %08x %08x\n",
 490                           dir, evts[evt], header[1], header[2]);
 491                 break;
 492         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 493                 fw_notify("A%c spd %x tl %02x, "
 494                     "%04x -> %04x, %s, "
 495                     "%s, %04x%08x%s\n",
 496                     dir, speed, header[0] >> 10 & 0x3f,
 497                     header[1] >> 16, header[0] >> 16, evts[evt],
 498                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 499                 break;
 500         default:
 501                 fw_notify("A%c spd %x tl %02x, "
 502                     "%04x -> %04x, %s, "
 503                     "%s%s\n",
 504                     dir, speed, header[0] >> 10 & 0x3f,
 505                     header[1] >> 16, header[0] >> 16, evts[evt],
 506                     tcodes[tcode], specific);
 507         }
 508 }
 509
 510 #else
 511
 512 #define param_debug 0
 513 static inline void log_irqs(u32 evt) {}
 514 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 515 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 516
 517 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 518
 519 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 520 {
 521         writel(data, ohci->registers + offset);
 522 }
 523
 524 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 525 {
 526         return readl(ohci->registers + offset);
 527 }
 528
 529 static inline void flush_writes(const struct fw_ohci *ohci)
 530 {
 531         /* Do a dummy read to flush writes. */
 532         reg_read(ohci, OHCI1394_Version);
 533 }
 534
 535 /*
 536  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 537  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 538  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 539  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 540  */
 541 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 542 {
 543         u32 val;
 544         int i;
 545
 546         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 547         for (i = 0; i < 3 + 100; i++) {
 548                 val = reg_read(ohci, OHCI1394_PhyControl);
 549                 if (!~val)
 550                         return -ENODEV; /* Card was ejected. */
 551
 552                 if (val & OHCI1394_PhyControl_ReadDone)
 553                         return OHCI1394_PhyControl_ReadData(val);
 554
 555                 /*
 556                  * Try a few times without waiting.  Sleeping is necessary
 557                  * only when the link/PHY interface is busy.
 558                  */
 559                 if (i >= 3)
 560                         msleep(1);
 561         }
 562         fw_error("failed to read phy reg\n");
 563
 564         return -EBUSY;
 565 }
 566
 567 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 568 {
 569         int i;
 570
 571         reg_write(ohci, OHCI1394_PhyControl,
 572                   OHCI1394_PhyControl_Write(addr, val));
 573         for (i = 0; i < 3 + 100; i++) {
 574                 val = reg_read(ohci, OHCI1394_PhyControl);
 575                 if (!~val)
 576                         return -ENODEV; /* Card was ejected. */
 577
 578                 if (!(val & OHCI1394_PhyControl_WritePending))
 579                         return 0;
 580
 581                 if (i >= 3)
 582                         msleep(1);
 583         }
 584         fw_error("failed to write phy reg\n");
 585
 586         return -EBUSY;
 587 }
 588
 589 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 590                           int clear_bits, int set_bits)
 591 {
 592         int ret = read_phy_reg(ohci, addr);
 593         if (ret < 0)
 594                 return ret;
 595
 596         /*
 597          * The interrupt status bits are cleared by writing a one bit.
 598          * Avoid clearing them unless explicitly requested in set_bits.
 599          */
 600         if (addr == 5)
 601                 clear_bits |= PHY_INT_STATUS_BITS;
 602
 603         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 604 }
 605
 606 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 607 {
 608         int ret;
 609
 610         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 611         if (ret < 0)
 612                 return ret;
 613
 614         return read_phy_reg(ohci, addr);
 615 }
 616
 617 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 618 {
 619         struct fw_ohci *ohci = fw_ohci(card);
 620         int ret;
 621
 622         mutex_lock(&ohci->phy_reg_mutex);
 623         ret = read_phy_reg(ohci, addr);
 624         mutex_unlock(&ohci->phy_reg_mutex);
 625
 626         return ret;
 627 }
 628
 629 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 630                                int clear_bits, int set_bits)
 631 {
 632         struct fw_ohci *ohci = fw_ohci(card);
 633         int ret;
 634
 635         mutex_lock(&ohci->phy_reg_mutex);
 636         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 637         mutex_unlock(&ohci->phy_reg_mutex);
 638
 639         return ret;
 640 }
 641
 642 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 643 {
 644         return page_private(ctx->pages[i]);
 645 }
 646
 647 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 648 {
 649         struct descriptor *d;
 650
 651         d = &ctx->descriptors[index];
 652         d->branch_address  &= cpu_to_le32(~0xf);
 653         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 654         d->transfer_status =  0;
 655
 656         wmb(); /* finish init of new descriptors before branch_address update */
 657         d = &ctx->descriptors[ctx->last_buffer_index];
 658         d->branch_address  |= cpu_to_le32(1);
 659
 660         ctx->last_buffer_index = index;
 661
 662         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 663 }
 664
 665 static void ar_context_release(struct ar_context *ctx)
 666 {
 667         unsigned int i;
 668
 669         if (ctx->buffer)
 670                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 671
 672         for (i = 0; i < AR_BUFFERS; i++)
 673                 if (ctx->pages[i]) {
 674                         dma_unmap_page(ctx->ohci->card.device,
 675                                        ar_buffer_bus(ctx, i),
 676                                        PAGE_SIZE, DMA_FROM_DEVICE);
 677                         __free_page(ctx->pages[i]);
 678                 }
 679 }
 680
 681 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 682 {
 683         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 684                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 685                 flush_writes(ctx->ohci);
 686
 687                 fw_error("AR error: %s; DMA stopped\n", error_msg);
 688         }
 689         /* FIXME: restart? */
 690 }
 691
 692 static inline unsigned int ar_next_buffer_index(unsigned int index)
 693 {
 694         return (index + 1) % AR_BUFFERS;
 695 }
 696
 697 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 698 {
 699         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 700 }
 701
 702 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 703 {
 704         return ar_next_buffer_index(ctx->last_buffer_index);
 705 }
 706
 707 /*
 708  * We search for the buffer that contains the last AR packet DMA data written
 709  * by the controller.
 710  */
 711 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 712                                                  unsigned int *buffer_offset)
 713 {
 714         unsigned int i, next_i, last = ctx->last_buffer_index;
 715         __le16 res_count, next_res_count;
 716
 717         i = ar_first_buffer_index(ctx);
 718         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 719
 720         /* A buffer that is not yet completely filled must be the last one. */
 721         while (i != last && res_count == 0) {
 722
 723                 /* Peek at the next descriptor. */
 724                 next_i = ar_next_buffer_index(i);
 725                 rmb(); /* read descriptors in order */
 726                 next_res_count = ACCESS_ONCE(
 727                                 ctx->descriptors[next_i].res_count);
 728                 /*
 729                  * If the next descriptor is still empty, we must stop at this
 730                  * descriptor.
 731                  */
 732                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 733                         /*
 734                          * The exception is when the DMA data for one packet is
 735                          * split over three buffers; in this case, the middle
 736                          * buffer's descriptor might be never updated by the
 737                          * controller and look still empty, and we have to peek
 738                          * at the third one.
 739                          */
 740                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 741                                 next_i = ar_next_buffer_index(next_i);
 742                                 rmb();
 743                                 next_res_count = ACCESS_ONCE(
 744                                         ctx->descriptors[next_i].res_count);
 745                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 746                                         goto next_buffer_is_active;
 747                         }
 748
 749                         break;
 750                 }
 751
 752 next_buffer_is_active:
 753                 i = next_i;
 754                 res_count = next_res_count;
 755         }
 756
 757         rmb(); /* read res_count before the DMA data */
 758
 759         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 760         if (*buffer_offset > PAGE_SIZE) {
 761                 *buffer_offset = 0;
 762                 ar_context_abort(ctx, "corrupted descriptor");
 763         }
 764
 765         return i;
 766 }
 767
 768 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 769                                     unsigned int end_buffer_index,
 770                                     unsigned int end_buffer_offset)
 771 {
 772         unsigned int i;
 773
 774         i = ar_first_buffer_index(ctx);
 775         while (i != end_buffer_index) {
 776                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 777                                         ar_buffer_bus(ctx, i),
 778                                         PAGE_SIZE, DMA_FROM_DEVICE);
 779                 i = ar_next_buffer_index(i);
 780         }
 781         if (end_buffer_offset > 0)
 782                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 783                                         ar_buffer_bus(ctx, i),
 784                                         end_buffer_offset, DMA_FROM_DEVICE);
 785 }
 786
 787 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 788 #define cond_le32_to_cpu(v) \
 789         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 790 #else
 791 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 792 #endif
 793
 794 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 795 {
 796         struct fw_ohci *ohci = ctx->ohci;
 797         struct fw_packet p;
 798         u32 status, length, tcode;
 799         int evt;
 800
 801         p.header[0] = cond_le32_to_cpu(buffer[0]);
 802         p.header[1] = cond_le32_to_cpu(buffer[1]);
 803         p.header[2] = cond_le32_to_cpu(buffer[2]);
 804
 805         tcode = (p.header[0] >> 4) & 0x0f;
 806         switch (tcode) {
 807         case TCODE_WRITE_QUADLET_REQUEST:
 808         case TCODE_READ_QUADLET_RESPONSE:
 809                 p.header[3] = (__force __u32) buffer[3];
 810                 p.header_length = 16;
 811                 p.payload_length = 0;
 812                 break;
 813
 814         case TCODE_READ_BLOCK_REQUEST :
 815                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 816                 p.header_length = 16;
 817                 p.payload_length = 0;
 818                 break;
 819
 820         case TCODE_WRITE_BLOCK_REQUEST:
 821         case TCODE_READ_BLOCK_RESPONSE:
 822         case TCODE_LOCK_REQUEST:
 823         case TCODE_LOCK_RESPONSE:
 824                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 825                 p.header_length = 16;
 826                 p.payload_length = p.header[3] >> 16;
 827                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 828                         ar_context_abort(ctx, "invalid packet length");
 829                         return NULL;
 830                 }
 831                 break;
 832
 833         case TCODE_WRITE_RESPONSE:
 834         case TCODE_READ_QUADLET_REQUEST:
 835         case OHCI_TCODE_PHY_PACKET:
 836                 p.header_length = 12;
 837                 p.payload_length = 0;
 838                 break;
 839
 840         default:
 841                 ar_context_abort(ctx, "invalid tcode");
 842                 return NULL;
 843         }
 844
 845         p.payload = (void *) buffer + p.header_length;
 846
 847         /* FIXME: What to do about evt_* errors? */
 848         length = (p.header_length + p.payload_length + 3) / 4;
 849         status = cond_le32_to_cpu(buffer[length]);
 850         evt    = (status >> 16) & 0x1f;
 851
 852         p.ack        = evt - 16;
 853         p.speed      = (status >> 21) & 0x7;
 854         p.timestamp  = status & 0xffff;
 855         p.generation = ohci->request_generation;
 856
 857         log_ar_at_event('R', p.speed, p.header, evt);
 858
 859         /*
 860          * Several controllers, notably from NEC and VIA, forget to
 861          * write ack_complete status at PHY packet reception.
 862          */
 863         if (evt == OHCI1394_evt_no_status &&
 864             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 865                 p.ack = ACK_COMPLETE;
 866
 867         /*
 868          * The OHCI bus reset handler synthesizes a PHY packet with
 869          * the new generation number when a bus reset happens (see
 870          * section 8.4.2.3).  This helps us determine when a request
 871          * was received and make sure we send the response in the same
 872          * generation.  We only need this for requests; for responses
 873          * we use the unique tlabel for finding the matching
 874          * request.
 875          *
 876          * Alas some chips sometimes emit bus reset packets with a
 877          * wrong generation.  We set the correct generation for these
 878          * at a slightly incorrect time (in bus_reset_work).
 879          */
 880         if (evt == OHCI1394_evt_bus_reset) {
 881                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 882                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 883         } else if (ctx == &ohci->ar_request_ctx) {
 884                 fw_core_handle_request(&ohci->card, &p);
 885         } else {
 886                 fw_core_handle_response(&ohci->card, &p);
 887         }
 888
 889         return buffer + length + 1;
 890 }
 891
 892 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 893 {
 894         void *next;
 895
 896         while (p < end) {
 897                 next = handle_ar_packet(ctx, p);
 898                 if (!next)
 899                         return p;
 900                 p = next;
 901         }
 902
 903         return p;
 904 }
 905
 906 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 907 {
 908         unsigned int i;
 909
 910         i = ar_first_buffer_index(ctx);
 911         while (i != end_buffer) {
 912                 dma_sync_single_for_device(ctx->ohci->card.device,
 913                                            ar_buffer_bus(ctx, i),
 914                                            PAGE_SIZE, DMA_FROM_DEVICE);
 915                 ar_context_link_page(ctx, i);
 916                 i = ar_next_buffer_index(i);
 917         }
 918 }
 919
 920 static void ar_context_tasklet(unsigned long data)
 921 {
 922         struct ar_context *ctx = (struct ar_context *)data;
 923         unsigned int end_buffer_index, end_buffer_offset;
 924         void *p, *end;
 925
 926         p = ctx->pointer;
 927         if (!p)
 928                 return;
 929
 930         end_buffer_index = ar_search_last_active_buffer(ctx,
 931                                                         &end_buffer_offset);
 932         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 933         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 934
 935         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 936                 /*
 937                  * The filled part of the overall buffer wraps around; handle
 938                  * all packets up to the buffer end here.  If the last packet
 939                  * wraps around, its tail will be visible after the buffer end
 940                  * because the buffer start pages are mapped there again.
 941                  */
 942                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 943                 p = handle_ar_packets(ctx, p, buffer_end);
 944                 if (p < buffer_end)
 945                         goto error;
 946                 /* adjust p to point back into the actual buffer */
 947                 p -= AR_BUFFERS * PAGE_SIZE;
 948         }
 949
 950         p = handle_ar_packets(ctx, p, end);
 951         if (p != end) {
 952                 if (p > end)
 953                         ar_context_abort(ctx, "inconsistent descriptor");
 954                 goto error;
 955         }
 956
 957         ctx->pointer = p;
 958         ar_recycle_buffers(ctx, end_buffer_index);
 959
 960         return;
 961
 962 error:
 963         ctx->pointer = NULL;
 964 }
 965
 966 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 967                            unsigned int descriptors_offset, u32 regs)
 968 {
 969         unsigned int i;
 970         dma_addr_t dma_addr;
 971         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 972         struct descriptor *d;
 973
 974         ctx->regs        = regs;
 975         ctx->ohci        = ohci;
 976         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 977
 978         for (i = 0; i < AR_BUFFERS; i++) {
 979                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 980                 if (!ctx->pages[i])
 981                         goto out_of_memory;
 982                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 983                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 984                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 985                         __free_page(ctx->pages[i]);
 986                         ctx->pages[i] = NULL;
 987                         goto out_of_memory;
 988                 }
 989                 set_page_private(ctx->pages[i], dma_addr);
 990         }
 991
 992         for (i = 0; i < AR_BUFFERS; i++)
 993                 pages[i]              = ctx->pages[i];
 994         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 995                 pages[AR_BUFFERS + i] = ctx->pages[i];
 996         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 997                                  -1, PAGE_KERNEL);
 998         if (!ctx->buffer)
 999                 goto out_of_memory;
1000
1001         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1002         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1003
1004         for (i = 0; i < AR_BUFFERS; i++) {
1005                 d = &ctx->descriptors[i];
1006                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1007                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1008                                                 DESCRIPTOR_STATUS |
1009                                                 DESCRIPTOR_BRANCH_ALWAYS);
1010                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1011                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1012                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1013         }
1014
1015         return 0;
1016
1017 out_of_memory:
1018         ar_context_release(ctx);
1019
1020         return -ENOMEM;
1021 }
1022
1023 static void ar_context_run(struct ar_context *ctx)
1024 {
1025         unsigned int i;
1026
1027         for (i = 0; i < AR_BUFFERS; i++)
1028                 ar_context_link_page(ctx, i);
1029
1030         ctx->pointer = ctx->buffer;
1031
1032         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1033         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1034 }
1035
1036 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1037 {
1038         __le16 branch;
1039
1040         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1041
1042         /* figure out which descriptor the branch address goes in */
1043         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1044                 return d;
1045         else
1046                 return d + z - 1;
1047 }
1048
1049 static void context_tasklet(unsigned long data)
1050 {
1051         struct context *ctx = (struct context *) data;
1052         struct descriptor *d, *last;
1053         u32 address;
1054         int z;
1055         struct descriptor_buffer *desc;
1056
1057         desc = list_entry(ctx->buffer_list.next,
1058                         struct descriptor_buffer, list);
1059         last = ctx->last;
1060         while (last->branch_address != 0) {
1061                 struct descriptor_buffer *old_desc = desc;
1062                 address = le32_to_cpu(last->branch_address);
1063                 z = address & 0xf;
1064                 address &= ~0xf;
1065                 ctx->current_bus = address;
1066
1067                 /* If the branch address points to a buffer outside of the
1068                  * current buffer, advance to the next buffer. */
1069                 if (address < desc->buffer_bus ||
1070                                 address >= desc->buffer_bus + desc->used)
1071                         desc = list_entry(desc->list.next,
1072                                         struct descriptor_buffer, list);
1073                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1074                 last = find_branch_descriptor(d, z);
1075
1076                 if (!ctx->callback(ctx, d, last))
1077                         break;
1078
1079                 if (old_desc != desc) {
1080                         /* If we've advanced to the next buffer, move the
1081                          * previous buffer to the free list. */
1082                         unsigned long flags;
1083                         old_desc->used = 0;
1084                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1085                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1086                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1087                 }
1088                 ctx->last = last;
1089         }
1090 }
1091
1092 /*
1093  * Allocate a new buffer and add it to the list of free buffers for this
1094  * context.  Must be called with ohci->lock held.
1095  */
1096 static int context_add_buffer(struct context *ctx)
1097 {
1098         struct descriptor_buffer *desc;
1099         dma_addr_t uninitialized_var(bus_addr);
1100         int offset;
1101
1102         /*
1103          * 16MB of descriptors should be far more than enough for any DMA
1104          * program.  This will catch run-away userspace or DoS attacks.
1105          */
1106         if (ctx->total_allocation >= 16*1024*1024)
1107                 return -ENOMEM;
1108
1109         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1110                         &bus_addr, GFP_ATOMIC);
1111         if (!desc)
1112                 return -ENOMEM;
1113
1114         offset = (void *)&desc->buffer - (void *)desc;
1115         desc->buffer_size = PAGE_SIZE - offset;
1116         desc->buffer_bus = bus_addr + offset;
1117         desc->used = 0;
1118
1119         list_add_tail(&desc->list, &ctx->buffer_list);
1120         ctx->total_allocation += PAGE_SIZE;
1121
1122         return 0;
1123 }
1124
1125 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1126                         u32 regs, descriptor_callback_t callback)
1127 {
1128         ctx->ohci = ohci;
1129         ctx->regs = regs;
1130         ctx->total_allocation = 0;
1131
1132         INIT_LIST_HEAD(&ctx->buffer_list);
1133         if (context_add_buffer(ctx) < 0)
1134                 return -ENOMEM;
1135
1136         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1137                         struct descriptor_buffer, list);
1138
1139         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1140         ctx->callback = callback;
1141
1142         /*
1143          * We put a dummy descriptor in the buffer that has a NULL
1144          * branch address and looks like it's been sent.  That way we
1145          * have a descriptor to append DMA programs to.
1146          */
1147         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1148         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1149         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1150         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1151         ctx->last = ctx->buffer_tail->buffer;
1152         ctx->prev = ctx->buffer_tail->buffer;
1153
1154         return 0;
1155 }
1156
1157 static void context_release(struct context *ctx)
1158 {
1159         struct fw_card *card = &ctx->ohci->card;
1160         struct descriptor_buffer *desc, *tmp;
1161
1162         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1163                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1164                         desc->buffer_bus -
1165                         ((void *)&desc->buffer - (void *)desc));
1166 }
1167
1168 /* Must be called with ohci->lock held */
1169 static struct descriptor *context_get_descriptors(struct context *ctx,
1170                                                   int z, dma_addr_t *d_bus)
1171 {
1172         struct descriptor *d = NULL;
1173         struct descriptor_buffer *desc = ctx->buffer_tail;
1174
1175         if (z * sizeof(*d) > desc->buffer_size)
1176                 return NULL;
1177
1178         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1179                 /* No room for the descriptor in this buffer, so advance to the
1180                  * next one. */
1181
1182                 if (desc->list.next == &ctx->buffer_list) {
1183                         /* If there is no free buffer next in the list,
1184                          * allocate one. */
1185                         if (context_add_buffer(ctx) < 0)
1186                                 return NULL;
1187                 }
1188                 desc = list_entry(desc->list.next,
1189                                 struct descriptor_buffer, list);
1190                 ctx->buffer_tail = desc;
1191         }
1192
1193         d = desc->buffer + desc->used / sizeof(*d);
1194         memset(d, 0, z * sizeof(*d));
1195         *d_bus = desc->buffer_bus + desc->used;
1196
1197         return d;
1198 }
1199
1200 static void context_run(struct context *ctx, u32 extra)
1201 {
1202         struct fw_ohci *ohci = ctx->ohci;
1203
1204         reg_write(ohci, COMMAND_PTR(ctx->regs),
1205                   le32_to_cpu(ctx->last->branch_address));
1206         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1207         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1208         ctx->running = true;
1209         flush_writes(ohci);
1210 }
1211
1212 static void context_append(struct context *ctx,
1213                            struct descriptor *d, int z, int extra)
1214 {
1215         dma_addr_t d_bus;
1216         struct descriptor_buffer *desc = ctx->buffer_tail;
1217
1218         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1219
1220         desc->used += (z + extra) * sizeof(*d);
1221
1222         wmb(); /* finish init of new descriptors before branch_address update */
1223         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1224         ctx->prev = find_branch_descriptor(d, z);
1225 }
1226
1227 static void context_stop(struct context *ctx)
1228 {
1229         u32 reg;
1230         int i;
1231
1232         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1233         ctx->running = false;
1234
1235         for (i = 0; i < 1000; i++) {
1236                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1237                 if ((reg & CONTEXT_ACTIVE) == 0)
1238                         return;
1239
1240                 if (i)
1241                         udelay(10);
1242         }
1243         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1244 }
1245
1246 struct driver_data {
1247         u8 inline_data[8];
1248         struct fw_packet *packet;
1249 };
1250
1251 /*
1252  * This function apppends a packet to the DMA queue for transmission.
1253  * Must always be called with the ochi->lock held to ensure proper
1254  * generation handling and locking around packet queue manipulation.
1255  */
1256 static int at_context_queue_packet(struct context *ctx,
1257                                    struct fw_packet *packet)
1258 {
1259         struct fw_ohci *ohci = ctx->ohci;
1260         dma_addr_t d_bus, uninitialized_var(payload_bus);
1261         struct driver_data *driver_data;
1262         struct descriptor *d, *last;
1263         __le32 *header;
1264         int z, tcode;
1265
1266         d = context_get_descriptors(ctx, 4, &d_bus);
1267         if (d == NULL) {
1268                 packet->ack = RCODE_SEND_ERROR;
1269                 return -1;
1270         }
1271
1272         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1273         d[0].res_count = cpu_to_le16(packet->timestamp);
1274
1275         /*
1276          * The DMA format for asyncronous link packets is different
1277          * from the IEEE1394 layout, so shift the fields around
1278          * accordingly.
1279          */
1280
1281         tcode = (packet->header[0] >> 4) & 0x0f;
1282         header = (__le32 *) &d[1];
1283         switch (tcode) {
1284         case TCODE_WRITE_QUADLET_REQUEST:
1285         case TCODE_WRITE_BLOCK_REQUEST:
1286         case TCODE_WRITE_RESPONSE:
1287         case TCODE_READ_QUADLET_REQUEST:
1288         case TCODE_READ_BLOCK_REQUEST:
1289         case TCODE_READ_QUADLET_RESPONSE:
1290         case TCODE_READ_BLOCK_RESPONSE:
1291         case TCODE_LOCK_REQUEST:
1292         case TCODE_LOCK_RESPONSE:
1293                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1294                                         (packet->speed << 16));
1295                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1296                                         (packet->header[0] & 0xffff0000));
1297                 header[2] = cpu_to_le32(packet->header[2]);
1298
1299                 if (TCODE_IS_BLOCK_PACKET(tcode))
1300                         header[3] = cpu_to_le32(packet->header[3]);
1301                 else
1302                         header[3] = (__force __le32) packet->header[3];
1303
1304                 d[0].req_count = cpu_to_le16(packet->header_length);
1305                 break;
1306
1307         case TCODE_LINK_INTERNAL:
1308                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1309                                         (packet->speed << 16));
1310                 header[1] = cpu_to_le32(packet->header[1]);
1311                 header[2] = cpu_to_le32(packet->header[2]);
1312                 d[0].req_count = cpu_to_le16(12);
1313
1314                 if (is_ping_packet(&packet->header[1]))
1315                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1316                 break;
1317
1318         case TCODE_STREAM_DATA:
1319                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1320                                         (packet->speed << 16));
1321                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1322                 d[0].req_count = cpu_to_le16(8);
1323                 break;
1324
1325         default:
1326                 /* BUG(); */
1327                 packet->ack = RCODE_SEND_ERROR;
1328                 return -1;
1329         }
1330
1331         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1332         driver_data = (struct driver_data *) &d[3];
1333         driver_data->packet = packet;
1334         packet->driver_data = driver_data;
1335
1336         if (packet->payload_length > 0) {
1337                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1338                         payload_bus = dma_map_single(ohci->card.device,
1339                                                      packet->payload,
1340                                                      packet->payload_length,
1341                                                      DMA_TO_DEVICE);
1342                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1343                                 packet->ack = RCODE_SEND_ERROR;
1344                                 return -1;
1345                         }
1346                         packet->payload_bus     = payload_bus;
1347                         packet->payload_mapped  = true;
1348                 } else {
1349                         memcpy(driver_data->inline_data, packet->payload,
1350                                packet->payload_length);
1351                         payload_bus = d_bus + 3 * sizeof(*d);
1352                 }
1353
1354                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1355                 d[2].data_address = cpu_to_le32(payload_bus);
1356                 last = &d[2];
1357                 z = 3;
1358         } else {
1359                 last = &d[0];
1360                 z = 2;
1361         }
1362
1363         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1364                                      DESCRIPTOR_IRQ_ALWAYS |
1365                                      DESCRIPTOR_BRANCH_ALWAYS);
1366
1367         /* FIXME: Document how the locking works. */
1368         if (ohci->generation != packet->generation) {
1369                 if (packet->payload_mapped)
1370                         dma_unmap_single(ohci->card.device, payload_bus,
1371                                          packet->payload_length, DMA_TO_DEVICE);
1372                 packet->ack = RCODE_GENERATION;
1373                 return -1;
1374         }
1375
1376         context_append(ctx, d, z, 4 - z);
1377
1378         if (ctx->running)
1379                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1380         else
1381                 context_run(ctx, 0);
1382
1383         return 0;
1384 }
1385
1386 static void at_context_flush(struct context *ctx)
1387 {
1388         tasklet_disable(&ctx->tasklet);
1389
1390         ctx->flushing = true;
1391         context_tasklet((unsigned long)ctx);
1392         ctx->flushing = false;
1393
1394         tasklet_enable(&ctx->tasklet);
1395 }
1396
1397 static int handle_at_packet(struct context *context,
1398                             struct descriptor *d,
1399                             struct descriptor *last)
1400 {
1401         struct driver_data *driver_data;
1402         struct fw_packet *packet;
1403         struct fw_ohci *ohci = context->ohci;
1404         int evt;
1405
1406         if (last->transfer_status == 0 && !context->flushing)
1407                 /* This descriptor isn't done yet, stop iteration. */
1408                 return 0;
1409
1410         driver_data = (struct driver_data *) &d[3];
1411         packet = driver_data->packet;
1412         if (packet == NULL)
1413                 /* This packet was cancelled, just continue. */
1414                 return 1;
1415
1416         if (packet->payload_mapped)
1417                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1418                                  packet->payload_length, DMA_TO_DEVICE);
1419
1420         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1421         packet->timestamp = le16_to_cpu(last->res_count);
1422
1423         log_ar_at_event('T', packet->speed, packet->header, evt);
1424
1425         switch (evt) {
1426         case OHCI1394_evt_timeout:
1427                 /* Async response transmit timed out. */
1428                 packet->ack = RCODE_CANCELLED;
1429                 break;
1430
1431         case OHCI1394_evt_flushed:
1432                 /*
1433                  * The packet was flushed should give same error as
1434                  * when we try to use a stale generation count.
1435                  */
1436                 packet->ack = RCODE_GENERATION;
1437                 break;
1438
1439         case OHCI1394_evt_missing_ack:
1440                 if (context->flushing)
1441                         packet->ack = RCODE_GENERATION;
1442                 else {
1443                         /*
1444                          * Using a valid (current) generation count, but the
1445                          * node is not on the bus or not sending acks.
1446                          */
1447                         packet->ack = RCODE_NO_ACK;
1448                 }
1449                 break;
1450
1451         case ACK_COMPLETE + 0x10:
1452         case ACK_PENDING + 0x10:
1453         case ACK_BUSY_X + 0x10:
1454         case ACK_BUSY_A + 0x10:
1455         case ACK_BUSY_B + 0x10:
1456         case ACK_DATA_ERROR + 0x10:
1457         case ACK_TYPE_ERROR + 0x10:
1458                 packet->ack = evt - 0x10;
1459                 break;
1460
1461         case OHCI1394_evt_no_status:
1462                 if (context->flushing) {
1463                         packet->ack = RCODE_GENERATION;
1464                         break;
1465                 }
1466                 /* fall through */
1467
1468         default:
1469                 packet->ack = RCODE_SEND_ERROR;
1470                 break;
1471         }
1472
1473         packet->callback(packet, &ohci->card, packet->ack);
1474
1475         return 1;
1476 }
1477
1478 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1479 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1480 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1481 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1482 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1483
1484 static void handle_local_rom(struct fw_ohci *ohci,
1485                              struct fw_packet *packet, u32 csr)
1486 {
1487         struct fw_packet response;
1488         int tcode, length, i;
1489
1490         tcode = HEADER_GET_TCODE(packet->header[0]);
1491         if (TCODE_IS_BLOCK_PACKET(tcode))
1492                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1493         else
1494                 length = 4;
1495
1496         i = csr - CSR_CONFIG_ROM;
1497         if (i + length > CONFIG_ROM_SIZE) {
1498                 fw_fill_response(&response, packet->header,
1499                                  RCODE_ADDRESS_ERROR, NULL, 0);
1500         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1501                 fw_fill_response(&response, packet->header,
1502                                  RCODE_TYPE_ERROR, NULL, 0);
1503         } else {
1504                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1505                                  (void *) ohci->config_rom + i, length);
1506         }
1507
1508         fw_core_handle_response(&ohci->card, &response);
1509 }
1510
1511 static void handle_local_lock(struct fw_ohci *ohci,
1512                               struct fw_packet *packet, u32 csr)
1513 {
1514         struct fw_packet response;
1515         int tcode, length, ext_tcode, sel, try;
1516         __be32 *payload, lock_old;
1517         u32 lock_arg, lock_data;
1518
1519         tcode = HEADER_GET_TCODE(packet->header[0]);
1520         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1521         payload = packet->payload;
1522         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1523
1524         if (tcode == TCODE_LOCK_REQUEST &&
1525             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1526                 lock_arg = be32_to_cpu(payload[0]);
1527                 lock_data = be32_to_cpu(payload[1]);
1528         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1529                 lock_arg = 0;
1530                 lock_data = 0;
1531         } else {
1532                 fw_fill_response(&response, packet->header,
1533                                  RCODE_TYPE_ERROR, NULL, 0);
1534                 goto out;
1535         }
1536
1537         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1538         reg_write(ohci, OHCI1394_CSRData, lock_data);
1539         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1540         reg_write(ohci, OHCI1394_CSRControl, sel);
1541
1542         for (try = 0; try < 20; try++)
1543                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1544                         lock_old = cpu_to_be32(reg_read(ohci,
1545                                                         OHCI1394_CSRData));
1546                         fw_fill_response(&response, packet->header,
1547                                          RCODE_COMPLETE,
1548                                          &lock_old, sizeof(lock_old));
1549                         goto out;
1550                 }
1551
1552         fw_error("swap not done (CSR lock timeout)\n");
1553         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1554
1555  out:
1556         fw_core_handle_response(&ohci->card, &response);
1557 }
1558
1559 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1560 {
1561         u64 offset, csr;
1562
1563         if (ctx == &ctx->ohci->at_request_ctx) {
1564                 packet->ack = ACK_PENDING;
1565                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1566         }
1567
1568         offset =
1569                 ((unsigned long long)
1570                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1571                 packet->header[2];
1572         csr = offset - CSR_REGISTER_BASE;
1573
1574         /* Handle config rom reads. */
1575         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1576                 handle_local_rom(ctx->ohci, packet, csr);
1577         else switch (csr) {
1578         case CSR_BUS_MANAGER_ID:
1579         case CSR_BANDWIDTH_AVAILABLE:
1580         case CSR_CHANNELS_AVAILABLE_HI:
1581         case CSR_CHANNELS_AVAILABLE_LO:
1582                 handle_local_lock(ctx->ohci, packet, csr);
1583                 break;
1584         default:
1585                 if (ctx == &ctx->ohci->at_request_ctx)
1586                         fw_core_handle_request(&ctx->ohci->card, packet);
1587                 else
1588                         fw_core_handle_response(&ctx->ohci->card, packet);
1589                 break;
1590         }
1591
1592         if (ctx == &ctx->ohci->at_response_ctx) {
1593                 packet->ack = ACK_COMPLETE;
1594                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1595         }
1596 }
1597
1598 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1599 {
1600         unsigned long flags;
1601         int ret;
1602
1603         spin_lock_irqsave(&ctx->ohci->lock, flags);
1604
1605         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1606             ctx->ohci->generation == packet->generation) {
1607                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1608                 handle_local_request(ctx, packet);
1609                 return;
1610         }
1611
1612         ret = at_context_queue_packet(ctx, packet);
1613         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1614
1615         if (ret < 0)
1616                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1617
1618 }
1619
1620 static void detect_dead_context(struct fw_ohci *ohci,
1621                                 const char *name, unsigned int regs)
1622 {
1623         u32 ctl;
1624
1625         ctl = reg_read(ohci, CONTROL_SET(regs));
1626         if (ctl & CONTEXT_DEAD) {
1627 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1628                 fw_error("DMA context %s has stopped, error code: %s\n",
1629                          name, evts[ctl & 0x1f]);
1630 #else
1631                 fw_error("DMA context %s has stopped, error code: %#x\n",
1632                          name, ctl & 0x1f);
1633 #endif
1634         }
1635 }
1636
1637 static void handle_dead_contexts(struct fw_ohci *ohci)
1638 {
1639         unsigned int i;
1640         char name[8];
1641
1642         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1643         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1644         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1645         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1646         for (i = 0; i < 32; ++i) {
1647                 if (!(ohci->it_context_support & (1 << i)))
1648                         continue;
1649                 sprintf(name, "IT%u", i);
1650                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1651         }
1652         for (i = 0; i < 32; ++i) {
1653                 if (!(ohci->ir_context_support & (1 << i)))
1654                         continue;
1655                 sprintf(name, "IR%u", i);
1656                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1657         }
1658         /* TODO: maybe try to flush and restart the dead contexts */
1659 }
1660
1661 static u32 cycle_timer_ticks(u32 cycle_timer)
1662 {
1663         u32 ticks;
1664
1665         ticks = cycle_timer & 0xfff;
1666         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1667         ticks += (3072 * 8000) * (cycle_timer >> 25);
1668
1669         return ticks;
1670 }
1671
1672 /*
1673  * Some controllers exhibit one or more of the following bugs when updating the
1674  * iso cycle timer register:
1675  *  - When the lowest six bits are wrapping around to zero, a read that happens
1676  *    at the same time will return garbage in the lowest ten bits.
1677  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1678  *    not incremented for about 60 ns.
1679  *  - Occasionally, the entire register reads zero.
1680  *
1681  * To catch these, we read the register three times and ensure that the
1682  * difference between each two consecutive reads is approximately the same, i.e.
1683  * less than twice the other.  Furthermore, any negative difference indicates an
1684  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1685  * execute, so we have enough precision to compute the ratio of the differences.)
1686  */
1687 static u32 get_cycle_time(struct fw_ohci *ohci)
1688 {
1689         u32 c0, c1, c2;
1690         u32 t0, t1, t2;
1691         s32 diff01, diff12;
1692         int i;
1693
1694         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1695
1696         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1697                 i = 0;
1698                 c1 = c2;
1699                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1700                 do {
1701                         c0 = c1;
1702                         c1 = c2;
1703                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1704                         t0 = cycle_timer_ticks(c0);
1705                         t1 = cycle_timer_ticks(c1);
1706                         t2 = cycle_timer_ticks(c2);
1707                         diff01 = t1 - t0;
1708                         diff12 = t2 - t1;
1709                 } while ((diff01 <= 0 || diff12 <= 0 ||
1710                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1711                          && i++ < 20);
1712         }
1713
1714         return c2;
1715 }
1716
1717 /*
1718  * This function has to be called at least every 64 seconds.  The bus_time
1719  * field stores not only the upper 25 bits of the BUS_TIME register but also
1720  * the most significant bit of the cycle timer in bit 6 so that we can detect
1721  * changes in this bit.
1722  */
1723 static u32 update_bus_time(struct fw_ohci *ohci)
1724 {
1725         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1726
1727         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1728                 ohci->bus_time += 0x40;
1729
1730         return ohci->bus_time | cycle_time_seconds;
1731 }
1732
1733 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1734 {
1735         int reg;
1736
1737         mutex_lock(&ohci->phy_reg_mutex);
1738         reg = write_phy_reg(ohci, 7, port_index);
1739         if (reg >= 0)
1740                 reg = read_phy_reg(ohci, 8);
1741         mutex_unlock(&ohci->phy_reg_mutex);
1742         if (reg < 0)
1743                 return reg;
1744
1745         switch (reg & 0x0f) {
1746         case 0x06:
1747                 return 2;       /* is child node (connected to parent node) */
1748         case 0x0e:
1749                 return 3;       /* is parent node (connected to child node) */
1750         }
1751         return 1;               /* not connected */
1752 }
1753
1754 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1755         int self_id_count)
1756 {
1757         int i;
1758         u32 entry;
1759
1760         for (i = 0; i < self_id_count; i++) {
1761                 entry = ohci->self_id_buffer[i];
1762                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1763                         return -1;
1764                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1765                         return i;
1766         }
1767         return i;
1768 }
1769
1770 /*
1771  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1772  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1773  * Construct the selfID from phy register contents.
1774  * FIXME:  How to determine the selfID.i flag?
1775  */
1776 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1777 {
1778         int reg, i, pos, status;
1779         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1780         u32 self_id = 0x8040c800;
1781
1782         reg = reg_read(ohci, OHCI1394_NodeID);
1783         if (!(reg & OHCI1394_NodeID_idValid)) {
1784                 fw_notify("node ID not valid, new bus reset in progress\n");
1785                 return -EBUSY;
1786         }
1787         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1788
1789         reg = ohci_read_phy_reg(&ohci->card, 4);
1790         if (reg < 0)
1791                 return reg;
1792         self_id |= ((reg & 0x07) << 8); /* power class */
1793
1794         reg = ohci_read_phy_reg(&ohci->card, 1);
1795         if (reg < 0)
1796                 return reg;
1797         self_id |= ((reg & 0x3f) << 16); /* gap count */
1798
1799         for (i = 0; i < 3; i++) {
1800                 status = get_status_for_port(ohci, i);
1801                 if (status < 0)
1802                         return status;
1803                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1804         }
1805
1806         pos = get_self_id_pos(ohci, self_id, self_id_count);
1807         if (pos >= 0) {
1808                 memmove(&(ohci->self_id_buffer[pos+1]),
1809                         &(ohci->self_id_buffer[pos]),
1810                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1811                 ohci->self_id_buffer[pos] = self_id;
1812                 self_id_count++;
1813         }
1814         return self_id_count;
1815 }
1816
1817 static void bus_reset_work(struct work_struct *work)
1818 {
1819         struct fw_ohci *ohci =
1820                 container_of(work, struct fw_ohci, bus_reset_work);
1821         int self_id_count, i, j, reg;
1822         int generation, new_generation;
1823         unsigned long flags;
1824         void *free_rom = NULL;
1825         dma_addr_t free_rom_bus = 0;
1826         bool is_new_root;
1827
1828         reg = reg_read(ohci, OHCI1394_NodeID);
1829         if (!(reg & OHCI1394_NodeID_idValid)) {
1830                 fw_notify("node ID not valid, new bus reset in progress\n");
1831                 return;
1832         }
1833         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1834                 fw_notify("malconfigured bus\n");
1835                 return;
1836         }
1837         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1838                                OHCI1394_NodeID_nodeNumber);
1839
1840         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1841         if (!(ohci->is_root && is_new_root))
1842                 reg_write(ohci, OHCI1394_LinkControlSet,
1843                           OHCI1394_LinkControl_cycleMaster);
1844         ohci->is_root = is_new_root;
1845
1846         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1847         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1848                 fw_notify("inconsistent self IDs\n");
1849                 return;
1850         }
1851         /*
1852          * The count in the SelfIDCount register is the number of
1853          * bytes in the self ID receive buffer.  Since we also receive
1854          * the inverted quadlets and a header quadlet, we shift one
1855          * bit extra to get the actual number of self IDs.
1856          */
1857         self_id_count = (reg >> 3) & 0xff;
1858
1859         if (self_id_count > 252) {
1860                 fw_notify("inconsistent self IDs\n");
1861                 return;
1862         }
1863
1864         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1865         rmb();
1866
1867         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1868                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1869                         /*
1870                          * If the invalid data looks like a cycle start packet,
1871                          * it's likely to be the result of the cycle master
1872                          * having a wrong gap count.  In this case, the self IDs
1873                          * so far are valid and should be processed so that the
1874                          * bus manager can then correct the gap count.
1875                          */
1876                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1877                                                         == 0xffff008f) {
1878                                 fw_notify("ignoring spurious self IDs\n");
1879                                 self_id_count = j;
1880                                 break;
1881                         } else {
1882                                 fw_notify("inconsistent self IDs\n");
1883                                 return;
1884                         }
1885                 }
1886                 ohci->self_id_buffer[j] =
1887                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1888         }
1889
1890         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1891                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1892                 if (self_id_count < 0) {
1893                         fw_notify("could not construct local self ID\n");
1894                         return;
1895                 }
1896         }
1897
1898         if (self_id_count == 0) {
1899                 fw_notify("inconsistent self IDs\n");
1900                 return;
1901         }
1902         rmb();
1903
1904         /*
1905          * Check the consistency of the self IDs we just read.  The
1906          * problem we face is that a new bus reset can start while we
1907          * read out the self IDs from the DMA buffer. If this happens,
1908          * the DMA buffer will be overwritten with new self IDs and we
1909          * will read out inconsistent data.  The OHCI specification
1910          * (section 11.2) recommends a technique similar to
1911          * linux/seqlock.h, where we remember the generation of the
1912          * self IDs in the buffer before reading them out and compare
1913          * it to the current generation after reading them out.  If
1914          * the two generations match we know we have a consistent set
1915          * of self IDs.
1916          */
1917
1918         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1919         if (new_generation != generation) {
1920                 fw_notify("recursive bus reset detected, "
1921                           "discarding self ids\n");
1922                 return;
1923         }
1924
1925         /* FIXME: Document how the locking works. */
1926         spin_lock_irqsave(&ohci->lock, flags);
1927
1928         ohci->generation = -1; /* prevent AT packet queueing */
1929         context_stop(&ohci->at_request_ctx);
1930         context_stop(&ohci->at_response_ctx);
1931
1932         spin_unlock_irqrestore(&ohci->lock, flags);
1933
1934         /*
1935          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1936          * packets in the AT queues and software needs to drain them.
1937          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1938          */
1939         at_context_flush(&ohci->at_request_ctx);
1940         at_context_flush(&ohci->at_response_ctx);
1941
1942         spin_lock_irqsave(&ohci->lock, flags);
1943
1944         ohci->generation = generation;
1945         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1946
1947         if (ohci->quirks & QUIRK_RESET_PACKET)
1948                 ohci->request_generation = generation;
1949
1950         /*
1951          * This next bit is unrelated to the AT context stuff but we
1952          * have to do it under the spinlock also.  If a new config rom
1953          * was set up before this reset, the old one is now no longer
1954          * in use and we can free it. Update the config rom pointers
1955          * to point to the current config rom and clear the
1956          * next_config_rom pointer so a new update can take place.
1957          */
1958
1959         if (ohci->next_config_rom != NULL) {
1960                 if (ohci->next_config_rom != ohci->config_rom) {
1961                         free_rom      = ohci->config_rom;
1962                         free_rom_bus  = ohci->config_rom_bus;
1963                 }
1964                 ohci->config_rom      = ohci->next_config_rom;
1965                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1966                 ohci->next_config_rom = NULL;
1967
1968                 /*
1969                  * Restore config_rom image and manually update
1970                  * config_rom registers.  Writing the header quadlet
1971                  * will indicate that the config rom is ready, so we
1972                  * do that last.
1973                  */
1974                 reg_write(ohci, OHCI1394_BusOptions,
1975                           be32_to_cpu(ohci->config_rom[2]));
1976                 ohci->config_rom[0] = ohci->next_header;
1977                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1978                           be32_to_cpu(ohci->next_header));
1979         }
1980
1981 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1982         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1983         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1984 #endif
1985
1986         spin_unlock_irqrestore(&ohci->lock, flags);
1987
1988         if (free_rom)
1989                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1990                                   free_rom, free_rom_bus);
1991
1992         log_selfids(ohci->node_id, generation,
1993                     self_id_count, ohci->self_id_buffer);
1994
1995         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1996                                  self_id_count, ohci->self_id_buffer,
1997                                  ohci->csr_state_setclear_abdicate);
1998         ohci->csr_state_setclear_abdicate = false;
1999 }
2000
2001 static irqreturn_t irq_handler(int irq, void *data)
2002 {
2003         struct fw_ohci *ohci = data;
2004         u32 event, iso_event;
2005         int i;
2006
2007         event = reg_read(ohci, OHCI1394_IntEventClear);
2008
2009         if (!event || !~event)
2010                 return IRQ_NONE;
2011
2012         /*
2013          * busReset and postedWriteErr must not be cleared yet
2014          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2015          */
2016         reg_write(ohci, OHCI1394_IntEventClear,
2017                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2018         log_irqs(event);
2019
2020         if (event & OHCI1394_selfIDComplete)
2021                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2022
2023         if (event & OHCI1394_RQPkt)
2024                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2025
2026         if (event & OHCI1394_RSPkt)
2027                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2028
2029         if (event & OHCI1394_reqTxComplete)
2030                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2031
2032         if (event & OHCI1394_respTxComplete)
2033                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2034
2035         if (event & OHCI1394_isochRx) {
2036                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2037                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2038
2039                 while (iso_event) {
2040                         i = ffs(iso_event) - 1;
2041                         tasklet_schedule(
2042                                 &ohci->ir_context_list[i].context.tasklet);
2043                         iso_event &= ~(1 << i);
2044                 }
2045         }
2046
2047         if (event & OHCI1394_isochTx) {
2048                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2049                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2050
2051                 while (iso_event) {
2052                         i = ffs(iso_event) - 1;
2053                         tasklet_schedule(
2054                                 &ohci->it_context_list[i].context.tasklet);
2055                         iso_event &= ~(1 << i);
2056                 }
2057         }
2058
2059         if (unlikely(event & OHCI1394_regAccessFail))
2060                 fw_error("Register access failure - "
2061                          "please notify linux1394-devel@lists.sf.net\n");
2062
2063         if (unlikely(event & OHCI1394_postedWriteErr)) {
2064                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2065                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2066                 reg_write(ohci, OHCI1394_IntEventClear,
2067                           OHCI1394_postedWriteErr);
2068                 if (printk_ratelimit())
2069                         fw_error("PCI posted write error\n");
2070         }
2071
2072         if (unlikely(event & OHCI1394_cycleTooLong)) {
2073                 if (printk_ratelimit())
2074                         fw_notify("isochronous cycle too long\n");
2075                 reg_write(ohci, OHCI1394_LinkControlSet,
2076                           OHCI1394_LinkControl_cycleMaster);
2077         }
2078
2079         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2080                 /*
2081                  * We need to clear this event bit in order to make
2082                  * cycleMatch isochronous I/O work.  In theory we should
2083                  * stop active cycleMatch iso contexts now and restart
2084                  * them at least two cycles later.  (FIXME?)
2085                  */
2086                 if (printk_ratelimit())
2087                         fw_notify("isochronous cycle inconsistent\n");
2088         }
2089
2090         if (unlikely(event & OHCI1394_unrecoverableError))
2091                 handle_dead_contexts(ohci);
2092
2093         if (event & OHCI1394_cycle64Seconds) {
2094                 spin_lock(&ohci->lock);
2095                 update_bus_time(ohci);
2096                 spin_unlock(&ohci->lock);
2097         } else
2098                 flush_writes(ohci);
2099
2100         return IRQ_HANDLED;
2101 }
2102
2103 static int software_reset(struct fw_ohci *ohci)
2104 {
2105         u32 val;
2106         int i;
2107
2108         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2109         for (i = 0; i < 500; i++) {
2110                 val = reg_read(ohci, OHCI1394_HCControlSet);
2111                 if (!~val)
2112                         return -ENODEV; /* Card was ejected. */
2113
2114                 if (!(val & OHCI1394_HCControl_softReset))
2115                         return 0;
2116
2117                 msleep(1);
2118         }
2119
2120         return -EBUSY;
2121 }
2122
2123 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2124 {
2125         size_t size = length * 4;
2126
2127         memcpy(dest, src, size);
2128         if (size < CONFIG_ROM_SIZE)
2129                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2130 }
2131
2132 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2133 {
2134         bool enable_1394a;
2135         int ret, clear, set, offset;
2136
2137         /* Check if the driver should configure link and PHY. */
2138         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2139               OHCI1394_HCControl_programPhyEnable))
2140                 return 0;
2141
2142         /* Paranoia: check whether the PHY supports 1394a, too. */
2143         enable_1394a = false;
2144         ret = read_phy_reg(ohci, 2);
2145         if (ret < 0)
2146                 return ret;
2147         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2148                 ret = read_paged_phy_reg(ohci, 1, 8);
2149                 if (ret < 0)
2150                         return ret;
2151                 if (ret >= 1)
2152                         enable_1394a = true;
2153         }
2154
2155         if (ohci->quirks & QUIRK_NO_1394A)
2156                 enable_1394a = false;
2157
2158         /* Configure PHY and link consistently. */
2159         if (enable_1394a) {
2160                 clear = 0;
2161                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2162         } else {
2163                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2164                 set = 0;
2165         }
2166         ret = update_phy_reg(ohci, 5, clear, set);
2167         if (ret < 0)
2168                 return ret;
2169
2170         if (enable_1394a)
2171                 offset = OHCI1394_HCControlSet;
2172         else
2173                 offset = OHCI1394_HCControlClear;
2174         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2175
2176         /* Clean up: configuration has been taken care of. */
2177         reg_write(ohci, OHCI1394_HCControlClear,
2178                   OHCI1394_HCControl_programPhyEnable);
2179
2180         return 0;
2181 }
2182
2183 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2184 {
2185         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2186         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2187         int reg, i;
2188
2189         reg = read_phy_reg(ohci, 2);
2190         if (reg < 0)
2191                 return reg;
2192         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2193                 return 0;
2194
2195         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2196                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2197                 if (reg < 0)
2198                         return reg;
2199                 if (reg != id[i])
2200                         return 0;
2201         }
2202         return 1;
2203 }
2204
2205 static int ohci_enable(struct fw_card *card,
2206                        const __be32 *config_rom, size_t length)
2207 {
2208         struct fw_ohci *ohci = fw_ohci(card);
2209         struct pci_dev *dev = to_pci_dev(card->device);
2210         u32 lps, seconds, version, irqs;
2211         int i, ret;
2212
2213         if (software_reset(ohci)) {
2214                 fw_error("Failed to reset ohci card.\n");
2215                 return -EBUSY;
2216         }
2217
2218         /*
2219          * Now enable LPS, which we need in order to start accessing
2220          * most of the registers.  In fact, on some cards (ALI M5251),
2221          * accessing registers in the SClk domain without LPS enabled
2222          * will lock up the machine.  Wait 50msec to make sure we have
2223          * full link enabled.  However, with some cards (well, at least
2224          * a JMicron PCIe card), we have to try again sometimes.
2225          */
2226         reg_write(ohci, OHCI1394_HCControlSet,
2227                   OHCI1394_HCControl_LPS |
2228                   OHCI1394_HCControl_postedWriteEnable);
2229         flush_writes(ohci);
2230
2231         for (lps = 0, i = 0; !lps && i < 3; i++) {
2232                 msleep(50);
2233                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2234                       OHCI1394_HCControl_LPS;
2235         }
2236
2237         if (!lps) {
2238                 fw_error("Failed to set Link Power Status\n");
2239                 return -EIO;
2240         }
2241
2242         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2243                 ret = probe_tsb41ba3d(ohci);
2244                 if (ret < 0)
2245                         return ret;
2246                 if (ret)
2247                         fw_notify("local TSB41BA3D phy\n");
2248                 else
2249                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2250         }
2251
2252         reg_write(ohci, OHCI1394_HCControlClear,
2253                   OHCI1394_HCControl_noByteSwapData);
2254
2255         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2256         reg_write(ohci, OHCI1394_LinkControlSet,
2257                   OHCI1394_LinkControl_cycleTimerEnable |
2258                   OHCI1394_LinkControl_cycleMaster);
2259
2260         reg_write(ohci, OHCI1394_ATRetries,
2261                   OHCI1394_MAX_AT_REQ_RETRIES |
2262                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2263                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2264                   (200 << 16));
2265
2266         seconds = lower_32_bits(get_seconds());
2267         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2268         ohci->bus_time = seconds & ~0x3f;
2269
2270         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2271         if (version >= OHCI_VERSION_1_1) {
2272                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2273                           0xfffffffe);
2274                 card->broadcast_channel_auto_allocated = true;
2275         }
2276
2277         /* Get implemented bits of the priority arbitration request counter. */
2278         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2279         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2280         reg_write(ohci, OHCI1394_FairnessControl, 0);
2281         card->priority_budget_implemented = ohci->pri_req_max != 0;
2282
2283         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2284         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2285         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2286
2287         ret = configure_1394a_enhancements(ohci);
2288         if (ret < 0)
2289                 return ret;
2290
2291         /* Activate link_on bit and contender bit in our self ID packets.*/
2292         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2293         if (ret < 0)
2294                 return ret;
2295
2296         /*
2297          * When the link is not yet enabled, the atomic config rom
2298          * update mechanism described below in ohci_set_config_rom()
2299          * is not active.  We have to update ConfigRomHeader and
2300          * BusOptions manually, and the write to ConfigROMmap takes
2301          * effect immediately.  We tie this to the enabling of the
2302          * link, so we have a valid config rom before enabling - the
2303          * OHCI requires that ConfigROMhdr and BusOptions have valid
2304          * values before enabling.
2305          *
2306          * However, when the ConfigROMmap is written, some controllers
2307          * always read back quadlets 0 and 2 from the config rom to
2308          * the ConfigRomHeader and BusOptions registers on bus reset.
2309          * They shouldn't do that in this initial case where the link
2310          * isn't enabled.  This means we have to use the same
2311          * workaround here, setting the bus header to 0 and then write
2312          * the right values in the bus reset tasklet.
2313          */
2314
2315         if (config_rom) {
2316                 ohci->next_config_rom =
2317                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2318                                            &ohci->next_config_rom_bus,
2319                                            GFP_KERNEL);
2320                 if (ohci->next_config_rom == NULL)
2321                         return -ENOMEM;
2322
2323                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2324         } else {
2325                 /*
2326                  * In the suspend case, config_rom is NULL, which
2327                  * means that we just reuse the old config rom.
2328                  */
2329                 ohci->next_config_rom = ohci->config_rom;
2330                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2331         }
2332
2333         ohci->next_header = ohci->next_config_rom[0];
2334         ohci->next_config_rom[0] = 0;
2335         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2336         reg_write(ohci, OHCI1394_BusOptions,
2337                   be32_to_cpu(ohci->next_config_rom[2]));
2338         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2339
2340         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2341
2342         if (!(ohci->quirks & QUIRK_NO_MSI))
2343                 pci_enable_msi(dev);
2344         if (request_irq(dev->irq, irq_handler,
2345                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2346                         ohci_driver_name, ohci)) {
2347                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2348                 pci_disable_msi(dev);
2349
2350                 if (config_rom) {
2351                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2352                                           ohci->next_config_rom,
2353                                           ohci->next_config_rom_bus);
2354                         ohci->next_config_rom = NULL;
2355                 }
2356                 return -EIO;
2357         }
2358
2359         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2360                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2361                 OHCI1394_isochTx | OHCI1394_isochRx |
2362                 OHCI1394_postedWriteErr |
2363                 OHCI1394_selfIDComplete |
2364                 OHCI1394_regAccessFail |
2365                 OHCI1394_cycle64Seconds |
2366                 OHCI1394_cycleInconsistent |
2367                 OHCI1394_unrecoverableError |
2368                 OHCI1394_cycleTooLong |
2369                 OHCI1394_masterIntEnable;
2370         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2371                 irqs |= OHCI1394_busReset;
2372         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2373
2374         reg_write(ohci, OHCI1394_HCControlSet,
2375                   OHCI1394_HCControl_linkEnable |
2376                   OHCI1394_HCControl_BIBimageValid);
2377
2378         reg_write(ohci, OHCI1394_LinkControlSet,
2379                   OHCI1394_LinkControl_rcvSelfID |
2380                   OHCI1394_LinkControl_rcvPhyPkt);
2381
2382         ar_context_run(&ohci->ar_request_ctx);
2383         ar_context_run(&ohci->ar_response_ctx);
2384
2385         flush_writes(ohci);
2386
2387         /* We are ready to go, reset bus to finish initialization. */
2388         fw_schedule_bus_reset(&ohci->card, false, true);
2389
2390         return 0;
2391 }
2392
2393 static int ohci_set_config_rom(struct fw_card *card,
2394                                const __be32 *config_rom, size_t length)
2395 {
2396         struct fw_ohci *ohci;
2397         unsigned long flags;
2398         __be32 *next_config_rom;
2399         dma_addr_t uninitialized_var(next_config_rom_bus);
2400
2401         ohci = fw_ohci(card);
2402
2403         /*
2404          * When the OHCI controller is enabled, the config rom update
2405          * mechanism is a bit tricky, but easy enough to use.  See
2406          * section 5.5.6 in the OHCI specification.
2407          *
2408          * The OHCI controller caches the new config rom address in a
2409          * shadow register (ConfigROMmapNext) and needs a bus reset
2410          * for the changes to take place.  When the bus reset is
2411          * detected, the controller loads the new values for the
2412          * ConfigRomHeader and BusOptions registers from the specified
2413          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2414          * shadow register. All automatically and atomically.
2415          *
2416          * Now, there's a twist to this story.  The automatic load of
2417          * ConfigRomHeader and BusOptions doesn't honor the
2418          * noByteSwapData bit, so with a be32 config rom, the
2419          * controller will load be32 values in to these registers
2420          * during the atomic update, even on litte endian
2421          * architectures.  The workaround we use is to put a 0 in the
2422          * header quadlet; 0 is endian agnostic and means that the
2423          * config rom isn't ready yet.  In the bus reset tasklet we
2424          * then set up the real values for the two registers.
2425          *
2426          * We use ohci->lock to avoid racing with the code that sets
2427          * ohci->next_config_rom to NULL (see bus_reset_work).
2428          */
2429
2430         next_config_rom =
2431                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2432                                    &next_config_rom_bus, GFP_KERNEL);
2433         if (next_config_rom == NULL)
2434                 return -ENOMEM;
2435
2436         spin_lock_irqsave(&ohci->lock, flags);
2437
2438         /*
2439          * If there is not an already pending config_rom update,
2440          * push our new allocation into the ohci->next_config_rom
2441          * and then mark the local variable as null so that we
2442          * won't deallocate the new buffer.
2443          *
2444          * OTOH, if there is a pending config_rom update, just
2445          * use that buffer with the new config_rom data, and
2446          * let this routine free the unused DMA allocation.
2447          */
2448
2449         if (ohci->next_config_rom == NULL) {
2450                 ohci->next_config_rom = next_config_rom;
2451                 ohci->next_config_rom_bus = next_config_rom_bus;
2452                 next_config_rom = NULL;
2453         }
2454
2455         copy_config_rom(ohci->next_config_rom, config_rom, length);
2456
2457         ohci->next_header = config_rom[0];
2458         ohci->next_config_rom[0] = 0;
2459
2460         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2461
2462         spin_unlock_irqrestore(&ohci->lock, flags);
2463
2464         /* If we didn't use the DMA allocation, delete it. */
2465         if (next_config_rom != NULL)
2466                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2467                                   next_config_rom, next_config_rom_bus);
2468
2469         /*
2470          * Now initiate a bus reset to have the changes take
2471          * effect. We clean up the old config rom memory and DMA
2472          * mappings in the bus reset tasklet, since the OHCI
2473          * controller could need to access it before the bus reset
2474          * takes effect.
2475          */
2476
2477         fw_schedule_bus_reset(&ohci->card, true, true);
2478
2479         return 0;
2480 }
2481
2482 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2483 {
2484         struct fw_ohci *ohci = fw_ohci(card);
2485
2486         at_context_transmit(&ohci->at_request_ctx, packet);
2487 }
2488
2489 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2490 {
2491         struct fw_ohci *ohci = fw_ohci(card);
2492
2493         at_context_transmit(&ohci->at_response_ctx, packet);
2494 }
2495
2496 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2497 {
2498         struct fw_ohci *ohci = fw_ohci(card);
2499         struct context *ctx = &ohci->at_request_ctx;
2500         struct driver_data *driver_data = packet->driver_data;
2501         int ret = -ENOENT;
2502
2503         tasklet_disable(&ctx->tasklet);
2504
2505         if (packet->ack != 0)
2506                 goto out;
2507
2508         if (packet->payload_mapped)
2509                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2510                                  packet->payload_length, DMA_TO_DEVICE);
2511
2512         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2513         driver_data->packet = NULL;
2514         packet->ack = RCODE_CANCELLED;
2515         packet->callback(packet, &ohci->card, packet->ack);
2516         ret = 0;
2517  out:
2518         tasklet_enable(&ctx->tasklet);
2519
2520         return ret;
2521 }
2522
2523 static int ohci_enable_phys_dma(struct fw_card *card,
2524                                 int node_id, int generation)
2525 {
2526 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2527         return 0;
2528 #else
2529         struct fw_ohci *ohci = fw_ohci(card);
2530         unsigned long flags;
2531         int n, ret = 0;
2532
2533         /*
2534          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2535          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2536          */
2537
2538         spin_lock_irqsave(&ohci->lock, flags);
2539
2540         if (ohci->generation != generation) {
2541                 ret = -ESTALE;
2542                 goto out;
2543         }
2544
2545         /*
2546          * Note, if the node ID contains a non-local bus ID, physical DMA is
2547          * enabled for _all_ nodes on remote buses.
2548          */
2549
2550         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2551         if (n < 32)
2552                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2553         else
2554                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2555
2556         flush_writes(ohci);
2557  out:
2558         spin_unlock_irqrestore(&ohci->lock, flags);
2559
2560         return ret;
2561 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2562 }
2563
2564 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2565 {
2566         struct fw_ohci *ohci = fw_ohci(card);
2567         unsigned long flags;
2568         u32 value;
2569
2570         switch (csr_offset) {
2571         case CSR_STATE_CLEAR:
2572         case CSR_STATE_SET:
2573                 if (ohci->is_root &&
2574                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2575                      OHCI1394_LinkControl_cycleMaster))
2576                         value = CSR_STATE_BIT_CMSTR;
2577                 else
2578                         value = 0;
2579                 if (ohci->csr_state_setclear_abdicate)
2580                         value |= CSR_STATE_BIT_ABDICATE;
2581
2582                 return value;
2583
2584         case CSR_NODE_IDS:
2585                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2586
2587         case CSR_CYCLE_TIME:
2588                 return get_cycle_time(ohci);
2589
2590         case CSR_BUS_TIME:
2591                 /*
2592                  * We might be called just after the cycle timer has wrapped
2593                  * around but just before the cycle64Seconds handler, so we
2594                  * better check here, too, if the bus time needs to be updated.
2595                  */
2596                 spin_lock_irqsave(&ohci->lock, flags);
2597                 value = update_bus_time(ohci);
2598                 spin_unlock_irqrestore(&ohci->lock, flags);
2599                 return value;
2600
2601         case CSR_BUSY_TIMEOUT:
2602                 value = reg_read(ohci, OHCI1394_ATRetries);
2603                 return (value >> 4) & 0x0ffff00f;
2604
2605         case CSR_PRIORITY_BUDGET:
2606                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2607                         (ohci->pri_req_max << 8);
2608
2609         default:
2610                 WARN_ON(1);
2611                 return 0;
2612         }
2613 }
2614
2615 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2616 {
2617         struct fw_ohci *ohci = fw_ohci(card);
2618         unsigned long flags;
2619
2620         switch (csr_offset) {
2621         case CSR_STATE_CLEAR:
2622                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2623                         reg_write(ohci, OHCI1394_LinkControlClear,
2624                                   OHCI1394_LinkControl_cycleMaster);
2625                         flush_writes(ohci);
2626                 }
2627                 if (value & CSR_STATE_BIT_ABDICATE)
2628                         ohci->csr_state_setclear_abdicate = false;
2629                 break;
2630
2631         case CSR_STATE_SET:
2632                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2633                         reg_write(ohci, OHCI1394_LinkControlSet,
2634                                   OHCI1394_LinkControl_cycleMaster);
2635                         flush_writes(ohci);
2636                 }
2637                 if (value & CSR_STATE_BIT_ABDICATE)
2638                         ohci->csr_state_setclear_abdicate = true;
2639                 break;
2640
2641         case CSR_NODE_IDS:
2642                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2643                 flush_writes(ohci);
2644                 break;
2645
2646         case CSR_CYCLE_TIME:
2647                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2648                 reg_write(ohci, OHCI1394_IntEventSet,
2649                           OHCI1394_cycleInconsistent);
2650                 flush_writes(ohci);
2651                 break;
2652
2653         case CSR_BUS_TIME:
2654                 spin_lock_irqsave(&ohci->lock, flags);
2655                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2656                 spin_unlock_irqrestore(&ohci->lock, flags);
2657                 break;
2658
2659         case CSR_BUSY_TIMEOUT:
2660                 value = (value & 0xf) | ((value & 0xf) << 4) |
2661                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2662                 reg_write(ohci, OHCI1394_ATRetries, value);
2663                 flush_writes(ohci);
2664                 break;
2665
2666         case CSR_PRIORITY_BUDGET:
2667                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2668                 flush_writes(ohci);
2669                 break;
2670
2671         default:
2672                 WARN_ON(1);
2673                 break;
2674         }
2675 }
2676
2677 static void copy_iso_headers(struct iso_context *ctx, void *p)
2678 {
2679         int i = ctx->header_length;
2680
2681         if (i + ctx->base.header_size > PAGE_SIZE)
2682                 return;
2683
2684         /*
2685          * The iso header is byteswapped to little endian by
2686          * the controller, but the remaining header quadlets
2687          * are big endian.  We want to present all the headers
2688          * as big endian, so we have to swap the first quadlet.
2689          */
2690         if (ctx->base.header_size > 0)
2691                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2692         if (ctx->base.header_size > 4)
2693                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2694         if (ctx->base.header_size > 8)
2695                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2696         ctx->header_length += ctx->base.header_size;
2697 }
2698
2699 static int handle_ir_packet_per_buffer(struct context *context,
2700                                        struct descriptor *d,
2701                                        struct descriptor *last)
2702 {
2703         struct iso_context *ctx =
2704                 container_of(context, struct iso_context, context);
2705         struct descriptor *pd;
2706         u32 buffer_dma;
2707         __le32 *ir_header;
2708         void *p;
2709
2710         for (pd = d; pd <= last; pd++)
2711                 if (pd->transfer_status)
2712                         break;
2713         if (pd > last)
2714                 /* Descriptor(s) not done yet, stop iteration */
2715                 return 0;
2716
2717         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2718                 d++;
2719                 buffer_dma = le32_to_cpu(d->data_address);
2720                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2721                                               buffer_dma & PAGE_MASK,
2722                                               buffer_dma & ~PAGE_MASK,
2723                                               le16_to_cpu(d->req_count),
2724                                               DMA_FROM_DEVICE);
2725         }
2726
2727         p = last + 1;
2728         copy_iso_headers(ctx, p);
2729
2730         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2731                 ir_header = (__le32 *) p;
2732                 ctx->base.callback.sc(&ctx->base,
2733                                       le32_to_cpu(ir_header[0]) & 0xffff,
2734                                       ctx->header_length, ctx->header,
2735                                       ctx->base.callback_data);
2736                 ctx->header_length = 0;
2737         }
2738
2739         return 1;
2740 }
2741
2742 /* d == last because each descriptor block is only a single descriptor. */
2743 static int handle_ir_buffer_fill(struct context *context,
2744                                  struct descriptor *d,
2745                                  struct descriptor *last)
2746 {
2747         struct iso_context *ctx =
2748                 container_of(context, struct iso_context, context);
2749         u32 buffer_dma;
2750
2751         if (!last->transfer_status)
2752                 /* Descriptor(s) not done yet, stop iteration */
2753                 return 0;
2754
2755         buffer_dma = le32_to_cpu(last->data_address);
2756         dma_sync_single_range_for_cpu(context->ohci->card.device,
2757                                       buffer_dma & PAGE_MASK,
2758                                       buffer_dma & ~PAGE_MASK,
2759                                       le16_to_cpu(last->req_count),
2760                                       DMA_FROM_DEVICE);
2761
2762         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2763                 ctx->base.callback.mc(&ctx->base,
2764                                       le32_to_cpu(last->data_address) +
2765                                       le16_to_cpu(last->req_count) -
2766                                       le16_to_cpu(last->res_count),
2767                                       ctx->base.callback_data);
2768
2769         return 1;
2770 }
2771
2772 static inline void sync_it_packet_for_cpu(struct context *context,
2773                                           struct descriptor *pd)
2774 {
2775         __le16 control;
2776         u32 buffer_dma;
2777
2778         /* only packets beginning with OUTPUT_MORE* have data buffers */
2779         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2780                 return;
2781
2782         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2783         pd += 2;
2784
2785         /*
2786          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2787          * data buffer is in the context program's coherent page and must not
2788          * be synced.
2789          */
2790         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2791             (context->current_bus          & PAGE_MASK)) {
2792                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2793                         return;
2794                 pd++;
2795         }
2796
2797         do {
2798                 buffer_dma = le32_to_cpu(pd->data_address);
2799                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2800                                               buffer_dma & PAGE_MASK,
2801                                               buffer_dma & ~PAGE_MASK,
2802                                               le16_to_cpu(pd->req_count),
2803                                               DMA_TO_DEVICE);
2804                 control = pd->control;
2805                 pd++;
2806         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2807 }
2808
2809 static int handle_it_packet(struct context *context,
2810                             struct descriptor *d,
2811                             struct descriptor *last)
2812 {
2813         struct iso_context *ctx =
2814                 container_of(context, struct iso_context, context);
2815         int i;
2816         struct descriptor *pd;
2817
2818         for (pd = d; pd <= last; pd++)
2819                 if (pd->transfer_status)
2820                         break;
2821         if (pd > last)
2822                 /* Descriptor(s) not done yet, stop iteration */
2823                 return 0;
2824
2825         sync_it_packet_for_cpu(context, d);
2826
2827         i = ctx->header_length;
2828         if (i + 4 < PAGE_SIZE) {
2829                 /* Present this value as big-endian to match the receive code */
2830                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2831                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2832                                 le16_to_cpu(pd->res_count));
2833                 ctx->header_length += 4;
2834         }
2835         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2836                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2837                                       ctx->header_length, ctx->header,
2838                                       ctx->base.callback_data);
2839                 ctx->header_length = 0;
2840         }
2841         return 1;
2842 }
2843
2844 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2845 {
2846         u32 hi = channels >> 32, lo = channels;
2847
2848         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2849         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2850         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2851         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2852         mmiowb();
2853         ohci->mc_channels = channels;
2854 }
2855
2856 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2857                                 int type, int channel, size_t header_size)
2858 {
2859         struct fw_ohci *ohci = fw_ohci(card);
2860         struct iso_context *uninitialized_var(ctx);
2861         descriptor_callback_t uninitialized_var(callback);
2862         u64 *uninitialized_var(channels);
2863         u32 *uninitialized_var(mask), uninitialized_var(regs);
2864         unsigned long flags;
2865         int index, ret = -EBUSY;
2866
2867         spin_lock_irqsave(&ohci->lock, flags);
2868
2869         switch (type) {
2870         case FW_ISO_CONTEXT_TRANSMIT:
2871                 mask     = &ohci->it_context_mask;
2872                 callback = handle_it_packet;
2873                 index    = ffs(*mask) - 1;
2874                 if (index >= 0) {
2875                         *mask &= ~(1 << index);
2876                         regs = OHCI1394_IsoXmitContextBase(index);
2877                         ctx  = &ohci->it_context_list[index];
2878                 }
2879                 break;
2880
2881         case FW_ISO_CONTEXT_RECEIVE:
2882                 channels = &ohci->ir_context_channels;
2883                 mask     = &ohci->ir_context_mask;
2884                 callback = handle_ir_packet_per_buffer;
2885                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2886                 if (index >= 0) {
2887                         *channels &= ~(1ULL << channel);
2888                         *mask     &= ~(1 << index);
2889                         regs = OHCI1394_IsoRcvContextBase(index);
2890                         ctx  = &ohci->ir_context_list[index];
2891                 }
2892                 break;
2893
2894         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2895                 mask     = &ohci->ir_context_mask;
2896                 callback = handle_ir_buffer_fill;
2897                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2898                 if (index >= 0) {
2899                         ohci->mc_allocated = true;
2900                         *mask &= ~(1 << index);
2901                         regs = OHCI1394_IsoRcvContextBase(index);
2902                         ctx  = &ohci->ir_context_list[index];
2903                 }
2904                 break;
2905
2906         default:
2907                 index = -1;
2908                 ret = -ENOSYS;
2909         }
2910
2911         spin_unlock_irqrestore(&ohci->lock, flags);
2912
2913         if (index < 0)
2914                 return ERR_PTR(ret);
2915
2916         memset(ctx, 0, sizeof(*ctx));
2917         ctx->header_length = 0;
2918         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2919         if (ctx->header == NULL) {
2920                 ret = -ENOMEM;
2921                 goto out;
2922         }
2923         ret = context_init(&ctx->context, ohci, regs, callback);
2924         if (ret < 0)
2925                 goto out_with_header;
2926
2927         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2928                 set_multichannel_mask(ohci, 0);
2929
2930         return &ctx->base;
2931
2932  out_with_header:
2933         free_page((unsigned long)ctx->header);
2934  out:
2935         spin_lock_irqsave(&ohci->lock, flags);
2936
2937         switch (type) {
2938         case FW_ISO_CONTEXT_RECEIVE:
2939                 *channels |= 1ULL << channel;
2940                 break;
2941
2942         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2943                 ohci->mc_allocated = false;
2944                 break;
2945         }
2946         *mask |= 1 << index;
2947
2948         spin_unlock_irqrestore(&ohci->lock, flags);
2949
2950         return ERR_PTR(ret);
2951 }
2952
2953 static int ohci_start_iso(struct fw_iso_context *base,
2954                           s32 cycle, u32 sync, u32 tags)
2955 {
2956         struct iso_context *ctx = container_of(base, struct iso_context, base);
2957         struct fw_ohci *ohci = ctx->context.ohci;
2958         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2959         int index;
2960
2961         /* the controller cannot start without any queued packets */
2962         if (ctx->context.last->branch_address == 0)
2963                 return -ENODATA;
2964
2965         switch (ctx->base.type) {
2966         case FW_ISO_CONTEXT_TRANSMIT:
2967                 index = ctx - ohci->it_context_list;
2968                 match = 0;
2969                 if (cycle >= 0)
2970                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2971                                 (cycle & 0x7fff) << 16;
2972
2973                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2974                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2975                 context_run(&ctx->context, match);
2976                 break;
2977
2978         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2979                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2980                 /* fall through */
2981         case FW_ISO_CONTEXT_RECEIVE:
2982                 index = ctx - ohci->ir_context_list;
2983                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2984                 if (cycle >= 0) {
2985                         match |= (cycle & 0x07fff) << 12;
2986                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2987                 }
2988
2989                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2990                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2991                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2992                 context_run(&ctx->context, control);
2993
2994                 ctx->sync = sync;
2995                 ctx->tags = tags;
2996
2997                 break;
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int ohci_stop_iso(struct fw_iso_context *base)
3004 {
3005         struct fw_ohci *ohci = fw_ohci(base->card);
3006         struct iso_context *ctx = container_of(base, struct iso_context, base);
3007         int index;
3008
3009         switch (ctx->base.type) {
3010         case FW_ISO_CONTEXT_TRANSMIT:
3011                 index = ctx - ohci->it_context_list;
3012                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3013                 break;
3014
3015         case FW_ISO_CONTEXT_RECEIVE:
3016         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3017                 index = ctx - ohci->ir_context_list;
3018                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3019                 break;
3020         }
3021         flush_writes(ohci);
3022         context_stop(&ctx->context);
3023         tasklet_kill(&ctx->context.tasklet);
3024
3025         return 0;
3026 }
3027
3028 static void ohci_free_iso_context(struct fw_iso_context *base)
3029 {
3030         struct fw_ohci *ohci = fw_ohci(base->card);
3031         struct iso_context *ctx = container_of(base, struct iso_context, base);
3032         unsigned long flags;
3033         int index;
3034
3035         ohci_stop_iso(base);
3036         context_release(&ctx->context);
3037         free_page((unsigned long)ctx->header);
3038
3039         spin_lock_irqsave(&ohci->lock, flags);
3040
3041         switch (base->type) {
3042         case FW_ISO_CONTEXT_TRANSMIT:
3043                 index = ctx - ohci->it_context_list;
3044                 ohci->it_context_mask |= 1 << index;
3045                 break;
3046
3047         case FW_ISO_CONTEXT_RECEIVE:
3048                 index = ctx - ohci->ir_context_list;
3049                 ohci->ir_context_mask |= 1 << index;
3050                 ohci->ir_context_channels |= 1ULL << base->channel;
3051                 break;
3052
3053         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3054                 index = ctx - ohci->ir_context_list;
3055                 ohci->ir_context_mask |= 1 << index;
3056                 ohci->ir_context_channels |= ohci->mc_channels;
3057                 ohci->mc_channels = 0;
3058                 ohci->mc_allocated = false;
3059                 break;
3060         }
3061
3062         spin_unlock_irqrestore(&ohci->lock, flags);
3063 }
3064
3065 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3066 {
3067         struct fw_ohci *ohci = fw_ohci(base->card);
3068         unsigned long flags;
3069         int ret;
3070
3071         switch (base->type) {
3072         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3073
3074                 spin_lock_irqsave(&ohci->lock, flags);
3075
3076                 /* Don't allow multichannel to grab other contexts' channels. */
3077                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3078                         *channels = ohci->ir_context_channels;
3079                         ret = -EBUSY;
3080                 } else {
3081                         set_multichannel_mask(ohci, *channels);
3082                         ret = 0;
3083                 }
3084
3085                 spin_unlock_irqrestore(&ohci->lock, flags);
3086
3087                 break;
3088         default:
3089                 ret = -EINVAL;
3090         }
3091
3092         return ret;
3093 }
3094
3095 #ifdef CONFIG_PM
3096 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3097 {
3098         int i;
3099         struct iso_context *ctx;
3100
3101         for (i = 0 ; i < ohci->n_ir ; i++) {
3102                 ctx = &ohci->ir_context_list[i];
3103                 if (ctx->context.running)
3104                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3105         }
3106
3107         for (i = 0 ; i < ohci->n_it ; i++) {
3108                 ctx = &ohci->it_context_list[i];
3109                 if (ctx->context.running)
3110                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3111         }
3112 }
3113 #endif
3114
3115 static int queue_iso_transmit(struct iso_context *ctx,
3116                               struct fw_iso_packet *packet,
3117                               struct fw_iso_buffer *buffer,
3118                               unsigned long payload)
3119 {
3120         struct descriptor *d, *last, *pd;
3121         struct fw_iso_packet *p;
3122         __le32 *header;
3123         dma_addr_t d_bus, page_bus;
3124         u32 z, header_z, payload_z, irq;
3125         u32 payload_index, payload_end_index, next_page_index;
3126         int page, end_page, i, length, offset;
3127
3128         p = packet;
3129         payload_index = payload;
3130
3131         if (p->skip)
3132                 z = 1;
3133         else
3134                 z = 2;
3135         if (p->header_length > 0)
3136                 z++;
3137
3138         /* Determine the first page the payload isn't contained in. */
3139         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3140         if (p->payload_length > 0)
3141                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3142         else
3143                 payload_z = 0;
3144
3145         z += payload_z;
3146
3147         /* Get header size in number of descriptors. */
3148         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3149
3150         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3151         if (d == NULL)
3152                 return -ENOMEM;
3153
3154         if (!p->skip) {
3155                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3156                 d[0].req_count = cpu_to_le16(8);
3157                 /*
3158                  * Link the skip address to this descriptor itself.  This causes
3159                  * a context to skip a cycle whenever lost cycles or FIFO
3160                  * overruns occur, without dropping the data.  The application
3161                  * should then decide whether this is an error condition or not.
3162                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3163                  */
3164                 d[0].branch_address = cpu_to_le32(d_bus | z);
3165
3166                 header = (__le32 *) &d[1];
3167                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3168                                         IT_HEADER_TAG(p->tag) |
3169                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3170                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3171                                         IT_HEADER_SPEED(ctx->base.speed));
3172                 header[1] =
3173                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3174                                                           p->payload_length));
3175         }
3176
3177         if (p->header_length > 0) {
3178                 d[2].req_count    = cpu_to_le16(p->header_length);
3179                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3180                 memcpy(&d[z], p->header, p->header_length);
3181         }
3182
3183         pd = d + z - payload_z;
3184         payload_end_index = payload_index + p->payload_length;
3185         for (i = 0; i < payload_z; i++) {
3186                 page               = payload_index >> PAGE_SHIFT;
3187                 offset             = payload_index & ~PAGE_MASK;
3188                 next_page_index    = (page + 1) << PAGE_SHIFT;
3189                 length             =
3190                         min(next_page_index, payload_end_index) - payload_index;
3191                 pd[i].req_count    = cpu_to_le16(length);
3192
3193                 page_bus = page_private(buffer->pages[page]);
3194                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3195
3196                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3197                                                  page_bus, offset, length,
3198                                                  DMA_TO_DEVICE);
3199
3200                 payload_index += length;
3201         }
3202
3203         if (p->interrupt)
3204                 irq = DESCRIPTOR_IRQ_ALWAYS;
3205         else
3206                 irq = DESCRIPTOR_NO_IRQ;
3207
3208         last = z == 2 ? d : d + z - 1;
3209         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3210                                      DESCRIPTOR_STATUS |
3211                                      DESCRIPTOR_BRANCH_ALWAYS |
3212                                      irq);
3213
3214         context_append(&ctx->context, d, z, header_z);
3215
3216         return 0;
3217 }
3218
3219 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3220                                        struct fw_iso_packet *packet,
3221                                        struct fw_iso_buffer *buffer,
3222                                        unsigned long payload)
3223 {
3224         struct device *device = ctx->context.ohci->card.device;
3225         struct descriptor *d, *pd;
3226         dma_addr_t d_bus, page_bus;
3227         u32 z, header_z, rest;
3228         int i, j, length;
3229         int page, offset, packet_count, header_size, payload_per_buffer;
3230
3231         /*
3232          * The OHCI controller puts the isochronous header and trailer in the
3233          * buffer, so we need at least 8 bytes.
3234          */
3235         packet_count = packet->header_length / ctx->base.header_size;
3236         header_size  = max(ctx->base.header_size, (size_t)8);
3237
3238         /* Get header size in number of descriptors. */
3239         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3240         page     = payload >> PAGE_SHIFT;
3241         offset   = payload & ~PAGE_MASK;
3242         payload_per_buffer = packet->payload_length / packet_count;
3243
3244         for (i = 0; i < packet_count; i++) {
3245                 /* d points to the header descriptor */
3246                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3247                 d = context_get_descriptors(&ctx->context,
3248                                 z + header_z, &d_bus);
3249                 if (d == NULL)
3250                         return -ENOMEM;
3251
3252                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3253                                               DESCRIPTOR_INPUT_MORE);
3254                 if (packet->skip && i == 0)
3255                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3256                 d->req_count    = cpu_to_le16(header_size);
3257                 d->res_count    = d->req_count;
3258                 d->transfer_status = 0;
3259                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3260
3261                 rest = payload_per_buffer;
3262                 pd = d;
3263                 for (j = 1; j < z; j++) {
3264                         pd++;
3265                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3266                                                   DESCRIPTOR_INPUT_MORE);
3267
3268                         if (offset + rest < PAGE_SIZE)
3269                                 length = rest;
3270                         else
3271                                 length = PAGE_SIZE - offset;
3272                         pd->req_count = cpu_to_le16(length);
3273                         pd->res_count = pd->req_count;
3274                         pd->transfer_status = 0;
3275
3276                         page_bus = page_private(buffer->pages[page]);
3277                         pd->data_address = cpu_to_le32(page_bus + offset);
3278
3279                         dma_sync_single_range_for_device(device, page_bus,
3280                                                          offset, length,
3281                                                          DMA_FROM_DEVICE);
3282
3283                         offset = (offset + length) & ~PAGE_MASK;
3284                         rest -= length;
3285                         if (offset == 0)
3286                                 page++;
3287                 }
3288                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3289                                           DESCRIPTOR_INPUT_LAST |
3290                                           DESCRIPTOR_BRANCH_ALWAYS);
3291                 if (packet->interrupt && i == packet_count - 1)
3292                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3293
3294                 context_append(&ctx->context, d, z, header_z);
3295         }
3296
3297         return 0;
3298 }
3299
3300 static int queue_iso_buffer_fill(struct iso_context *ctx,
3301                                  struct fw_iso_packet *packet,
3302                                  struct fw_iso_buffer *buffer,
3303                                  unsigned long payload)
3304 {
3305         struct descriptor *d;
3306         dma_addr_t d_bus, page_bus;
3307         int page, offset, rest, z, i, length;
3308
3309         page   = payload >> PAGE_SHIFT;
3310         offset = payload & ~PAGE_MASK;
3311         rest   = packet->payload_length;
3312
3313         /* We need one descriptor for each page in the buffer. */
3314         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3315
3316         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3317                 return -EFAULT;
3318
3319         for (i = 0; i < z; i++) {
3320                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3321                 if (d == NULL)
3322                         return -ENOMEM;
3323
3324                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3325                                          DESCRIPTOR_BRANCH_ALWAYS);
3326                 if (packet->skip && i == 0)
3327                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3328                 if (packet->interrupt && i == z - 1)
3329                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3330
3331                 if (offset + rest < PAGE_SIZE)
3332                         length = rest;
3333                 else
3334                         length = PAGE_SIZE - offset;
3335                 d->req_count = cpu_to_le16(length);
3336                 d->res_count = d->req_count;
3337                 d->transfer_status = 0;
3338
3339                 page_bus = page_private(buffer->pages[page]);
3340                 d->data_address = cpu_to_le32(page_bus + offset);
3341
3342                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3343                                                  page_bus, offset, length,
3344                                                  DMA_FROM_DEVICE);
3345
3346                 rest -= length;
3347                 offset = 0;
3348                 page++;
3349
3350                 context_append(&ctx->context, d, 1, 0);
3351         }
3352
3353         return 0;
3354 }
3355
3356 static int ohci_queue_iso(struct fw_iso_context *base,
3357                           struct fw_iso_packet *packet,
3358                           struct fw_iso_buffer *buffer,
3359                           unsigned long payload)
3360 {
3361         struct iso_context *ctx = container_of(base, struct iso_context, base);
3362         unsigned long flags;
3363         int ret = -ENOSYS;
3364
3365         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3366         switch (base->type) {
3367         case FW_ISO_CONTEXT_TRANSMIT:
3368                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3369                 break;
3370         case FW_ISO_CONTEXT_RECEIVE:
3371                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3372                 break;
3373         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3374                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3375                 break;
3376         }
3377         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3378
3379         return ret;
3380 }
3381
3382 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3383 {
3384         struct context *ctx =
3385                         &container_of(base, struct iso_context, base)->context;
3386
3387         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3388 }
3389
3390 static const struct fw_card_driver ohci_driver = {
3391         .enable                 = ohci_enable,
3392         .read_phy_reg           = ohci_read_phy_reg,
3393         .update_phy_reg         = ohci_update_phy_reg,
3394         .set_config_rom         = ohci_set_config_rom,
3395         .send_request           = ohci_send_request,
3396         .send_response          = ohci_send_response,
3397         .cancel_packet          = ohci_cancel_packet,
3398         .enable_phys_dma        = ohci_enable_phys_dma,
3399         .read_csr               = ohci_read_csr,
3400         .write_csr              = ohci_write_csr,
3401
3402         .allocate_iso_context   = ohci_allocate_iso_context,
3403         .free_iso_context       = ohci_free_iso_context,
3404         .set_iso_channels       = ohci_set_iso_channels,
3405         .queue_iso              = ohci_queue_iso,
3406         .flush_queue_iso        = ohci_flush_queue_iso,
3407         .start_iso              = ohci_start_iso,
3408         .stop_iso               = ohci_stop_iso,
3409 };
3410
3411 #ifdef CONFIG_PPC_PMAC
3412 static void pmac_ohci_on(struct pci_dev *dev)
3413 {
3414         if (machine_is(powermac)) {
3415                 struct device_node *ofn = pci_device_to_OF_node(dev);
3416
3417                 if (ofn) {
3418                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3419                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3420                 }
3421         }
3422 }
3423
3424 static void pmac_ohci_off(struct pci_dev *dev)
3425 {
3426         if (machine_is(powermac)) {
3427                 struct device_node *ofn = pci_device_to_OF_node(dev);
3428
3429                 if (ofn) {
3430                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3431                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3432                 }
3433         }
3434 }
3435 #else
3436 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3437 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3438 #endif /* CONFIG_PPC_PMAC */
3439
3440 static int __devinit pci_probe(struct pci_dev *dev,
3441                                const struct pci_device_id *ent)
3442 {
3443         struct fw_ohci *ohci;
3444         u32 bus_options, max_receive, link_speed, version;
3445         u64 guid;
3446         int i, err;
3447         size_t size;
3448
3449         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3450                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3451                 return -ENOSYS;
3452         }
3453
3454         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3455         if (ohci == NULL) {
3456                 err = -ENOMEM;
3457                 goto fail;
3458         }
3459
3460         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3461
3462         pmac_ohci_on(dev);
3463
3464         err = pci_enable_device(dev);
3465         if (err) {
3466                 fw_error("Failed to enable OHCI hardware\n");
3467                 goto fail_free;
3468         }
3469
3470         pci_set_master(dev);
3471         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3472         pci_set_drvdata(dev, ohci);
3473
3474         spin_lock_init(&ohci->lock);
3475         mutex_init(&ohci->phy_reg_mutex);
3476
3477         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3478
3479         err = pci_request_region(dev, 0, ohci_driver_name);
3480         if (err) {
3481                 fw_error("MMIO resource unavailable\n");
3482                 goto fail_disable;
3483         }
3484
3485         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3486         if (ohci->registers == NULL) {
3487                 fw_error("Failed to remap registers\n");
3488                 err = -ENXIO;
3489                 goto fail_iomem;
3490         }
3491
3492         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3493                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3494                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3495                      ohci_quirks[i].device == dev->device) &&
3496                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3497                      ohci_quirks[i].revision >= dev->revision)) {
3498                         ohci->quirks = ohci_quirks[i].flags;
3499                         break;
3500                 }
3501         if (param_quirks)
3502                 ohci->quirks = param_quirks;
3503
3504         /*
3505          * Because dma_alloc_coherent() allocates at least one page,
3506          * we save space by using a common buffer for the AR request/
3507          * response descriptors and the self IDs buffer.
3508          */
3509         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3510         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3511         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3512                                                PAGE_SIZE,
3513                                                &ohci->misc_buffer_bus,
3514                                                GFP_KERNEL);
3515         if (!ohci->misc_buffer) {
3516                 err = -ENOMEM;
3517                 goto fail_iounmap;
3518         }
3519
3520         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3521                               OHCI1394_AsReqRcvContextControlSet);
3522         if (err < 0)
3523                 goto fail_misc_buf;
3524
3525         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3526                               OHCI1394_AsRspRcvContextControlSet);
3527         if (err < 0)
3528                 goto fail_arreq_ctx;
3529
3530         err = context_init(&ohci->at_request_ctx, ohci,
3531                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3532         if (err < 0)
3533                 goto fail_arrsp_ctx;
3534
3535         err = context_init(&ohci->at_response_ctx, ohci,
3536                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3537         if (err < 0)
3538                 goto fail_atreq_ctx;
3539
3540         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3541         ohci->ir_context_channels = ~0ULL;
3542         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3543         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3544         ohci->ir_context_mask = ohci->ir_context_support;
3545         ohci->n_ir = hweight32(ohci->ir_context_mask);
3546         size = sizeof(struct iso_context) * ohci->n_ir;
3547         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3548
3549         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3550         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3551         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3552         ohci->it_context_mask = ohci->it_context_support;
3553         ohci->n_it = hweight32(ohci->it_context_mask);
3554         size = sizeof(struct iso_context) * ohci->n_it;
3555         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3556
3557         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3558                 err = -ENOMEM;
3559                 goto fail_contexts;
3560         }
3561
3562         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3563         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3564
3565         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3566         max_receive = (bus_options >> 12) & 0xf;
3567         link_speed = bus_options & 0x7;
3568         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3569                 reg_read(ohci, OHCI1394_GUIDLo);
3570
3571         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3572         if (err)
3573                 goto fail_contexts;
3574
3575         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3576         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3577                   "%d IR + %d IT contexts, quirks 0x%x\n",
3578                   dev_name(&dev->dev), version >> 16, version & 0xff,
3579                   ohci->n_ir, ohci->n_it, ohci->quirks);
3580
3581         return 0;
3582
3583  fail_contexts:
3584         kfree(ohci->ir_context_list);
3585         kfree(ohci->it_context_list);
3586         context_release(&ohci->at_response_ctx);
3587  fail_atreq_ctx:
3588         context_release(&ohci->at_request_ctx);
3589  fail_arrsp_ctx:
3590         ar_context_release(&ohci->ar_response_ctx);
3591  fail_arreq_ctx:
3592         ar_context_release(&ohci->ar_request_ctx);
3593  fail_misc_buf:
3594         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3595                           ohci->misc_buffer, ohci->misc_buffer_bus);
3596  fail_iounmap:
3597         pci_iounmap(dev, ohci->registers);
3598  fail_iomem:
3599         pci_release_region(dev, 0);
3600  fail_disable:
3601         pci_disable_device(dev);
3602  fail_free:
3603         kfree(ohci);
3604         pmac_ohci_off(dev);
3605  fail:
3606         if (err == -ENOMEM)
3607                 fw_error("Out of memory\n");
3608
3609         return err;
3610 }
3611
3612 static void pci_remove(struct pci_dev *dev)
3613 {
3614         struct fw_ohci *ohci;
3615
3616         ohci = pci_get_drvdata(dev);
3617         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3618         flush_writes(ohci);
3619         cancel_work_sync(&ohci->bus_reset_work);
3620         fw_core_remove_card(&ohci->card);
3621
3622         /*
3623          * FIXME: Fail all pending packets here, now that the upper
3624          * layers can't queue any more.
3625          */
3626
3627         software_reset(ohci);
3628         free_irq(dev->irq, ohci);
3629
3630         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3631                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3632                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3633         if (ohci->config_rom)
3634                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3635                                   ohci->config_rom, ohci->config_rom_bus);
3636         ar_context_release(&ohci->ar_request_ctx);
3637         ar_context_release(&ohci->ar_response_ctx);
3638         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3639                           ohci->misc_buffer, ohci->misc_buffer_bus);
3640         context_release(&ohci->at_request_ctx);
3641         context_release(&ohci->at_response_ctx);
3642         kfree(ohci->it_context_list);
3643         kfree(ohci->ir_context_list);
3644         pci_disable_msi(dev);
3645         pci_iounmap(dev, ohci->registers);
3646         pci_release_region(dev, 0);
3647         pci_disable_device(dev);
3648         kfree(ohci);
3649         pmac_ohci_off(dev);
3650
3651         fw_notify("Removed fw-ohci device.\n");
3652 }
3653
3654 #ifdef CONFIG_PM
3655 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3656 {
3657         struct fw_ohci *ohci = pci_get_drvdata(dev);
3658         int err;
3659
3660         software_reset(ohci);
3661         free_irq(dev->irq, ohci);
3662         pci_disable_msi(dev);
3663         err = pci_save_state(dev);
3664         if (err) {
3665                 fw_error("pci_save_state failed\n");
3666                 return err;
3667         }
3668         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3669         if (err)
3670                 fw_error("pci_set_power_state failed with %d\n", err);
3671         pmac_ohci_off(dev);
3672
3673         return 0;
3674 }
3675
3676 static int pci_resume(struct pci_dev *dev)
3677 {
3678         struct fw_ohci *ohci = pci_get_drvdata(dev);
3679         int err;
3680
3681         pmac_ohci_on(dev);
3682         pci_set_power_state(dev, PCI_D0);
3683         pci_restore_state(dev);
3684         err = pci_enable_device(dev);
3685         if (err) {
3686                 fw_error("pci_enable_device failed\n");
3687                 return err;
3688         }
3689
3690         /* Some systems don't setup GUID register on resume from ram  */
3691         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3692                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3693                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3694                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3695         }
3696
3697         err = ohci_enable(&ohci->card, NULL, 0);
3698         if (err)
3699                 return err;
3700
3701         ohci_resume_iso_dma(ohci);
3702
3703         return 0;
3704 }
3705 #endif
3706
3707 static const struct pci_device_id pci_table[] = {
3708         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3709         { }
3710 };
3711
3712 MODULE_DEVICE_TABLE(pci, pci_table);
3713
3714 static struct pci_driver fw_ohci_pci_driver = {
3715         .name           = ohci_driver_name,
3716         .id_table       = pci_table,
3717         .probe          = pci_probe,
3718         .remove         = pci_remove,
3719 #ifdef CONFIG_PM
3720         .resume         = pci_resume,
3721         .suspend        = pci_suspend,
3722 #endif
3723 };
3724
3725 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3726 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3727 MODULE_LICENSE("GPL");
3728
3729 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3730 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3731 MODULE_ALIAS("ohci1394");
3732 #endif
3733
3734 static int __init fw_ohci_init(void)
3735 {
3736         return pci_register_driver(&fw_ohci_pci_driver);
3737 }
3738
3739 static void __exit fw_ohci_cleanup(void)
3740 {
3741         pci_unregister_driver(&fw_ohci_pci_driver);
3742 }
3743
3744 module_init(fw_ohci_init);
3745 module_exit(fw_ohci_cleanup);