drivers/emgd/pal/sdvo/sdvo_intf.h

   1 /*
   2  *-----------------------------------------------------------------------------
   3  * Filename: sdvo_intf.h
   4  * $Revision: 1.10 $
   5  *-----------------------------------------------------------------------------
   6  * Copyright (c) 2002-2010, Intel Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  *-----------------------------------------------------------------------------
  27  * Description:
  28  *  Definitions for SDVO interface
  29  *-----------------------------------------------------------------------------
  30  */
  31
  32 #ifndef _SDVO_INTF_H_
  33 #define _SDVO_INTF_H_
  34
  35 /*  ......................................................................... */
  36 /*  Opcode, Status Code, Register definitions */
  37
  38 typedef enum {
  39     /*  General */
  40     RESET = 0x1,
  41     GET_DEVICE_CAPABILITIES,
  42     GET_TRAINED_INPUTS,
  43     GET_ACTIVE_OUTPUTS,
  44     SET_ACTIVE_OUTPUTS,
  45
  46     /*  Picture Routing  */
  47     GET_IN_OUT_MAP = 0x6,
  48     SET_IN_OUT_MAP,
  49
  50     GET_ATTACHED_DISPLAYS = 0x0B,
  51
  52     /* Hot Plug */
  53     GET_HOT_PLUG_SUPPORT = 0x0C,
  54     SET_ACTIVE_HOT_PLUG,
  55     GET_ACTIVE_HOT_PLUG,
  56     GET_INTERRUPT_EVENT_SOURCE,
  57
  58     /*  Input/Output Timings */
  59     SET_TARGET_INPUT = 0x10,
  60     SET_TARGET_OUTUT,
  61     GET_INPUT_TIMINGS_PART1,
  62     GET_INPUT_TIMINGS_PART2,
  63     SET_INPUT_TIMINGS_PART1,
  64     SET_INPUT_TIMINGS_PART2,
  65     SET_OUTPUT_TIMINGS_PART1,
  66     SET_OUTPUT_TIMINGS_PART2,
  67     GET_OUTPUT_TIMINGS_PART1,
  68     GET_OUTPUT_TIMINGS_PART2,
  69     CREATE_PREFERRED_INPUT_TIMINGS,
  70     GET_PREFERRED_INPUT_TIMINGS_PART1,
  71     GET_PREFERRED_INPUT_TIMINGS_PART2,
  72     GET_INPUT_PIXEL_CLOCK_RANGE,
  73     GET_OUTPUT_PIXEL_CLOCK_RANGE,
  74     GET_SUPPORTED_SDVO_CLOCK_RATE_MULTIPLIERS,
  75     GET_SDVO_CLOCK_RATE_MULTIPLIER,
  76     SET_SDVO_CLOCK_RATE_MULTIPLIER,
  77
  78     GET_SUPPORTED_TV_OUTPUT_FORMATS = 0x27,
  79     GET_TV_OUTPUT_FORMAT,
  80     SET_TV_OUTPUT_FORMAT,
  81
  82     /*  Power Management */
  83     GET_SUPPORTED_POWER_STATES = 0x2A,
  84     GET_POWER_STATE,
  85     SET_POWER_STATE,
  86
  87     /*  Panel Power Sequencing */
  88     GET_MAX_PANEL_POWER_SEQUENCING_PARAMETER = 0x2D,
  89     GET_PANEL_POWER_SEQUENCING_PARAMETER,
  90     SET_PANEL_POWER_SEQUENCING_PARAMETER,
  91
  92     GET_MAX_BACKLIGHT_LEVEL,
  93     GET_BACKLIGHT_LEVEL,
  94     SET_BACKLIGHT_LEVEL,
  95
  96     GET_AMBIENT_LIGHT,
  97     SET_AMBIENT_LIGHT,
  98
  99     SET_UPSCALAR_COEFFICIENTS = 0x36,
 100
 101     GET_SSC,
 102     SET_SSC,
 103
 104     /*  Content Protection */
 105     GET_ANCILLARY_VIDEO_INFORMATION,
 106     SET_ANCILLARY_VIDEO_INFORMATION,
 107
 108     /*  Picture Enhancements */
 109     GET_MAX_FLICKER_FILTER = 0x4D,
 110     GET_FLICKER_FILTER,
 111     SET_FLICKER_FILTER,
 112
 113     GET_ADAPTIVE_FLICKER_FILTER,
 114     SET_ADAPTIVE_FLICKER_FILTER,
 115
 116     GET_MAX_2D_FLICKER_FILTER,
 117     GET_2D_FLICKER_FILTER,
 118     SET_2D_FLICKER_FILTER,
 119
 120     GET_MAX_SATURATION,
 121     GET_SATURATION,
 122     SET_SATURATION,
 123
 124     GET_MAX_HUE,
 125     GET_HUE,
 126     SET_HUE,
 127
 128     GET_MAX_BRIGHTNESS,
 129     GET_BRIGHTNESS,
 130     SET_BRIGHTNESS,
 131
 132     GET_MAX_CONTRAST,
 133     GET_CONTRAST,
 134     SET_CONTRAST,
 135
 136     GET_MAX_HORIZONTAL_OVERSCAN,
 137     GET_HORIZONTAL_OVERSCAN,
 138     SET_HORIZONTAL_OVERSCAN,
 139
 140     GET_MAX_VERTICAL_OVERSCAN,
 141     GET_VERTICAL_OVERSCAN,
 142     SET_VERTICAL_OVERSCAN,
 143
 144     GET_MAX_HORIZONTAL_POSITION,
 145     GET_HORIZONTAL_POSITION,
 146     SET_HORIZONTAL_POSITION,
 147
 148     GET_MAX_VERTICAL_POSITION,
 149     GET_VERTICAL_POSITION,
 150     SET_VERTICAL_POSITION,
 151
 152     GET_MAX_SHARPNESS,
 153     GET_SHARPNESS,
 154     SET_SHARPNESS,
 155
 156     GET_DOT_CRAWL,
 157     SET_DOT_CRAWL,
 158
 159     GET_DITHER,
 160     SET_DITHER,
 161
 162     GET_MAX_TV_CHROMA_FILTER,
 163     GET_TV_CHROMA_FILTER,
 164     SET_TV_CHROMA_FILTER,
 165
 166     GET_MAX_TV_LUMA_FILTER,
 167     GET_TV_LUMA_FILTER,
 168     SET_TV_LUMA_FILTER,
 169
 170     /*  Control Bus Switch */
 171     SET_CONTROL_BUS_SWITCH = 0x7A,
 172
 173     /*  Picture Enhancements */
 174     GET_MAX_ADAPTIVE_FLICKER_FILTER = 0x7B,
 175
 176     /*  Power Management */
 177     SET_DISPLAY_POWER_STATE = 0x7D,
 178
 179     /*  Panel Power Sequencing */
 180     GET_MAX_SSC = 0x7E,
 181     GET_LVDS_PANEL_INFORMATION,
 182     SET_LVDS_PANEL_INFORMATION,
 183     GET_LVDS_PANEL_PROTECTION,
 184     SET_LVDS_PANEL_PROTECTION,
 185
 186         GET_SDTV_RESOLUTION_SUPPORT = 0x83,
 187         GET_SUPPORTED_ENHANCEMENTS,
 188         GET_SCALED_HDTV_RESOLUTION_SUPPORT,
 189
 190         /*  General */
 191         GET_FIRMWARE_VERSION = 0x86,
 192         DETECT_LEGACY_VGA = 0x87,
 193
 194         /* HDMI */
 195         PREPARE_TO_GENERATE_HDCPAN = 0x8A,
 196         SET_PIXEL_REPLICATION = 0x8B,
 197         GET_PIXEL_REPLICATION,
 198         GET_COLORIMETRY_CAPABILITIES,
 199         SET_CURRENT_COLORIMETRY,
 200         GET_CURRENT_COLORIMETRY,
 201         GET_AUDIO_ENCRYPTION_PREFERENCE,
 202         SET_AUDIO_STATE,
 203         GET_AUDIO_STATE,
 204         SET_HDMI_BUFFER_INDEX,
 205         GET_HDMI_BUFFER_INDEX,
 206         GET_HDMI_BUFFER_INFO,
 207         SET_HDMI_BUFFER_AUDIO_VIDEO_SPLIT,
 208         GET_HDMI_BUFFER_AUDIO_VIDEO_SPLIT,
 209         SET_HDMI_BUFFER_DATA,
 210         GET_HDMI_BUFFER_DATA,
 211         SET_HDMI_BUFFER_TRANSMIT_RATE,
 212         GET_HDMI_BUFFER_TRANSMIT_RATE,
 213         GET_HDMI_AUDIO_TRANSMISSION_CHARACTERISTICS,
 214         GET_SUPPORTED_DIGITAL_ENCODING_MODES, /* 0x9D, */
 215         GET_DIGITAL_ENCODING_MODE,
 216         SET_DIGITAL_ENCODING_MODE,
 217 } sdvo_opcode_t;
 218
 219 typedef enum {
 220     SS_POWER_ON_STATE,       /*  00: */
 221     SS_SUCCESS,              /*  01: Command successfully completed */
 222     SS_NOT_SUPPORTED,        /*  02: Invalid Opcode */
 223     SS_INVALID_ARGUMENT,     /*  03: Opcode is valid but arguments are not */
 224     SS_PENDING,              /*  04: Opcode is not completed yet */
 225     SS_TARGET_UNSPECIFIED,   /*  05: SetTargetInput/Output not called */
 226     SS_SCALING_UNSUPPORTED,  /*  06: Device does not support scaling */
 227
 228     /*  New Errors */
 229     SS_UNSUCCESSFUL = 10,    /*  10: General Failure */
 230     SS_INVALID_RETURN,       /*  11: Unexpected return value */
 231     SS_WRITE_FAILED,         /*  12: Write Operation failed */
 232     SS_READ_FAILED,          /*  13: Read Operation failed */
 233 } sdvo_status_t;
 234
 235 #define SDVO_MAX_ARGS           8
 236 #define SDVO_MAX_RETURNS        8
 237
 238 #define SDVO_REG_ARG_START      0x07
 239 #define SDVO_REG_ARG_END        0x00
 240 #define SDVO_REG_OPCODE         0x08
 241 #define SDVO_REG_STATUS         0x09
 242 #define SDVO_REG_RETURN_START   0x0A
 243 #define SDVO_REG_RETURN_END     0x11
 244
 245 #define SDVO_MAX_RETRIES        3
 246
 247 /*  ........................................................................ */
 248 /*  Structure definitions for Commands */
 249
 250 typedef unsigned char i2c_reg_t;
 251
 252 /* SDVOOutputFlagStructure Byte 0 */
 253 typedef struct {
 254     i2c_reg_t tmds  : 1;
 255     i2c_reg_t rgb   : 1;
 256     i2c_reg_t cvbs  : 1;
 257     i2c_reg_t svid  : 1;
 258     i2c_reg_t yprpb : 1;
 259     i2c_reg_t scart : 1;
 260     i2c_reg_t lvds  : 1;
 261     i2c_reg_t drgb  : 1;
 262 } sdvo_display_output_t;
 263
 264 /* Display masks */
 265 #define FP_DISP_MASK (BIT(0)|BIT(6)|BIT(7)|BIT(8)|BIT(14)) /*TMDS/LVDS/DRGB*/
 266 #define TV_DISP_MASK (BIT(2)|BIT(3)|BIT(4)|BIT(5)) /*CVBS0/SVID0/YPRPB0/SCART0*/
 267 #define CRT_EXT_DISP_MASK (BIT(1)|BIT(9))   /* External CRT */
 268 #define LVDS_DISP_MASK    (BIT(6)|BIT(14))  /* LVDS */
 269 #define TMDS_DISP_MASK (BIT(0)|BIT(8))
 270 #define TV_SVIDEO_DISP_MASK (BIT(3))   /* S-VIDEO */
 271 #define TV_YPBPR_DISP_MASK (BIT(4))    /* YPBPR/Yipper */
 272 #define DRGB_DISP_MASK  (BIT(7))       /* DRGB0 */
 273 typedef struct {
 274         union {
 275                 struct {
 276                         sdvo_display_output_t out0;
 277                         sdvo_display_output_t out1;
 278                 };
 279                 unsigned short flags;
 280         };
 281 } sdvo_output_flags_t;
 282
 283 typedef struct {
 284     i2c_reg_t vendor_id;         /* 00: Vendor ID */
 285     i2c_reg_t device_id;         /* 01: Device ID */
 286     i2c_reg_t revision_id;       /* 02: Revision ID */
 287     i2c_reg_t version_minor;     /*  03 : sDVO Minor Version (00) */
 288     i2c_reg_t version_major;     /*  04 : sDVO Major Version (01) */
 289                                  /*  05 : Device capabilities */
 290     i2c_reg_t num_inputs    :2;  /*  10 : Number of sDVO inputs (1 or 2) */
 291     i2c_reg_t smooth_scaling:1;  /*   2 : Smooth (Graphics) Scaling */
 292     i2c_reg_t sharp_scaling :1;  /*   3 : Sharp (Text) scaling */
 293     i2c_reg_t up_scaling    :1;  /*   4 : Up Scaling */
 294     i2c_reg_t down_scaling  :1;  /*   5 : Down Scaling */
 295     i2c_reg_t stall         :1;  /*   6 : Stall */
 296     i2c_reg_t reserved      :1;  /*   7 : Reserved */
 297     sdvo_output_flags_t output;  /* 06&07: Ouput supported by sDVO device */
 298 } sdvo_device_capabilities_t;
 299
 300 typedef struct {
 301     unsigned short pixel_clock;         /*  Pixel clock / 10,000 */
 302     unsigned short active_horz_pixels;  /*  12 bits of horizontal active */
 303     unsigned short active_vert_pixels;  /*  12 bits of vertical active */
 304     unsigned char  b_interlaced :1;     /*  1:Interlaced, 0: Non-Interlaced */
 305     unsigned char  b_scaled     :1;     /*  1:Image to be scaled, 0:Otherwise*/
 306     unsigned char  resv_bits    :6;     /*  Reserved bits */
 307     unsigned char  resv_byte;
 308 } sdvo_create_preferred_timings_t;
 309
 310 typedef enum {
 311     CRM_1X = BIT(0),
 312     CRM_2X = BIT(1),
 313     CRM_4X = BIT(3),
 314 } sdvo_clock_rate_mult_t;
 315
 316 /*  Detailed Timing Descriptor */
 317 typedef struct {
 318     unsigned short pixel_clock;      /*  Pixel Clock / 10,000 */
 319     unsigned short horz_active;      /*  Horizontal Active */
 320     unsigned short horz_blanking;    /*  Horizontal Blanking */
 321     unsigned short vert_active;      /*  Vertical Active */
 322     unsigned short vert_blanking;    /*  Vertical Blanking */
 323     unsigned short horz_sync_offset;  /*  Pixels from blanking start */
 324     unsigned short horz_sync_pulse_width;
 325     unsigned char  vert_sync_offset;
 326     unsigned char  vert_sync_pulse_width;
 327     unsigned char  dtd_flags;
 328     unsigned char  sdvo_flags;
 329 } sdvo_dtd_t;
 330
 331 typedef enum {
 332     SDVO0,
 333     SDVO1,
 334 } sdvo_target_input_t;
 335
 336 typedef struct {
 337     i2c_reg_t dev_D0 :1; /*  SDVO On */
 338     i2c_reg_t dev_D1 :1;
 339     i2c_reg_t dev_D2 :1;
 340     i2c_reg_t dev_D3 :1; /*  SDVO Off */
 341     i2c_reg_t disp_D0:1; /*  Display On      : Vsync/Hsync/Video Active */
 342     i2c_reg_t disp_D1:1; /*  Display Standby : Vsync Active, Hsync/Video Off */
 343     i2c_reg_t disp_D2:1; /*  Display Suspend : Hsync Active, Vsync/Video Off */
 344     i2c_reg_t disp_D3:1; /*  Display Off     : All signals Off */
 345 } sdvo_power_states_t;
 346
 347 typedef struct {
 348         struct{
 349                 i2c_reg_t minor_DVI_rev :4;
 350                 i2c_reg_t major_DVI_rev :4;
 351         };
 352         struct{
 353                 i2c_reg_t minor_HDMI_rev:4;
 354                 i2c_reg_t major_HDMI_rev:4;
 355         };
 356
 357     i2c_reg_t reserved[6];              /* reserved for future use */
 358 } sdvo_digital_encode_modes_t;
 359
 360 typedef struct{
 361         sdvo_digital_encode_modes_t     version;
 362 }sdvo_hdmi_context_t;
 363
 364
 365 typedef struct _sdvo_device_context {
 366     sdvo_target_input_t        inp_dev;
 367     sdvo_output_flags_t        out_type;
 368         sdvo_device_capabilities_t dev_cap;
 369     pd_callback_t             *p_callback;
 370         pd_attr_t                 *p_attr_table;
 371         unsigned long              num_attrs;
 372         pd_timing_t               *p_mode_table;
 373         pd_timing_t               *native_dtd;
 374         unsigned short             fp_width;
 375         unsigned short             fp_height;
 376         unsigned char              supp_pwr_states;
 377         unsigned char              device_pwr_state, display_pwr_state;
 378         unsigned char              up_scaling;
 379         unsigned short             t1;   /* power state delays */
 380         unsigned short             t2;   /* power state delays */
 381         unsigned short             t3;   /* power state delays */
 382         unsigned short             t4;
 383         unsigned short             t5;
 384         unsigned short             text_tune;
 385         sdvo_hdmi_context_t                hdmi;
 386         unsigned short             st_sdvo;
 387 } sdvo_device_context_t;
 388
 389 typedef struct sdvo_state {
 390         unsigned long power_state;
 391         pd_timing_t timing;
 392 } sdvo_state_t;
 393
 394 /*  ......................................................................... */
 395 sdvo_status_t sdvo_execute_command(sdvo_device_context_t *p_ctx,
 396         sdvo_opcode_t opcode,
 397         i2c_reg_t num_args, i2c_reg_t *p_arg,
 398         i2c_reg_t num_returns, i2c_reg_t *p_ret_value);
 399
 400 sdvo_status_t sdvo_reset(sdvo_device_context_t *p_ctx);
 401 sdvo_status_t sdvo_get_device_capabilities(sdvo_device_context_t *p_ctx,
 402         sdvo_device_capabilities_t *p_Dev_Cap);
 403 sdvo_status_t sdvo_get_trained_inputs(sdvo_device_context_t *p_ctx,
 404         i2c_reg_t *p_Out);
 405 sdvo_status_t sdvo_get_active_outputs(sdvo_device_context_t *p_ctx,
 406         sdvo_output_flags_t *p_Out_Flags);
 407 sdvo_status_t sdvo_set_active_outputs(sdvo_device_context_t *p_ctx,
 408         sdvo_output_flags_t out_flags);
 409
 410 sdvo_status_t sdvo_get_in_out_map(sdvo_device_context_t *p_ctx,
 411         sdvo_output_flags_t out_flags[2]);
 412 sdvo_status_t sdvo_set_in_out_map(sdvo_device_context_t *p_ctx,
 413         sdvo_output_flags_t out_flags[2]);
 414 sdvo_status_t sdvo_set_upscalar_coefficient(sdvo_device_context_t *p_ctx,
 415         i2c_reg_t upscalar_coefficient);
 416
 417 sdvo_status_t sdvo_get_attached_displays(sdvo_device_context_t *p_ctx,
 418         sdvo_output_flags_t *p_Out_Flags);
 419
 420 sdvo_status_t sdvo_set_target_input(sdvo_device_context_t *p_ctx,
 421         sdvo_target_input_t input);
 422 sdvo_status_t sdvo_set_target_output(sdvo_device_context_t *p_ctx,
 423         sdvo_output_flags_t out_flags);
 424
 425 sdvo_status_t sdvo_get_input_timings(sdvo_device_context_t *p_ctx,
 426         sdvo_dtd_t *p_dtd);
 427 sdvo_status_t sdvo_set_input_timings(sdvo_device_context_t *p_ctx,
 428         sdvo_dtd_t *p_dtd);
 429
 430 sdvo_status_t sdvo_get_output_timings(sdvo_device_context_t *p_ctx,
 431         sdvo_dtd_t *p_dtd);
 432 sdvo_status_t sdvo_set_output_timings(sdvo_device_context_t *p_ctx,
 433         sdvo_dtd_t *p_dtd);
 434
 435 sdvo_status_t sdvo_get_input_pixel_clock_range(sdvo_device_context_t *p_ctx,
 436         unsigned short p_Pixel[2]);
 437
 438 sdvo_status_t sdvo_get_preferred_input_timings(sdvo_device_context_t *p_ctx,
 439         sdvo_create_preferred_timings_t *p_Timings,
 440         sdvo_dtd_t *p_dtd);
 441 sdvo_status_t sdvo_get_clock_rate_multiplier(sdvo_device_context_t *p_ctx,
 442         sdvo_clock_rate_mult_t *p_mult);
 443 sdvo_status_t sdvo_set_clock_rate_multiplier(sdvo_device_context_t *p_ctx,
 444         sdvo_clock_rate_mult_t mult);
 445
 446 sdvo_status_t sdvo_get_supported_power_states(sdvo_device_context_t *p_ctx,
 447         i2c_reg_t *p_pwr_state);
 448 sdvo_status_t sdvo_get_power_state(sdvo_device_context_t *p_ctx,
 449         i2c_reg_t *p_Power_State);
 450 sdvo_status_t sdvo_set_power_state(sdvo_device_context_t *p_ctx,
 451         i2c_reg_t pwr_state);
 452 sdvo_status_t sdvo_set_display_power_state(sdvo_device_context_t *p_ctx,
 453         i2c_reg_t display_state);
 454 #if !defined(CONFIG_MICRO) /* These are not used in vBIOS */
 455 sdvo_status_t sdvo_set_digital_encoding_mode(sdvo_device_context_t *p_ctx,
 456         i2c_reg_t digital_encoding_mode);
 457 sdvo_status_t sdvo_get_hdmi_audio_transmission_char(
 458         sdvo_device_context_t *p_ctx, i2c_reg_t *hdmi_reg);
 459 sdvo_status_t sdvo_get_supported_encoding_modes(sdvo_device_context_t *p_ctx,
 460     sdvo_digital_encode_modes_t *digital_encoding_modes);
 461 sdvo_status_t sdvo_get_digital_encoding_mode(sdvo_device_context_t *p_ctx,
 462         i2c_reg_t *digital_encoding_mode);
 463 /* ------------------------------------------------------------------------- */
 464 #endif
 465 sdvo_status_t sdvo_get_min_max_pixel_clock(sdvo_device_context_t *p_ctx,
 466         unsigned long *p_min_clock, unsigned long *p_max_clock);
 467
 468 sdvo_status_t sdvo_get_tv_output_format(sdvo_device_context_t *p_ctx,
 469         i2c_reg_t *p_TV_Output_Format_Flag);
 470
 471 sdvo_status_t sdvo_get_sdtv_resolution_support(sdvo_device_context_t *p_ctx,
 472         i2c_reg_t *p_Requested_SDTV_Format_Flag, i2c_reg_t *p_Resolution_Support_Flags);
 473
 474 sdvo_status_t sdvo_get_scaled_hdtv_resolution_support(
 475         sdvo_device_context_t *p_ctx, i2c_reg_t *p_Requested_HDTV_Format_Flag,
 476         i2c_reg_t *p_Resolution_Support_Flags);
 477
 478 sdvo_status_t sdvo_execute_command_read(sdvo_device_context_t *p_ctx,
 479         i2c_reg_t num_returns, i2c_reg_t *p_ret_value);
 480
 481 #endif  /*  _SDVO_INTF_H_ */
 482