2 *-----------------------------------------------------------------------------
5 *-----------------------------------------------------------------------------
6 * Copyright (c) 2002-2010, Intel Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
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12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
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19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 *-----------------------------------------------------------------------------
29 *-----------------------------------------------------------------------------
32 #define MODULE_NAME hal.dpd
47 #include "../cmn/i2c_dispatch.h"
50 * @addtogroup display_group
54 /*......................................................................... */
55 extern igd_display_port_t dvob_port_plb;
57 /*......................................................................... */
58 static int i2c_read_regs_plb(
59 igd_context_t *context,
60 unsigned long i2c_bus,
61 unsigned long i2c_speed,
64 unsigned char FAR *buffer,
65 unsigned long num_bytes,
68 static int i2c_write_reg_list_plb(
69 igd_context_t *context,
70 unsigned long i2c_bus,
71 unsigned long i2c_speed,
76 i2c_dispatch_t i2c_dispatch_plb = {
78 i2c_write_reg_list_plb,
82 /*.......................................................................... */
85 GMBUS_SPEED_50K = 0x0100,
86 GMBUS_SPEED_100K = 0x0000,
87 GMBUS_SPEED_400K = 0x0200,
88 GMBUS_SPEED_1000K = 0x0300,
109 GMBUS_PINS_DEDICATED = 1, /* Dedicated Control/GMBUS Pins */
110 /* LCTRCLKA, LCTRLCLKB SSC Clock Device */
111 GMBUS_PINS_ANALOG = 2, /* Analog DDC */
112 GMBUS_PINS_INT_LVDS = 3, /* Alviso : Integrated Digital Panel */
113 GMBUS_PINS_SDVO = 5, /* SDVO Registers, DDC, PROM */
125 /*.......................................................................... */
128 SDVO_BUS_PROM = BIT(0),
129 SDVO_BUS_DDC1 = BIT(1),
130 SDVO_BUS_DDC2 = BIT(2),
134 #define SDVO_OPCODE_BUS_SWITCH 0x7A
136 #define SDVO_INDEX_PARAM_1 0x07
137 #define SDVO_INDEX_OPCODE 0x08
138 #define SDVO_INDEX_STATUS 0x09
140 #define SDVO_STATUS_SUCCESS 0x01
141 #define SDVO_STATUS_PENDING 0x04
143 /*.......................................................................... */
145 * In 16-bit, the mmio is a 16-bit pointer, the watcom 1.2 compiler will have
146 * error if directly convert it to unsigned long. Normally, have to cast it to
147 * unsigned short first then cast again to unsigned long; then, it will be
148 * correct. But this type of casting may cause some error in the 32 and 64 bit
149 * code. Since mmio will be equal to zero for 16-bit code. Add the checking
150 * for MICRO definition code to correct the macro by remove mmio.
152 #define READ_GMCH_REG(reg) EMGD_READ32(EMGD_MMIO(mmio) + reg)
153 #define WRITE_GMCH_REG(reg, data) EMGD_WRITE32(data, EMGD_MMIO(mmio) + reg)
155 static int gmbus_init(unsigned char *mmio, unsigned long i2c_bus,
156 unsigned long i2c_speed);
158 static int gmbus_read_edid(unsigned char *mmio,
159 unsigned long ddc_addr,
160 unsigned long slave_addr,
162 unsigned long num_bytes,
163 unsigned char FAR *buffer);
165 static int gmbus_read_reg(unsigned char *mmio,
166 unsigned long slave_addr,
168 unsigned char FAR *data);
170 static int gmbus_write_reg(unsigned char *mmio,
171 unsigned long slave_addr,
175 static int gmbus_set_control_bus_switch(unsigned char *mmio,
176 unsigned long slave_addr,
177 gmbus_ddc_addr_t ddc_addr);
179 static int gmbus_wait_event_one(unsigned char *mmio, unsigned long bit);
180 static int gmbus_wait_event_zero(unsigned char *mmio, unsigned long bit);
181 static int gmbus_error_handler(unsigned char *mmio);
184 * i2c_read_regs_plb is called to read Edid or a single sDVO register
187 * @param i2c_bus port->ddc_reg, port->i2c_reg
188 * @param i2c_speed 50, 100, 400, 1000 (Khz)
189 * @param dab 0x70/0x72 (sDVO Regs), 0xA0/0xA2 (sDVO/Analog DDC)
190 * @param reg I2C Reg Index
191 * @param num_bytes <= 508
192 * @param buffer Data read
193 * @param flags unused, put in to match TNC func signature
195 * @return 0 on success
196 * @return 1 on failure
198 static int i2c_read_regs_plb(igd_context_t *context,
199 unsigned long i2c_bus,
200 unsigned long i2c_speed,
203 unsigned char FAR *buffer,
204 unsigned long num_bytes,
207 unsigned char *mmio = EMGD_MMIO(context->device_context.virt_mmadr);
208 unsigned long slave_addr;
210 if (! gmbus_init(mmio, i2c_bus, i2c_speed)) {
211 EMGD_DEBUG("Error ! i2c_read_regs_plb : gmbus_init() failed");
215 /* If the request is to read Edid from sDVO display, find out the */
216 /* i2c addres of the sDVO device */
217 if (i2c_bus == GMBUS_DVOB_DDC) {
218 slave_addr = dvob_port_plb.dab;
226 case GMBUS_ANALOG_DDC :
227 case GMBUS_INT_LVDS_DDC :
228 case GMBUS_DVOB_DDC :
229 case GMBUS_DVOC_DDC :
230 if (! gmbus_read_edid(mmio, dab, slave_addr, reg, num_bytes, buffer)) {
232 EMGD_DEBUG("Error ! i2c_read_regs_plb : gmbus_read_edid() failed");
238 if (! gmbus_read_reg(mmio, dab, reg, buffer)) {
240 EMGD_DEBUG("Error ! i2c_read_regs_plb : gmbus_read_reg() failed");
246 EMGD_ERROR("Error ! i2c_read_regs_plb : Invalid i2c_bus=0x%lx",
255 * i2c_write_reg_list_plb is called to write a list of i2c registers to sDVO
259 * @param i2c_bus NAP_GMBUS_DVOB_DDC/NAP_GMBUS_DVOC_DDC
260 * @param i2c_speed 1000 Khz
261 * @param dab 0x70/0x72
262 * @param reg_list List of i2c indexes and data, terminated with register index
263 * set to PD_REG_LIST_END
265 * @return 0 on success
266 * @return 1 on failure
268 static int i2c_write_reg_list_plb(igd_context_t *context,
269 unsigned long i2c_bus,
270 unsigned long i2c_speed,
275 unsigned char *mmio = EMGD_MMIO(context->device_context.virt_mmadr);
276 unsigned long reg_num = 0, ddc_addr = 0, slave_addr = 0;
278 if (! gmbus_init(mmio, i2c_bus, i2c_speed)) {
280 EMGD_DEBUG("Error ! i2c_write_reg_list_plb : gmbus_init() failed");
283 /*If it is SDVO Make sure we issue SDVO command to enable DDC access*/
284 if ((i2c_bus == GMBUS_DVOB_DDC) || (i2c_bus == GMBUS_DVOC_DDC)) {
285 if (i2c_bus == GMBUS_DVOB_DDC) {
286 slave_addr = dvob_port_plb.dab;
287 }else if (i2c_bus == GMBUS_DVOC_DDC) {
288 /* Is DVOC available in PLB? */
289 //slave_addr = dvoc_port_plb.dab;
293 if (! gmbus_set_control_bus_switch(mmio, slave_addr, ddc_addr)) {
294 EMGD_DEBUG("Error ! i2c_write_reg_list_plb : gmbus_set_control_bus_switch()"
298 while (reg_list[reg_num].reg != PD_REG_LIST_END) {
300 if (! gmbus_write_reg(mmio, dab, reg_list[reg_num].reg,
301 (unsigned char)reg_list[reg_num].value)) {
303 EMGD_DEBUG("Error ! i2c_write_reg_list_plb : gmbus_write_reg() failed, reg_num=%lu",
310 /*...................................................................... */
311 /* Issue a Stop Command */
312 gmbus_wait_event_one(mmio, HW_WAIT);
313 WRITE_GMCH_REG(GMBUS1, STO | SW_RDY | ddc_addr);
314 gmbus_wait_event_one(mmio, HW_RDY);
315 gmbus_wait_event_zero(mmio, GA);
316 gmbus_error_handler(mmio);
317 WRITE_GMCH_REG(GMBUS1, SW_RDY);
318 WRITE_GMCH_REG(GMBUS1, SW_CLR_INT);
319 WRITE_GMCH_REG(GMBUS1, 0);
320 WRITE_GMCH_REG(GMBUS5, 0);
321 WRITE_GMCH_REG(GMBUS0, 0);
322 /*...................................................................... */
325 while (reg_list[reg_num].reg != PD_REG_LIST_END) {
327 if (! gmbus_write_reg(mmio, dab, reg_list[reg_num].reg,
328 (unsigned char)reg_list[reg_num].value)) {
330 EMGD_DEBUG("Error ! i2c_write_reg_list_plb : gmbus_write_reg() failed, reg_num=%lu",
343 * gmbus_init initializes the GMBUS controller with specified bus and speed
346 * @param i2c_bus sDVO B/C Reg/DDC or Analog DDC
347 * @param i2c_speed 50/100/400/1000 Khz
349 * @return TRUE(1) on success
350 * @return FALSE(0) on failure
352 static int gmbus_init(unsigned char *mmio, unsigned long i2c_bus,
353 unsigned long i2c_speed)
355 gmbus_pins_pair_t pin_pair;
356 gmbus_speed_t bus_speed;
361 case GMBUS_DVOB_DDC :
362 case GMBUS_DVOC_DDC :
363 pin_pair = GMBUS_PINS_SDVO;
366 case GMBUS_ANALOG_DDC :
367 pin_pair = GMBUS_PINS_ANALOG;
370 case GMBUS_INT_LVDS_DDC :
371 pin_pair = GMBUS_PINS_INT_LVDS;
375 EMGD_ERROR("Error ! gmbus_init : Invalid i2c_bus=0x%lx", i2c_bus);
381 case 50 : /* Slow speed */
382 bus_speed = GMBUS_SPEED_50K;
386 bus_speed = GMBUS_SPEED_400K;
389 case 1000 : /* sDVO Registers */
390 bus_speed = GMBUS_SPEED_1000K;
395 bus_speed = GMBUS_SPEED_100K;
399 WRITE_GMCH_REG(GMBUS5, 0); /* Clear the word index reg */
400 WRITE_GMCH_REG(GMBUS0, pin_pair | bus_speed);
406 * gmbus_wait_event_zero waits for specified GMBUS2 register bit to be deasserted
411 * @return TRUE(1) on success. The bit was deasserted in the specified timeout period
412 * @return FALSE(0) on failure
414 static int gmbus_wait_event_zero(unsigned char *mmio, unsigned long bit)
417 unsigned long status;
419 for (i = 0; i < 0x1000; i++) {
421 status = READ_GMCH_REG(GMBUS2);
423 if ((status & bit) == 0) {
429 EMGD_DEBUG("Error ! gmbus_wait_event_zero : Failed : bit=0x%lx, status=0x%lx, forcing reset",
432 /* If we are here, that means that the GBMUS is busy or in a bad
433 * state, the situation was observed
434 * that the GMBUS never becomes available (idle state) after S3.
435 * This results in the driver never being able to set the display.
437 * To fix this, we force force a reset of the GMBUS.
439 WRITE_GMCH_REG(GMBUS1, SW_RDY);
440 WRITE_GMCH_REG(GMBUS1, SW_CLR_INT);
441 WRITE_GMCH_REG(GMBUS1, 0);
447 * gmbus_wait_event_one wait for specified GMBUS2 register bits to be asserted
452 * @return TRUE(1) on success. The bit was asserted in the specified timeout period
453 * @return FALSE(0) on failure
455 static int gmbus_wait_event_one(unsigned char *mmio, unsigned long bit)
458 unsigned long status;
460 for (i = 0; i < 0x10000; i++) {
462 status = READ_GMCH_REG(GMBUS2);
463 if ((status & bit) != 0) {
469 EMGD_DEBUG("Error ! gmbus_wait_event_one : Failed : bit=0x%lx, status=0x%lx",
476 * gmbus_error_handler attempts to recover from timeout error
480 * @return TRUE(1) error was detected and handled
481 * @return FALSE(0) there was no error
483 static int gmbus_error_handler(unsigned char *mmio)
485 unsigned long status = READ_GMCH_REG(GMBUS2);
487 /* Clear the SW_INT, wait for HWRDY and GMBus active (GA) */
488 if ((status & HW_BUS_ERR) || (status & HW_TMOUT)) {
490 EMGD_DEBUG("Error ! gmbus_error_handler : Resolving error=0x%lx",
493 WRITE_GMCH_REG(GMBUS1, SW_RDY);
494 WRITE_GMCH_REG(GMBUS1, SW_CLR_INT);
495 WRITE_GMCH_REG(GMBUS1, 0);
497 gmbus_wait_event_zero(mmio, GA);
499 return 1; /* Handled the error */
502 return 0; /* There was no error */
506 * Assemble 32 bit GMBUS1 command
508 * @param slave_addr 0x70/0x72
509 * @param index 0 - 256
510 * @param num_bytes Bytes to transfer
511 * @param flags Bits 25-31 of GMBUS1
512 * @param i2c_dir I2C_READ / I2C_WRITE
514 * @return The assembled command
516 static unsigned long gmbus_assemble_command(unsigned long slave_addr, unsigned long index,
517 unsigned long num_bytes, unsigned long flags,
518 i2c_bus_dir_t i2c_dir)
520 unsigned long cmd = flags | ENIDX | ENT | (num_bytes << 16) | (index << 8) |
521 slave_addr | i2c_dir;
527 * gmbus_send_pkt transmits a block a data to specified i2c slave device
530 * @param slave_addr I2C device address
531 * @param index Starting i2c register index
532 * @param pkt_size 1 - 508 bytes
533 * @param pkt Bytes to send
535 * @return TRUE(1) if successful in sending the specified number of bytes
536 * @return FALSE(0) on failure
538 static int gmbus_send_pkt(unsigned char *mmio,
539 unsigned long slave_addr, unsigned long index,
540 unsigned long pkt_size, void *pkt)
542 unsigned long gmbus1_cmd;
543 unsigned long bytes_sent;
546 if ((pkt_size == 0) || (pkt == NULL) || (pkt_size > 508)) {
551 data = (unsigned long *)pkt;
553 /*...................................................................... */
554 gmbus_error_handler(mmio);
556 gmbus1_cmd = gmbus_assemble_command(slave_addr, index, pkt_size,
560 gmbus1_cmd |= SW_RDY;
563 /*...................................................................... */
568 WRITE_GMCH_REG(GMBUS3, *data);
570 if (bytes_sent == 0) {
572 WRITE_GMCH_REG(GMBUS1, gmbus1_cmd);
575 if (! gmbus_wait_event_one(mmio, HW_RDY)) {
577 EMGD_DEBUG("Error ! gmbus_send_pkt : Failed to get HW_RDY, bytes_sent=%ld",
583 if (gmbus_error_handler(mmio)) {
585 EMGD_DEBUG("Error ! gmbus_send_pkt : gmbus error, bytes_sent=%ld",
597 bytes_sent += pkt_size;
600 } while (bytes_sent < pkt_size);
602 /*...................................................................... */
603 if (bytes_sent != pkt_size) {
614 * gmbus_recv_pkt reads a block of data from specified i2c slave device
617 * @param slave_addr I2C device address
618 * @param index Starting i2c register index
619 * @param pkt_size 1 - 508 bytes
620 * @param pkt Bytes to send
622 * @return TRUE(1) if successful in receiving specified number of bytes
623 * @return FALSE(0) on failure
625 static int gmbus_recv_pkt(unsigned char *mmio,
626 unsigned long slave_addr, unsigned long index,
627 unsigned long pkt_size, void FAR *pkt)
629 unsigned long gmbus1_cmd;
630 unsigned long bytes_rcvd;
631 unsigned long FAR *data;
633 if ((pkt_size == 0) || (pkt == NULL) || (pkt_size > 508)) {
638 data = (unsigned long FAR *)pkt;
640 /*...................................................................... */
641 gmbus_error_handler(mmio);
643 /* Program the command */
644 gmbus1_cmd = gmbus_assemble_command(slave_addr, index, pkt_size,
645 STA | SW_RDY, I2C_READ);
646 WRITE_GMCH_REG(GMBUS1, gmbus1_cmd);
648 /*...................................................................... */
652 unsigned long gmbus3_data;
653 unsigned long bytes_left = pkt_size - bytes_rcvd;
655 if (! gmbus_wait_event_one(mmio, HW_RDY)) {
657 EMGD_DEBUG("Error ! gmbus_recv_pkt : Failed to get HW_RDY, "
658 "bytes_rcvd=%ld", bytes_rcvd);
662 if (gmbus_error_handler(mmio)) {
664 EMGD_DEBUG("Error ! gmbus_recv_pkt : gmbus error, bytes_rcvd=%ld",
669 gmbus3_data = READ_GMCH_REG(GMBUS3);
671 switch (bytes_left) {
674 *(unsigned char *)data = (unsigned char)gmbus3_data;
678 *(unsigned short *)data = (unsigned short)gmbus3_data;
683 unsigned char *dest = (unsigned char *)data;
684 unsigned char *src = (unsigned char *)&(gmbus3_data);
697 if (bytes_left > 4) {
702 bytes_rcvd += bytes_left;
706 } while (bytes_rcvd < pkt_size);
708 /*...................................................................... */
709 if (bytes_rcvd < pkt_size) {
718 * gmbus_set_control_bus_switch sends sDVO command to switch i2c bus to read EDID
722 * @param slave_addr sDVO device address (0x70/0x72)
723 * @param ddc_addr DDC1_ADDR/DDC2_ADDR
725 * @return TRUE(1) if successful in sending the opcode
726 * @return FALSE(0) on failure
728 static int gmbus_set_control_bus_switch(unsigned char *mmio,
729 unsigned long slave_addr,
730 gmbus_ddc_addr_t ddc_addr)
733 sdvo_bus_switch_t bus_switch;
736 bus_switch = SDVO_BUS_DDC1;
738 /*...................................................................... */
739 /* Transmit the Arguments */
740 if (! gmbus_send_pkt(mmio, slave_addr, SDVO_INDEX_PARAM_1, 1, &bus_switch)) {
742 EMGD_DEBUG("Error ! gmbus_set_control_bus_switch : gmbus_send_pkt() failed");
747 /*...................................................................... */
748 /* Generate I2C stop cycle */
749 gmbus_wait_event_one(mmio, HW_WAIT);
750 WRITE_GMCH_REG(GMBUS1, STO | SW_RDY | slave_addr);
751 gmbus_wait_event_one(mmio, HW_RDY);
752 gmbus_wait_event_zero(mmio, GA);
754 /*...................................................................... */
755 /* Transmit the Opcode */
756 data = SDVO_OPCODE_BUS_SWITCH;
757 if (! gmbus_send_pkt(mmio, slave_addr, SDVO_INDEX_OPCODE, 1, &data)) {
759 EMGD_DEBUG("Error ! gmbus_set_control_bus_switch : gmbus_send_pkt(Opcode)"
765 /*...................................................................... */
767 for (retry = 0; retry < 3; retry++) {
768 if (! gmbus_recv_pkt(mmio, slave_addr, SDVO_INDEX_STATUS, 1, &data)) {
773 if (data != SDVO_STATUS_PENDING) {
779 /*...................................................................... */
781 gmbus_wait_event_one(mmio, HW_WAIT);
782 WRITE_GMCH_REG(GMBUS1, STO | SW_RDY | slave_addr);
783 gmbus_wait_event_one(mmio, HW_RDY);
784 gmbus_wait_event_zero(mmio, GA);
786 /*...................................................................... */
787 if (data != SDVO_STATUS_SUCCESS) {
789 EMGD_DEBUG("Error ! gmbus_set_control_bus_switch : Opcode Bus Switch failed");
798 * gmbus_read_edid reads specified number of Edid data bytes
801 * @param ddc_addr 0xA0/0xA2 (DDC1/DDC2)
802 * @param slave_addr 0x70/0x72 (sDVOB, sDVOC), 0 Analog
803 * @param index i2c register index
804 * @param num_bytes <= 508
805 * @param buffer Edid data read from the display
807 * @return TRUE(1) if successful in reading Edid
808 * @return FALSE(0) on failure
810 static int gmbus_read_edid(unsigned char *mmio,
811 unsigned long ddc_addr,
812 unsigned long slave_addr,
814 unsigned long num_bytes,
815 unsigned char FAR *buffer)
819 if ((slave_addr == SDVOB_ADDR) || (slave_addr == SDVOC_ADDR)) {
821 if (! gmbus_set_control_bus_switch(mmio, slave_addr, ddc_addr)) {
823 EMGD_DEBUG("Error ! gmbus_read_edid : gmbus_set_control_bus_switch()"
830 gmbus_recv_pkt(mmio, ddc_addr, 0, 1, buffer);
833 status = gmbus_recv_pkt(mmio, ddc_addr, index, num_bytes, buffer);
836 EMGD_DEBUG("Error ! gmbus_read_edid : gmbus_recv_pkt() failed");
839 /*...................................................................... */
840 /* Issue a Stop Command */
842 gmbus_wait_event_one(mmio, HW_WAIT);
843 WRITE_GMCH_REG(GMBUS1, STO | SW_RDY | ddc_addr);
844 gmbus_wait_event_one(mmio, HW_RDY);
846 gmbus_wait_event_zero(mmio, GA);
848 gmbus_error_handler(mmio);
849 WRITE_GMCH_REG(GMBUS1, SW_RDY);
850 WRITE_GMCH_REG(GMBUS1, SW_CLR_INT);
851 WRITE_GMCH_REG(GMBUS1, 0);
852 WRITE_GMCH_REG(GMBUS5, 0);
853 WRITE_GMCH_REG(GMBUS0, 0);
855 /*...................................................................... */
860 * gmbus_read_reg reads one i2c register
863 * @param slave_addr 0x70/0x72 (sDVOB, sDVOC)
864 * @param index i2c register index
865 * @param data register data
867 * @return TRUE(1) if successful in reading the i2c register
868 * @return FALSE(0) on failure
870 static int gmbus_read_reg(unsigned char *mmio,
871 unsigned long slave_addr,
873 unsigned char FAR *data)
875 unsigned long gmbus1_cmd;
877 WRITE_GMCH_REG(GMBUS5, 0x0); /* Clear Word Index register */
879 if (! gmbus_wait_event_zero(mmio, GA)) {
881 EMGD_DEBUG("Error ! gmbus_read_reg : Failed to get GA(1)");
886 gmbus1_cmd = gmbus_assemble_command(slave_addr, index, 1,
887 STO | STA, I2C_READ);
888 WRITE_GMCH_REG(GMBUS1, gmbus1_cmd);
890 if (! gmbus_wait_event_zero(mmio, GA)) {
892 EMGD_DEBUG("Error ! gmbus_read_reg : Failed to get GA(2)");
897 *data = (unsigned char)READ_GMCH_REG(GMBUS3);
903 * gmbus_write_reg writes one i2c register
906 * @param slave_addr 0x70/0x72 (sDVOB, sDVOC)
907 * @param index i2c register index
908 * @param data register data
910 * @return TRUE(1) if successful in updating the i2c register
911 * @return FALSE(0) if failed to update the register
913 static int gmbus_write_reg(unsigned char *mmio,
914 unsigned long slave_addr,
918 unsigned long gmbus1_cmd;
920 WRITE_GMCH_REG(GMBUS5, 0x0); /* Clear Word Index register */
922 if (! gmbus_wait_event_zero(mmio, GA)) {
924 EMGD_DEBUG("Error ! gmbus_write_reg : Failed to get GA(1)");
929 WRITE_GMCH_REG(GMBUS3, data);
931 gmbus1_cmd = gmbus_assemble_command(slave_addr, index, 1,
932 STO | STA, I2C_WRITE);
933 WRITE_GMCH_REG(GMBUS1, gmbus1_cmd);
935 if (! gmbus_wait_event_zero(mmio, GA)) {
937 EMGD_DEBUG("Error ! gmbus_write_reg : Failed to get GA(2)");