drivers/emgd/display/dsp/plb/dsp_plb.c

   1 /*
   2  *-----------------------------------------------------------------------------
   3  * Filename: dsp_plb.c
   4  * $Revision: 1.8 $
   5  *-----------------------------------------------------------------------------
   6  * Copyright (c) 2002-2010, Intel Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  *-----------------------------------------------------------------------------
  27  * Description:
  28  *
  29  *-----------------------------------------------------------------------------
  30  */
  31
  32
  33 #include <io.h>
  34 #include <memory.h>
  35
  36 #include <igd.h>
  37 #include <igd_mode.h>
  38 #include <igd_pwr.h>
  39
  40 #include <mode.h>
  41 #include <utils.h>
  42
  43 #include <plb/regs.h>
  44 #include <plb/context.h>
  45
  46 #include "../cmn/dsp_dispatch.h"
  47
  48 #ifdef CONFIG_PLB
  49
  50 extern igd_framebuffer_info_t fb_info_cmn[];
  51
  52 /*
  53  * NOTE: Some of these format lists are shared with GMM. For this reason
  54  * they cannot be static.
  55  */
  56 unsigned long fb_pixel_formats_plb[] = {
  57         IGD_PF_ARGB32,
  58         IGD_PF_xRGB32,
  59         IGD_PF_ABGR32,
  60         IGD_PF_ARGB32_2101010,
  61         IGD_PF_RGB16_565,
  62         IGD_PF_ARGB8_INDEXED,
  63         0
  64 };
  65
  66 unsigned long vga_pixel_formats_plb[] = {
  67         IGD_PF_ARGB8_INDEXED,
  68         0
  69 };
  70
  71 #ifndef CONFIG_MICRO
  72 unsigned long sprite_pixel_formats_plb[] = {
  73         IGD_PF_ARGB32,
  74         IGD_PF_ABGR32,
  75         IGD_PF_ARGB32_2101010,
  76         IGD_PF_RGB16_565,
  77         IGD_PF_ARGB8_INDEXED,
  78         IGD_PF_YUV422_PACKED_YUY2,
  79         IGD_PF_YUV422_PACKED_UYVY,
  80         0
  81 };
  82
  83 unsigned long render_pixel_formats_plb[] = {
  84         IGD_PF_ARGB32,
  85         IGD_PF_xRGB32,
  86         IGD_PF_ARGB32_2101010,
  87         IGD_PF_RGB16_565,
  88         IGD_PF_xRGB16_555,
  89         IGD_PF_ARGB16_1555,
  90         IGD_PF_ARGB16_4444,
  91         IGD_PF_YUV422_PACKED_YUY2,
  92         IGD_PF_YUV422_PACKED_UYVY,
  93         IGD_PF_R16F,
  94         IGD_PF_GR32_1616F,
  95         IGD_PF_R32F,
  96         IGD_PF_ABGR64_16161616F,
  97         IGD_PF_YUV420_PLANAR_NV12,
  98         IGD_PF_YUV410_PLANAR_YVU9,
  99         0
 100 };
 101
 102 unsigned long texture_pixel_formats_plb[] = {
 103         IGD_PF_ARGB32,
 104         IGD_PF_xRGB32,
 105         IGD_PF_ABGR32,
 106         IGD_PF_xBGR32,
 107         IGD_PF_RGB16_565,
 108         IGD_PF_xRGB16_555,
 109         IGD_PF_ARGB16_1555,
 110         IGD_PF_ARGB16_4444,
 111         IGD_PF_ARGB8_INDEXED,
 112         IGD_PF_YUV422_PACKED_YUY2,
 113         IGD_PF_YUV422_PACKED_UYVY,
 114         IGD_PF_YUV420_PLANAR_I420,
 115         IGD_PF_YUV420_PLANAR_IYUV,
 116         IGD_PF_YUV420_PLANAR_YV12,
 117         IGD_PF_YUV410_PLANAR_YVU9,
 118         IGD_PF_YUV420_PLANAR_NV12,
 119         IGD_PF_DVDU_88,
 120         IGD_PF_LDVDU_655,
 121         IGD_PF_xLDVDU_8888,
 122         IGD_PF_DXT1,
 123         IGD_PF_DXT2,
 124         IGD_PF_DXT3,
 125         IGD_PF_DXT4,
 126         IGD_PF_DXT5,
 127         IGD_PF_L8,
 128         IGD_PF_A8,
 129         IGD_PF_AL88,
 130         IGD_PF_AI44,
 131         IGD_PF_L16,
 132         IGD_PF_ARGB32_2101010,
 133         IGD_PF_AWVU32_2101010,
 134         IGD_PF_QWVU32_8888,
 135         IGD_PF_GR32_1616,
 136         IGD_PF_VU32_1616,
 137         IGD_PF_R16F,
 138         IGD_PF_GR32_1616F,
 139         IGD_PF_R32F,
 140         IGD_PF_ABGR64_16161616F,
 141         0
 142 };
 143
 144 unsigned long depth_pixel_formats_plb[] = {
 145         IGD_PF_Z16,
 146         IGD_PF_Z24,
 147         IGD_PF_S8Z24,
 148         0
 149 };
 150
 151
 152 unsigned long cursor_pixel_formats_plb[] = {
 153         IGD_PF_ARGB32,
 154         IGD_PF_RGB_2,
 155         IGD_PF_RGB_XOR_2,
 156         IGD_PF_RGB_T_2,
 157         0
 158 };
 159
 160 unsigned long overlay_pixel_formats_plb[] = {
 161         IGD_PF_YUV422_PACKED_YUY2,
 162         IGD_PF_YUV422_PACKED_UYVY,
 163         IGD_PF_YUV420_PLANAR_I420,
 164         IGD_PF_YUV420_PLANAR_IYUV,
 165         IGD_PF_YUV420_PLANAR_YV12,
 166         IGD_PF_YUV420_PLANAR_NV12,
 167         IGD_PF_YUV410_PLANAR_YVU9,
 168         0
 169 };
 170
 171 unsigned long video_pixel_formats_plb[] = {
 172         IGD_PF_YUV420_PLANAR_NV12,
 173         0
 174 };
 175
 176 unsigned long blt_pixel_formats_plb[] = {
 177         IGD_PF_ARGB32,
 178         IGD_PF_xRGB32,
 179         IGD_PF_ABGR32,
 180         IGD_PF_xBGR32,
 181         IGD_PF_RGB16_565,
 182         IGD_PF_xRGB16_555,
 183         IGD_PF_ARGB16_1555,
 184         IGD_PF_ARGB16_4444,
 185         IGD_PF_ARGB8_INDEXED,
 186         IGD_PF_YUV422_PACKED_YUY2,
 187         IGD_PF_YUV422_PACKED_UYVY,
 188         IGD_PF_YUV420_PLANAR_I420,
 189         IGD_PF_YUV420_PLANAR_IYUV,
 190         IGD_PF_YUV420_PLANAR_YV12,
 191         IGD_PF_YUV420_PLANAR_NV12,
 192         IGD_PF_YUV410_PLANAR_YVU9,
 193         IGD_PF_DVDU_88,
 194         IGD_PF_LDVDU_655,
 195         IGD_PF_xLDVDU_8888,
 196         IGD_PF_DXT1,
 197         IGD_PF_DXT2,
 198         IGD_PF_DXT3,
 199         IGD_PF_DXT4,
 200         IGD_PF_DXT5,
 201         IGD_PF_Z16,
 202         IGD_PF_Z24,
 203         IGD_PF_S8Z24,
 204         IGD_PF_RGB_2,
 205         IGD_PF_RGB_XOR_2,
 206         IGD_PF_RGB_T_2,
 207         IGD_PF_L8,
 208         IGD_PF_A8,
 209         IGD_PF_AL88,
 210         IGD_PF_AI44,
 211         IGD_PF_L16,
 212         IGD_PF_ARGB32_2101010,
 213         IGD_PF_AWVU32_2101010,
 214         IGD_PF_QWVU32_8888,
 215         IGD_PF_GR32_1616,
 216         IGD_PF_VU32_1616,
 217         IGD_PF_R16F,
 218         IGD_PF_GR32_1616F,
 219         IGD_PF_R32F,
 220         IGD_PF_ABGR64_16161616F,
 221         0
 222 };
 223
 224 static igd_fb_caps_t caps_table_plb[] = {
 225         {IGD_PF_ARGB32, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 226         {IGD_PF_xRGB32, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 227         {IGD_PF_ABGR32, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 228         {IGD_PF_xBGR32, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 229         {IGD_PF_ARGB32_2101010, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 230         {IGD_PF_RGB16_565, IGD_CAP_FULL_2D | IGD_CAP_BLEND},
 231         {IGD_PF_ARGB8_INDEXED, IGD_CAP_FULL_2D},
 232         {0, 0}
 233 };
 234
 235 #endif
 236
 237 /*
 238  * Plane Definitions for PLB family.
 239  */
 240 static igd_plane_t planea_plb = {
 241         DSPACNTR, IGD_PLANE_DISPLAY | IGD_PLANE_DIH, 0, 0,
 242         fb_pixel_formats_plb, &fb_info_cmn[0], NULL
 243 };
 244
 245 static igd_plane_t planeb_plb = {
 246         DSPBCNTR, IGD_PLANE_DISPLAY | IGD_PLANE_SPRITE | IGD_PLANE_DIH, 0, 0,
 247         fb_pixel_formats_plb, &fb_info_cmn[1], NULL
 248 };
 249
 250 static igd_plane_t planec_plb = {
 251         DSPCCNTR, IGD_PLANE_SPRITE, 0, 0,
 252         OPT_MICRO_VALUE(sprite_pixel_formats_plb, NULL), NULL, NULL
 253 };
 254
 255 static igd_plane_t plane_vga_plb = {
 256         VGACNTRL, IGD_PLANE_VGA, 0, 0,
 257         vga_pixel_formats_plb, NULL, NULL
 258 };
 259
 260 static igd_plane_t plane_overlay_plb = {
 261         OVADD, IGD_PLANE_OVERLAY, 0, 0,
 262         OPT_MICRO_VALUE(overlay_pixel_formats_plb, NULL), NULL, NULL
 263 };
 264
 265 static igd_plane_t plane_cursora_plb = {
 266         CUR_A_CNTR, IGD_PLANE_CURSOR|IGD_CURSOR_USE_PIPEA|IGD_CURSOR_USE_PIPEB, 0,0,
 267         OPT_MICRO_VALUE(cursor_pixel_formats_plb, NULL), NULL, NULL
 268 };
 269
 270 static igd_plane_t plane_cursorb_plb = {
 271         CUR_B_CNTR, IGD_PLANE_CURSOR|IGD_CURSOR_USE_PIPEA|IGD_CURSOR_USE_PIPEB, 0,0,
 272         OPT_MICRO_VALUE(cursor_pixel_formats_plb, NULL), NULL, NULL
 273 };
 274
 275 /*
 276  * Plane lists for PLB family members.
 277  */
 278 /* Two Main Plane, One Sprite, One VGA, One Overlay, Two Cursor */
 279 static igd_plane_t *plane_table_plb[] = {
 280         &planeb_plb,
 281         &planea_plb,
 282         &planec_plb,
 283         &plane_vga_plb,
 284         &plane_overlay_plb,
 285         &plane_cursora_plb,
 286         &plane_cursorb_plb,
 287         NULL
 288 };
 289
 290 static igd_clock_t clock_a_plb = {
 291         DPLLACNTR, FPA0, 16
 292 };
 293
 294 static igd_clock_t clock_b_plb = {
 295         DPLLBCNTR, FPB0, 16
 296 };
 297
 298 /*
 299  * Pipe definitions for PLB family.
 300  */
 301 static igd_display_pipe_t pipea_plb = {
 302         0, PIPEA_CONF, PIPEA_TIMINGS, DPALETTE_A, &clock_a_plb,
 303         (IGD_PIPE_IS_PIPEA | IGD_PORT_SHARE_DIGITAL),
 304         0, 0,{NULL, NULL, NULL}, NULL, NULL, NULL,
 305         NULL, NULL
 306 };
 307
 308 static igd_display_pipe_t pipeb_plb = {
 309         1, PIPEB_CONF, PIPEB_TIMINGS, DPALETTE_B, &clock_b_plb,
 310         (IGD_PIPE_IS_PIPEB | IGD_PORT_SHARE_LVDS),
 311         0, 0,{NULL, NULL, NULL}, NULL, NULL, NULL,
 312         NULL, NULL
 313 };
 314
 315 static igd_display_pipe_t *pipe_table_plb[] = {
 316         &pipea_plb,
 317         &pipeb_plb,
 318         NULL
 319 };
 320
 321 /*
 322  * Port definitions for PLB family.
 323  */
 324
 325 /*
 326  * Port number: Port number is 1-number of available ports on any hardware.
 327  * Here are the definitions:
 328  *
 329  * On PLB:
 330  * =======
 331  * Port mappings:
 332  *   1 - None
 333  *   2 - DVO B port
 334  *   3 - None
 335  *   4 - Internal LVDS port
 336  *   5 - None
 337  *
 338  * Note: Port number should match with port numbers in port parameters.
 339  *       See igd_init.h for more information.
 340  */
 341
 342 #endif
 343 /*
 344  * These are the port attributes that the PLB core support.
 345  * Note that currently it only contains color correction attributes.
 346  * Eventually, this will include all the attributes.
 347  */
 348 igd_attr_t port_attrib_plb[IGD_MAX_PORTS][5] = {
 349         { /* Config for port 1:  Integrated TV Encoder (Alviso only) */
 350                 PD_MAKE_ATTR(
 351                         PD_ATTR_ID_FB_GAMMA,
 352                         PD_ATTR_TYPE_RANGE,
 353                         "Frame Buffer Gamma",
 354                         PD_ATTR_FLAG_PD_INVISIBLE,
 355                         0x202020,  /* default */
 356                         0x202020,  /* current */
 357                         0x131313,  /* Min:  ~0.6 in 3i.5f format for R-G-B*/
 358                         0xC0C0C0,  /* Max:  6 in 3i.5f format for R-G-B   */
 359                         1),
 360                 PD_MAKE_ATTR(
 361                         PD_ATTR_ID_FB_BRIGHTNESS,
 362                         PD_ATTR_TYPE_RANGE,
 363                         "Frame Buffer Brightness",
 364                         PD_ATTR_FLAG_PD_INVISIBLE,
 365                         0x808080,
 366                         0x808080,
 367                         0x000000,    /* Min: */
 368                         0xFFFFFF,    /* Max: */
 369                         1),
 370                 PD_MAKE_ATTR(
 371                         PD_ATTR_ID_FB_CONTRAST,
 372                         PD_ATTR_TYPE_RANGE,
 373                         "Frame Buffer Contrast",
 374                         PD_ATTR_FLAG_PD_INVISIBLE,
 375                         0x808080,
 376                         0x808080,
 377                         0x000000,    /* Min: */
 378                         0xFFFFFF,    /* Max: */
 379                         1),
 380                 PD_MAKE_ATTR(
 381                         PD_ATTR_ID_EXTENSION,
 382                         0,
 383                         "",
 384                         PD_ATTR_FLAG_PD_INVISIBLE|PD_ATTR_FLAG_USER_INVISIBLE,
 385                         0,
 386                         0,
 387                         0,
 388                         0,
 389                         0),
 390                 PD_MAKE_ATTR(
 391                         PD_ATTR_LIST_END,
 392                         0,
 393                         "",
 394                         0,
 395                         0,
 396                         0,
 397                         0,
 398                         0,
 399                         0)
 400         },
 401         { /* Config for port 2:  DVO B */
 402                 PD_MAKE_ATTR(
 403                         PD_ATTR_ID_FB_GAMMA,
 404                         PD_ATTR_TYPE_RANGE,
 405                         "Frame Buffer Gamma",
 406                         PD_ATTR_FLAG_PD_INVISIBLE,
 407                         0x202020,  /* default */
 408                         0x202020,  /* current */
 409                         0x131313,  /* Min:  ~0.6 in 3i.5f format for R-G-B*/
 410                         0xC0C0C0,  /* Max:  6 in 3i.5f format for R-G-B   */
 411                         1),
 412                 PD_MAKE_ATTR(
 413                         PD_ATTR_ID_FB_BRIGHTNESS,
 414                         PD_ATTR_TYPE_RANGE,
 415                         "Frame Buffer Brightness",
 416                         PD_ATTR_FLAG_PD_INVISIBLE,
 417                         0x808080,
 418                         0x808080,
 419                         0x000000,    /* Min: */
 420                         0xFFFFFF,    /* Max: */
 421                         1),
 422                 PD_MAKE_ATTR(
 423                         PD_ATTR_ID_FB_CONTRAST,
 424                         PD_ATTR_TYPE_RANGE,
 425                         "Frame Buffer Contrast",
 426                         PD_ATTR_FLAG_PD_INVISIBLE,
 427                         0x808080,
 428                         0x808080,
 429                         0x000000,    /* Min: */
 430                         0xFFFFFF,    /* Max: */
 431                         1),
 432                 PD_MAKE_ATTR(
 433                         PD_ATTR_ID_EXTENSION,
 434                         0,
 435                         "",
 436                         PD_ATTR_FLAG_PD_INVISIBLE|PD_ATTR_FLAG_USER_INVISIBLE,
 437                         0,
 438                         0,
 439                         0,
 440                         0,
 441                         0),
 442                 PD_MAKE_ATTR(
 443                         PD_ATTR_LIST_END,
 444                         0,
 445                         "",
 446                         0,
 447                         0,
 448                         0,
 449                         0,
 450                         0,
 451                         0)
 452         },
 453         { /* Config for port 3:  DVO C */
 454                 PD_MAKE_ATTR(
 455                         PD_ATTR_ID_FB_GAMMA,
 456                         PD_ATTR_TYPE_RANGE,
 457                         "Frame Buffer Gamma",
 458                         PD_ATTR_FLAG_PD_INVISIBLE,
 459                         0x202020,  /* default */
 460                         0x202020,  /* current */
 461                         0x131313,  /* Min:  ~0.6 in 3i.5f format for R-G-B*/
 462                         0xC0C0C0,  /* Max:  6 in 3i.5f format for R-G-B   */
 463                         1),
 464                 PD_MAKE_ATTR(
 465                         PD_ATTR_ID_FB_BRIGHTNESS,
 466                         PD_ATTR_TYPE_RANGE,
 467                         "Frame Buffer Brightness",
 468                         PD_ATTR_FLAG_PD_INVISIBLE,
 469                         0x808080,
 470                         0x808080,
 471                         0x000000,    /* Min: */
 472                         0xFFFFFF,    /* Max: */
 473                         1),
 474                 PD_MAKE_ATTR(
 475                         PD_ATTR_ID_FB_CONTRAST,
 476                         PD_ATTR_TYPE_RANGE,
 477                         "Frame Buffer Contrast",
 478                         PD_ATTR_FLAG_PD_INVISIBLE,
 479                         0x808080,
 480                         0x808080,
 481                         0x000000,    /* Min: */
 482                         0xFFFFFF,    /* Max: */
 483                         1),
 484                 PD_MAKE_ATTR(
 485                         PD_ATTR_ID_EXTENSION,
 486                         0,
 487                         "",
 488                         PD_ATTR_FLAG_PD_INVISIBLE|PD_ATTR_FLAG_USER_INVISIBLE,
 489                         0,
 490                         0,
 491                         0,
 492                         0,
 493                         0),
 494                 PD_MAKE_ATTR(
 495                         PD_ATTR_LIST_END,
 496                         0,
 497                         "",
 498                         0,
 499                         0,
 500                         0,
 501                         0,
 502                         0,
 503                         0)
 504         },
 505         { /* Config for port 4:  LVDS */
 506                 PD_MAKE_ATTR(
 507                         PD_ATTR_ID_FB_GAMMA,
 508                         PD_ATTR_TYPE_RANGE,
 509                         "Frame Buffer Gamma",
 510                         PD_ATTR_FLAG_PD_INVISIBLE,
 511                         0x202020,  /* default */
 512                         0x202020,  /* current */
 513                         0x131313,  /* Min:  ~0.6 in 3i.5f format for R-G-B*/
 514                         0xC0C0C0,  /* Max:  6 in 3i.5f format for R-G-B   */
 515                         1),
 516                 PD_MAKE_ATTR(
 517                         PD_ATTR_ID_FB_BRIGHTNESS,
 518                         PD_ATTR_TYPE_RANGE,
 519                         "Frame Buffer Brightness",
 520                         PD_ATTR_FLAG_PD_INVISIBLE,
 521                         0x808080,
 522                         0x808080,
 523                         0x000000,    /* Min: */
 524                         0xFFFFFF,    /* Max: */
 525                         1),
 526                 PD_MAKE_ATTR(
 527                         PD_ATTR_ID_FB_CONTRAST,
 528                         PD_ATTR_TYPE_RANGE,
 529                         "Frame Buffer Contrast",
 530                         PD_ATTR_FLAG_PD_INVISIBLE,
 531                         0x808080,
 532                         0x808080,
 533                         0x000000,    /* Min: */
 534                         0xFFFFFF,    /* Max: */
 535                         1),
 536                 PD_MAKE_ATTR(
 537                         PD_ATTR_ID_EXTENSION,
 538                         0,
 539                         "",
 540                         PD_ATTR_FLAG_PD_INVISIBLE|PD_ATTR_FLAG_USER_INVISIBLE,
 541                         0,
 542                         0,
 543                         0,
 544                         0,
 545                         0),
 546                 PD_MAKE_ATTR(
 547                         PD_ATTR_LIST_END,
 548                         0,
 549                         "",
 550                         0,
 551                         0,
 552                         0,
 553                         0,
 554                         0,
 555                         0)
 556         },
 557         { /* Config for port 5:  ANALOG */
 558                 PD_MAKE_ATTR(
 559                         PD_ATTR_ID_FB_GAMMA,
 560                         PD_ATTR_TYPE_RANGE,
 561                         "Frame Buffer Gamma",
 562                         PD_ATTR_FLAG_PD_INVISIBLE,
 563                         0x202020,  /* default */
 564                         0x202020,  /* current */
 565                         0x131313,  /* Min:  ~0.6 in 3i.5f format for R-G-B*/
 566                         0xC0C0C0,  /* Max:  6 in 3i.5f format for R-G-B   */
 567                         1),
 568                 PD_MAKE_ATTR(
 569                         PD_ATTR_ID_FB_BRIGHTNESS,
 570                         PD_ATTR_TYPE_RANGE,
 571                         "Frame Buffer Brightness",
 572                         PD_ATTR_FLAG_PD_INVISIBLE,
 573                         0x808080,
 574                         0x808080,
 575                         0x000000,    /* Min: */
 576                         0xFFFFFF,    /* Max: */
 577                         1),
 578                 PD_MAKE_ATTR(
 579                         PD_ATTR_ID_FB_CONTRAST,
 580                         PD_ATTR_TYPE_RANGE,
 581                         "Frame Buffer Contrast",
 582                         PD_ATTR_FLAG_PD_INVISIBLE,
 583                         0x808080,
 584                         0x808080,
 585                         0x000000,    /* Min: */
 586                         0xFFFFFF,    /* Max: */
 587                         1),
 588                 PD_MAKE_ATTR(
 589                         PD_ATTR_ID_EXTENSION,
 590                         0,
 591                         "",
 592                         PD_ATTR_FLAG_PD_INVISIBLE|PD_ATTR_FLAG_USER_INVISIBLE,
 593                         0,
 594                         0,
 595                         0,
 596                         0,
 597                         0),
 598                 PD_MAKE_ATTR(
 599                         PD_ATTR_LIST_END,
 600                         0,
 601                         "",
 602                         0,
 603                         0,
 604                         0,
 605                         0,
 606                         0,
 607                         0)
 608         }
 609 };
 610
 611 #ifdef CONFIG_PLB
 612
 613 igd_display_port_t dvob_port_plb = {
 614         IGD_PORT_DIGITAL, 2, "SDVO B", 0x61140, GMBUS_DVO_REG, 0,
 615         GMBUS_DVOB_DDC, 0xA0,
 616         (IGD_PORT_USE_PIPEA | IGD_VGA_COMPRESS | IGD_RGBA_COLOR |
 617          IGD_PORT_GANG),
 618         TVCLKINBC, 0, IGD_POWERSTATE_D0, IGD_POWERSTATE_D0,
 619         NULL, NULL,
 620         NULL, NULL, NULL, 0, NULL, 0,
 621         DDC_DEFAULT_SPEED, NULL, NULL, NULL, NULL, 0, NULL, 0, 0,
 622         IGD_POWERSTATE_UNDEFINED,
 623         port_attrib_plb[2 - 1], /* Port Number - 1 */
 624         0, { NULL },
 625         (BIT14 | BIT16 | BIT17),
 626         (BIT17), 1,
 627
 628 };
 629
 630 static igd_display_port_t lvds_port_plb = {
 631         IGD_PORT_LVDS, 4, "IntLVDS", 0x61180, 0, 0,
 632         GMBUS_INT_LVDS_DDC, 0xA0,
 633         (IGD_PORT_USE_PIPEB | IGD_VGA_COMPRESS),
 634         DREFCLK, 0, IGD_POWERSTATE_D0, IGD_POWERSTATE_D0, NULL, NULL,
 635         NULL, NULL, NULL, 0, NULL, 0,
 636         DDC_DEFAULT_SPEED, NULL, NULL, NULL, NULL, 0, NULL, 0, 0,
 637         IGD_POWERSTATE_UNDEFINED,
 638         port_attrib_plb[4 - 1], /* Port Number - 1 */
 639         0, { NULL }, 0, 0, 0,
 640 };
 641
 642 static igd_display_port_t *port_table_plb[] = {
 643         &lvds_port_plb,
 644         &dvob_port_plb,
 645         NULL
 646 };
 647
 648 static int dsp_init_plb(igd_context_t *context)
 649 {
 650         return 0;
 651 }
 652
 653 void dsp_control_plane_format_plb(igd_context_t *context,
 654                 int enable, int plane, igd_plane_t *plane_override)
 655 {
 656         igd_plane_t * pl = NULL;
 657         unsigned char *mmio = EMGD_MMIO(context->device_context.virt_mmadr);
 658         unsigned long tmp;
 659
 660         if (plane_override == NULL) {
 661                 pl = (plane == 0) ? &planea_plb : &planeb_plb;
 662         } else {
 663                 pl = plane_override;
 664         }
 665         tmp = EMGD_READ32(mmio +  pl->plane_reg);
 666
 667         /*
 668          * Pixel format bits (29:26) are in plane control register 0x70180 for
 669          * Plane A and 0x71180 for Plane B
 670          * 0110 = XRGB pixel format
 671          * 0111 = ARGB pixel format
 672          * Note that the plane control register is double buffered and will be
 673          * updated on the next VBLANK operation so there is no need to sync with
 674          * an explicit VSYNC.
 675          */
 676         if(enable) {
 677                 if((tmp & DSPxCNTR_SRC_FMT_MASK) == DSPxCNTR_RGB_8888) {
 678                         EMGD_WRITE32(tmp | DSPxCNTR_ARGB_8888, mmio +  pl->plane_reg);
 679                         tmp = EMGD_READ32(mmio + pl->plane_reg + 4);
 680                         EMGD_WRITE32(tmp, mmio + pl->plane_reg + 4);
 681                         EMGD_DEBUG("Changed pixel format from XRGB to ARGB\n");
 682                 }
 683         } else {
 684                 if((tmp & DSPxCNTR_SRC_FMT_MASK) == DSPxCNTR_ARGB_8888) {
 685                         tmp = tmp & (~(DSPxCNTR_SRC_FMT_MASK));
 686                         EMGD_WRITE32(tmp | DSPxCNTR_RGB_8888, mmio +  pl->plane_reg);
 687                         tmp = EMGD_READ32(mmio + pl->plane_reg + 4);
 688                         EMGD_WRITE32(tmp, mmio + pl->plane_reg + 4);
 689                         OS_SLEEP(100);
 690                         EMGD_DEBUG("Changed pixel format from ARGB to XRGB\n");
 691                 }
 692         }
 693         EMGD_DEBUG("Plane register 0x%lX has value of 0x%X\n", pl->plane_reg,
 694                         EMGD_READ32(mmio + pl->plane_reg));
 695
 696 }
 697
 698 dsp_dispatch_t dsp_dispatch_plb = {
 699         plane_table_plb, pipe_table_plb, port_table_plb,
 700         OPT_MICRO_VALUE(caps_table_plb, NULL),
 701         OPT_MICRO_VALUE(overlay_pixel_formats_plb, NULL),
 702         OPT_MICRO_VALUE(render_pixel_formats_plb, NULL),
 703         OPT_MICRO_VALUE(texture_pixel_formats_plb, NULL),
 704         dsp_init_plb,
 705         dsp_control_plane_format_plb,
 706 };
 707
 708 #endif
 709