1 // SPDX-License-Identifier: GPL-2.0
3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
4 * Originally split out from the skx_edac driver.
6 * Copyright (c) 2018, Intel Corporation.
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/adxl.h>
12 #include <acpi/nfit.h>
14 #include "edac_module.h"
15 #include "skx_common.h"
17 static const char * const component_names[] = {
18 [INDEX_SOCKET] = "ProcessorSocketId",
19 [INDEX_MEMCTRL] = "MemoryControllerId",
20 [INDEX_CHANNEL] = "ChannelId",
21 [INDEX_DIMM] = "DimmSlotId",
24 static int component_indices[ARRAY_SIZE(component_names)];
25 static int adxl_component_count;
26 static const char * const *adxl_component_names;
27 static u64 *adxl_values;
28 static char *adxl_msg;
30 static char skx_msg[MSG_SIZE];
31 static skx_decode_f skx_decode;
32 static u64 skx_tolm, skx_tohm;
33 static LIST_HEAD(dev_edac_list);
35 int __init skx_adxl_get(void)
37 const char * const *names;
40 names = adxl_get_component_names();
42 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
46 for (i = 0; i < INDEX_MAX; i++) {
47 for (j = 0; names[j]; j++) {
48 if (!strcmp(component_names[i], names[j])) {
49 component_indices[i] = j;
58 adxl_component_names = names;
60 adxl_component_count++;
62 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
65 adxl_component_count = 0;
69 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
71 adxl_component_count = 0;
78 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
80 for (j = 0; names[j]; j++)
81 skx_printk(KERN_CONT, "%s ", names[j]);
82 skx_printk(KERN_CONT, "\n");
87 void __exit skx_adxl_put(void)
93 static bool skx_adxl_decode(struct decoded_addr *res)
97 if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
98 res->addr < BIT_ULL(32))) {
99 edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
103 if (adxl_decode(res->addr, adxl_values)) {
104 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
108 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
109 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
110 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
111 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
113 for (i = 0; i < adxl_component_count; i++) {
114 if (adxl_values[i] == ~0x0ull)
117 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
118 adxl_component_names[i], adxl_values[i]);
119 if (MSG_SIZE - len <= 0)
126 void skx_set_decode(skx_decode_f decode)
131 int skx_get_src_id(struct skx_dev *d, u8 *id)
135 if (pci_read_config_dword(d->util_all, 0xf0, ®)) {
136 skx_printk(KERN_ERR, "Failed to read src id\n");
140 *id = GET_BITFIELD(reg, 12, 14);
144 int skx_get_node_id(struct skx_dev *d, u8 *id)
148 if (pci_read_config_dword(d->util_all, 0xf4, ®)) {
149 skx_printk(KERN_ERR, "Failed to read node id\n");
153 *id = GET_BITFIELD(reg, 0, 2);
157 static int get_width(u32 mtr)
159 switch (GET_BITFIELD(mtr, 8, 9)) {
171 * We use the per-socket device @did to count how many sockets are present,
172 * and to detemine which PCI buses are associated with each socket. Allocate
173 * and build the full list of all the skx_dev structures that we need here.
175 int skx_get_all_bus_mappings(unsigned int did, int off, enum type type,
176 struct list_head **list)
178 struct pci_dev *pdev, *prev;
185 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, prev);
189 d = kzalloc(sizeof(*d), GFP_KERNEL);
195 if (pci_read_config_dword(pdev, off, ®)) {
198 skx_printk(KERN_ERR, "Failed to read bus idx\n");
202 d->bus[0] = GET_BITFIELD(reg, 0, 7);
203 d->bus[1] = GET_BITFIELD(reg, 8, 15);
205 d->seg = pci_domain_nr(pdev->bus);
206 d->bus[2] = GET_BITFIELD(reg, 16, 23);
207 d->bus[3] = GET_BITFIELD(reg, 24, 31);
209 d->seg = GET_BITFIELD(reg, 16, 23);
212 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
213 d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
214 list_add_tail(&d->list, &dev_edac_list);
219 *list = &dev_edac_list;
223 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
225 struct pci_dev *pdev;
228 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
230 skx_printk(KERN_ERR, "Can't get tolm/tohm\n");
234 if (pci_read_config_dword(pdev, off[0], ®)) {
235 skx_printk(KERN_ERR, "Failed to read tolm\n");
240 if (pci_read_config_dword(pdev, off[1], ®)) {
241 skx_printk(KERN_ERR, "Failed to read lower tohm\n");
246 if (pci_read_config_dword(pdev, off[2], ®)) {
247 skx_printk(KERN_ERR, "Failed to read upper tohm\n");
250 skx_tohm |= (u64)reg << 32;
255 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
262 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
263 int minval, int maxval, const char *name)
265 u32 val = GET_BITFIELD(reg, lobit, hibit);
267 if (val < minval || val > maxval) {
268 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
274 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
275 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
276 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
278 int skx_get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm,
279 struct skx_imc *imc, int chan, int dimmno)
281 int banks = 16, ranks, rows, cols, npages;
284 ranks = numrank(mtr);
289 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
291 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
292 npages = MiB_TO_PAGES(size);
294 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
295 imc->mc, chan, dimmno, size, npages,
296 banks, 1 << ranks, rows, cols);
298 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0);
299 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9);
300 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
301 imc->chan[chan].dimms[dimmno].rowbits = rows;
302 imc->chan[chan].dimms[dimmno].colbits = cols;
304 dimm->nr_pages = npages;
306 dimm->dtype = get_width(mtr);
307 dimm->mtype = MEM_DDR4;
308 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
309 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
310 imc->src_id, imc->lmc, chan, dimmno);
315 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
316 int chan, int dimmno, const char *mod_str)
323 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
326 smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
327 if (smbios_handle == -EOPNOTSUPP) {
328 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
332 if (smbios_handle < 0) {
333 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
337 if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
338 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
342 size = dmi_memdev_size(smbios_handle);
344 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
345 dev_handle, smbios_handle);
348 dimm->nr_pages = size >> PAGE_SHIFT;
350 dimm->dtype = DEV_UNKNOWN;
351 dimm->mtype = MEM_NVDIMM;
352 dimm->edac_mode = EDAC_SECDED; /* likely better than this */
354 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
355 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
357 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
358 imc->src_id, imc->lmc, chan, dimmno);
360 return (size == 0 || size == ~0ull) ? 0 : 1;
363 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
364 const char *ctl_name, const char *mod_str,
365 get_dimm_config_f get_dimm_config)
367 struct mem_ctl_info *mci;
368 struct edac_mc_layer layers[2];
372 /* Allocate a new MC control structure */
373 layers[0].type = EDAC_MC_LAYER_CHANNEL;
374 layers[0].size = NUM_CHANNELS;
375 layers[0].is_virt_csrow = false;
376 layers[1].type = EDAC_MC_LAYER_SLOT;
377 layers[1].size = NUM_DIMMS;
378 layers[1].is_virt_csrow = true;
379 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
380 sizeof(struct skx_pvt));
385 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
387 /* Associate skx_dev and mci for future usage */
392 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
393 imc->node_id, imc->lmc);
394 if (!mci->ctl_name) {
399 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
400 mci->edac_ctl_cap = EDAC_FLAG_NONE;
401 mci->edac_cap = EDAC_FLAG_NONE;
402 mci->mod_name = mod_str;
403 mci->dev_name = pci_name(pdev);
404 mci->ctl_page_to_phys = NULL;
406 rc = get_dimm_config(mci);
410 /* Record ptr to the generic device */
411 mci->pdev = &pdev->dev;
413 /* Add this new MC control structure to EDAC's list of MCs */
414 if (unlikely(edac_mc_add_mc(mci))) {
415 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
423 kfree(mci->ctl_name);
430 static void skx_unregister_mci(struct skx_imc *imc)
432 struct mem_ctl_info *mci = imc->mci;
437 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
439 /* Remove MC sysfs nodes */
440 edac_mc_del_mc(mci->pdev);
442 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
443 kfree(mci->ctl_name);
447 static struct mem_ctl_info *get_mci(int src_id, int lmc)
451 if (lmc > NUM_IMC - 1) {
452 skx_printk(KERN_ERR, "Bad lmc %d\n", lmc);
456 list_for_each_entry(d, &dev_edac_list, list) {
457 if (d->imc[0].src_id == src_id)
458 return d->imc[lmc].mci;
461 skx_printk(KERN_ERR, "No mci for src_id %d lmc %d\n", src_id, lmc);
465 static void skx_mce_output_error(struct mem_ctl_info *mci,
467 struct decoded_addr *res)
469 enum hw_event_mc_err_type tp_event;
471 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
472 bool overflow = GET_BITFIELD(m->status, 62, 62);
473 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
475 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
476 u32 mscod = GET_BITFIELD(m->status, 16, 31);
477 u32 errcode = GET_BITFIELD(m->status, 0, 15);
478 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
480 recoverable = GET_BITFIELD(m->status, 56, 56);
482 if (uncorrected_error) {
486 tp_event = HW_EVENT_ERR_FATAL;
489 tp_event = HW_EVENT_ERR_UNCORRECTED;
493 tp_event = HW_EVENT_ERR_CORRECTED;
497 * According to Intel Architecture spec vol 3B,
498 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
499 * memory errors should fit one of these masks:
500 * 000f 0000 1mmm cccc (binary)
501 * 000f 0010 1mmm cccc (binary) [RAM used as cache]
503 * f = Correction Report Filtering Bit. If 1, subsequent errors
507 * If the mask doesn't match, report an error to the parsing logic
509 if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
510 optype = "Can't parse: it is not a mem";
514 optype = "generic undef request error";
517 optype = "memory read error";
520 optype = "memory write error";
523 optype = "addr/cmd error";
526 optype = "memory scrubbing error";
533 if (adxl_component_count) {
534 snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
535 overflow ? " OVERFLOW" : "",
536 (uncorrected_error && recoverable) ? " recoverable" : "",
537 mscod, errcode, adxl_msg);
539 snprintf(skx_msg, MSG_SIZE,
540 "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
541 overflow ? " OVERFLOW" : "",
542 (uncorrected_error && recoverable) ? " recoverable" : "",
544 res->socket, res->imc, res->rank,
545 res->bank_group, res->bank_address, res->row, res->column);
548 edac_dbg(0, "%s\n", skx_msg);
550 /* Call the helper to output message */
551 edac_mc_handle_error(tp_event, mci, core_err_cnt,
552 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
553 res->channel, res->dimm, -1,
557 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
560 struct mce *mce = (struct mce *)data;
561 struct decoded_addr res;
562 struct mem_ctl_info *mci;
565 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
568 /* ignore unless this is memory related with an address */
569 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
572 memset(&res, 0, sizeof(res));
573 res.addr = mce->addr;
575 if (adxl_component_count) {
576 if (!skx_adxl_decode(&res))
579 mci = get_mci(res.socket, res.imc);
581 if (!skx_decode || !skx_decode(&res))
584 mci = res.dev->imc[res.imc].mci;
590 if (mce->mcgstatus & MCG_STATUS_MCIP)
595 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
597 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
598 "Bank %d: 0x%llx\n", mce->extcpu, type,
599 mce->mcgstatus, mce->bank, mce->status);
600 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
601 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
602 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
604 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
605 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
606 mce->time, mce->socketid, mce->apicid);
608 skx_mce_output_error(mci, mce, &res);
613 void skx_remove(void)
616 struct skx_dev *d, *tmp;
620 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
622 for (i = 0; i < NUM_IMC; i++) {
624 skx_unregister_mci(&d->imc[i]);
627 pci_dev_put(d->imc[i].mdev);
630 iounmap(d->imc[i].mbase);
632 for (j = 0; j < NUM_CHANNELS; j++) {
633 if (d->imc[i].chan[j].cdev)
634 pci_dev_put(d->imc[i].chan[j].cdev);
638 pci_dev_put(d->util_all);
640 pci_dev_put(d->sad_all);
642 pci_dev_put(d->uracu);
648 #ifdef CONFIG_EDAC_DEBUG
651 * Exercise the address decode logic by writing an address to
652 * /sys/kernel/debug/edac/dirname/addr.
654 static struct dentry *skx_test;
656 static int debugfs_u64_set(void *data, u64 val)
660 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
662 memset(&m, 0, sizeof(m));
663 /* ADDRV + MemRd + Unknown channel */
664 m.status = MCI_STATUS_ADDRV + 0x90;
665 /* One corrected error */
666 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
668 skx_mce_check_error(NULL, 0, &m);
672 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
674 void setup_skx_debug(const char *dirname)
676 skx_test = edac_debugfs_create_dir(dirname);
680 if (!edac_debugfs_create_file("addr", 0200, skx_test,
681 NULL, &fops_u64_wo)) {
682 debugfs_remove(skx_test);
687 void teardown_skx_debug(void)
689 debugfs_remove_recursive(skx_test);
691 #endif /*CONFIG_EDAC_DEBUG*/