1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
4 * This driver supports the memory controllers found on the Intel
5 * processor family Sandy Bridge.
7 * Copyright (c) 2011 by:
8 * Mauro Carvalho Chehab
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pci_ids.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/edac.h>
18 #include <linux/mmzone.h>
19 #include <linux/smp.h>
20 #include <linux/bitmap.h>
21 #include <linux/math64.h>
22 #include <linux/mod_devicetable.h>
23 #include <asm/cpu_device_id.h>
24 #include <asm/intel-family.h>
25 #include <asm/processor.h>
28 #include "edac_module.h"
31 static LIST_HEAD(sbridge_edac_list);
34 * Alter this version for the module when modifications are made
36 #define SBRIDGE_REVISION " Ver: 1.1.2 "
37 #define EDAC_MOD_STR "sb_edac"
42 #define sbridge_printk(level, fmt, arg...) \
43 edac_printk(level, "sbridge", fmt, ##arg)
45 #define sbridge_mc_printk(mci, level, fmt, arg...) \
46 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
49 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 #define GET_BITFIELD(v, lo, hi) \
52 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
54 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
55 static const u32 sbridge_dram_rule[] = {
56 0x80, 0x88, 0x90, 0x98, 0xa0,
57 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
60 static const u32 ibridge_dram_rule[] = {
61 0x60, 0x68, 0x70, 0x78, 0x80,
62 0x88, 0x90, 0x98, 0xa0, 0xa8,
63 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
64 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
67 static const u32 knl_dram_rule[] = {
68 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
69 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
70 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
71 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
72 0x100, 0x108, 0x110, 0x118, /* 20-23 */
75 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
76 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
78 static char *show_dram_attr(u32 attr)
92 static const u32 sbridge_interleave_list[] = {
93 0x84, 0x8c, 0x94, 0x9c, 0xa4,
94 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
97 static const u32 ibridge_interleave_list[] = {
98 0x64, 0x6c, 0x74, 0x7c, 0x84,
99 0x8c, 0x94, 0x9c, 0xa4, 0xac,
100 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
101 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
104 static const u32 knl_interleave_list[] = {
105 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
106 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
107 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
108 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
109 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
111 #define MAX_INTERLEAVE \
112 (max_t(unsigned int, ARRAY_SIZE(sbridge_interleave_list), \
113 max_t(unsigned int, ARRAY_SIZE(ibridge_interleave_list), \
114 ARRAY_SIZE(knl_interleave_list))))
116 struct interleave_pkg {
121 static const struct interleave_pkg sbridge_interleave_pkg[] = {
132 static const struct interleave_pkg ibridge_interleave_pkg[] = {
143 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
146 return GET_BITFIELD(reg, table[interleave].start,
147 table[interleave].end);
150 /* Devices 12 Function 7 */
154 #define HASWELL_TOLM 0xd0
155 #define HASWELL_TOHM_0 0xd4
156 #define HASWELL_TOHM_1 0xd8
157 #define KNL_TOLM 0xd0
158 #define KNL_TOHM_0 0xd4
159 #define KNL_TOHM_1 0xd8
161 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
162 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
164 /* Device 13 Function 6 */
166 #define SAD_TARGET 0xf0
168 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
170 #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
172 #define SAD_CONTROL 0xf4
174 /* Device 14 function 0 */
176 static const u32 tad_dram_rule[] = {
177 0x40, 0x44, 0x48, 0x4c,
178 0x50, 0x54, 0x58, 0x5c,
179 0x60, 0x64, 0x68, 0x6c,
181 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
183 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
184 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
185 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
186 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
187 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
188 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
189 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
191 /* Device 15, function 0 */
194 #define KNL_MCMTR 0x624
196 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
197 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
198 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
200 /* Device 15, function 1 */
202 #define RASENABLES 0xac
203 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
205 /* Device 15, functions 2-5 */
207 static const int mtr_regs[] = {
211 static const int knl_mtr_reg = 0xb60;
213 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
214 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
215 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
216 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
217 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
219 static const u32 tad_ch_nilv_offset[] = {
220 0x90, 0x94, 0x98, 0x9c,
221 0xa0, 0xa4, 0xa8, 0xac,
222 0xb0, 0xb4, 0xb8, 0xbc,
224 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
225 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
227 static const u32 rir_way_limit[] = {
228 0x108, 0x10c, 0x110, 0x114, 0x118,
230 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
232 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
233 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
235 #define MAX_RIR_WAY 8
237 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
238 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
239 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
240 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
241 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
242 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
245 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
246 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
248 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
249 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
251 /* Device 16, functions 2-7 */
254 * FIXME: Implement the error count reads directly
257 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
258 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
259 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
260 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
262 #if 0 /* Currently unused*/
263 static const u32 correrrcnt[] = {
264 0x104, 0x108, 0x10c, 0x110,
267 static const u32 correrrthrsld[] = {
268 0x11c, 0x120, 0x124, 0x128,
272 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
273 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
276 /* Device 17, function 0 */
278 #define SB_RANK_CFG_A 0x0328
280 #define IB_RANK_CFG_A 0x0320
286 #define NUM_CHANNELS 6 /* Max channels per MC */
287 #define MAX_DIMMS 3 /* Max DIMMS per channel */
288 #define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */
289 #define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */
290 #define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */
291 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
307 enum mirroring_mode {
309 ADDR_RANGE_MIRRORING,
314 struct sbridge_info {
318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
320 u64 (*rir_limit)(u32 reg);
321 u64 (*sad_limit)(u32 reg);
322 u32 (*interleave_mode)(u32 reg);
323 u32 (*dram_attr)(u32 reg);
324 const u32 *dram_rule;
325 const u32 *interleave_list;
326 const struct interleave_pkg *interleave_pkg;
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
329 u8 (*get_ha)(u8 bank);
330 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
331 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
332 struct pci_dev *pci_vtd;
335 struct sbridge_channel {
340 struct pci_id_descr {
346 struct pci_id_table {
347 const struct pci_id_descr *descr;
355 struct list_head list;
358 u8 node_id, source_id;
359 struct pci_dev **pdev;
363 struct mem_ctl_info *mci;
367 struct pci_dev *pci_cha[KNL_MAX_CHAS];
368 struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
369 struct pci_dev *pci_mc0;
370 struct pci_dev *pci_mc1;
371 struct pci_dev *pci_mc0_misc;
372 struct pci_dev *pci_mc1_misc;
373 struct pci_dev *pci_mc_info; /* tolm, tohm */
377 /* Devices per socket */
378 struct pci_dev *pci_ddrio;
379 struct pci_dev *pci_sad0, *pci_sad1;
380 struct pci_dev *pci_br0, *pci_br1;
381 /* Devices per memory controller */
382 struct pci_dev *pci_ha, *pci_ta, *pci_ras;
383 struct pci_dev *pci_tad[NUM_CHANNELS];
385 struct sbridge_dev *sbridge_dev;
387 struct sbridge_info info;
388 struct sbridge_channel channel[NUM_CHANNELS];
390 /* Memory type detection */
391 bool is_cur_addr_mirrored, is_lockstep, is_close_pg;
393 enum mirroring_mode mirror_mode;
395 /* Memory description */
400 #define PCI_DESCR(device_id, opt, domain) \
401 .dev_id = (device_id), \
405 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
406 /* Processor Home Agent */
407 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0, IMC0) },
409 /* Memory controller */
410 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0, IMC0) },
411 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0, IMC0) },
412 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0, IMC0) },
413 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0, IMC0) },
414 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0, IMC0) },
415 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0, IMC0) },
416 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
418 /* System Address Decoder */
419 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0, SOCK) },
420 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0, SOCK) },
422 /* Broadcast Registers */
423 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0, SOCK) },
426 #define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
428 .n_devs_per_imc = N, \
429 .n_devs_per_sock = ARRAY_SIZE(A), \
430 .n_imcs_per_sock = M, \
434 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
435 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
436 {0,} /* 0 terminated list. */
439 /* This changes depending if 1HA or 2HA:
441 * 0x0eb8 (17.0) is DDRIO0
443 * 0x0ebc (17.4) is DDRIO0
445 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
446 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
449 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
450 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
451 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
452 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
455 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
456 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
461 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
462 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
463 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
464 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
465 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
467 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
468 /* Processor Home Agent */
469 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0, IMC0) },
470 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1, IMC1) },
472 /* Memory controller */
473 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0, IMC0) },
474 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0, IMC0) },
475 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0, IMC0) },
476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0, IMC0) },
477 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0, IMC0) },
478 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0, IMC0) },
480 /* Optional, mode 2HA */
481 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1, IMC1) },
482 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1, IMC1) },
483 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1, IMC1) },
484 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1, IMC1) },
485 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1, IMC1) },
486 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1, IMC1) },
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
489 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
491 /* System Address Decoder */
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0, SOCK) },
494 /* Broadcast Registers */
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1, SOCK) },
496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0, SOCK) },
500 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
501 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
502 {0,} /* 0 terminated list. */
505 /* Haswell support */
508 * - 3 DDR3 channels, 2 DPC per channel
511 * - 4 DDR4 channels, 3 DPC per channel
514 * - 4 DDR4 channels, 3 DPC per channel
517 * - each IMC interfaces with a SMI 2 channel
518 * - each SMI channel interfaces with a scalable memory buffer
519 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
521 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
522 #define HASWELL_HASYSDEFEATURE2 0x84
523 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
524 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
525 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
526 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
527 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0x2f71
528 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
529 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0x2f79
530 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
539 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
540 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
541 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
542 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
543 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
544 static const struct pci_id_descr pci_dev_descr_haswell[] = {
545 /* first item must be the HA */
546 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0, IMC0) },
547 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1, IMC1) },
549 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0, IMC0) },
550 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM, 0, IMC0) },
551 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
552 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
553 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
554 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
556 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1, IMC1) },
557 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM, 1, IMC1) },
558 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
559 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
560 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
561 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
563 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
564 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
565 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1, SOCK) },
566 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1, SOCK) },
567 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1, SOCK) },
568 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1, SOCK) },
571 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
572 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
573 {0,} /* 0 terminated list. */
576 /* Knight's Landing Support */
578 * KNL's memory channels are swizzled between memory controllers.
579 * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
581 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
583 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
584 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
585 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
586 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0x7843
587 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
588 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
589 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
590 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a
591 /* SAD target - 1-29-1 (1 of these) */
592 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b
593 /* Caching / Home Agent */
594 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c
595 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
596 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810
599 * KNL differs from SB, IB, and Haswell in that it has multiple
600 * instances of the same device with the same device ID, so we handle that
601 * by creating as many copies in the table as we expect to find.
602 * (Like device ID must be grouped together.)
605 static const struct pci_id_descr pci_dev_descr_knl[] = {
606 [0 ... 1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0, IMC0)},
607 [2 ... 7] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0, IMC0) },
608 [8] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0, IMC0) },
609 [9] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
610 [10] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0, SOCK) },
611 [11] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0, SOCK) },
612 [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0, SOCK) },
615 static const struct pci_id_table pci_dev_descr_knl_table[] = {
616 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
625 * - 2 DDR3 channels, 2 DPC per channel
628 * - 4 DDR4 channels, 3 DPC per channel
631 * - 4 DDR4 channels, 3 DPC per channel
634 * - each IMC interfaces with a SMI 2 channel
635 * - each SMI channel interfaces with a scalable memory buffer
636 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
638 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
639 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
640 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
641 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
642 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0x6f71
643 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
644 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0x6f79
645 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
651 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
652 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
653 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
654 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
655 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
657 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
658 /* first item must be the HA */
659 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0, IMC0) },
660 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1, IMC1) },
662 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0, IMC0) },
663 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM, 0, IMC0) },
664 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
665 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
666 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
667 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
669 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1, IMC1) },
670 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM, 1, IMC1) },
671 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
672 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
673 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
674 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
676 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
677 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
678 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1, SOCK) },
681 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
682 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
683 {0,} /* 0 terminated list. */
687 /****************************************************************************
688 Ancillary status routines
689 ****************************************************************************/
691 static inline int numrank(enum type type, u32 mtr)
693 int ranks = (1 << RANK_CNT_BITS(mtr));
696 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
700 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
701 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
708 static inline int numrow(u32 mtr)
710 int rows = (RANK_WIDTH_BITS(mtr) + 12);
712 if (rows < 13 || rows > 18) {
713 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
714 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
721 static inline int numcol(u32 mtr)
723 int cols = (COL_WIDTH_BITS(mtr) + 10);
726 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
727 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
734 static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom,
736 struct sbridge_dev *prev)
738 struct sbridge_dev *sbridge_dev;
741 * If we have devices scattered across several busses that pertain
742 * to the same memory controller, we'll lump them all together.
745 return list_first_entry_or_null(&sbridge_edac_list,
746 struct sbridge_dev, list);
749 sbridge_dev = list_entry(prev ? prev->list.next
750 : sbridge_edac_list.next, struct sbridge_dev, list);
752 list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) {
753 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) &&
754 (dom == SOCK || dom == sbridge_dev->dom))
761 static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom,
762 const struct pci_id_table *table)
764 struct sbridge_dev *sbridge_dev;
766 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
770 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc,
771 sizeof(*sbridge_dev->pdev),
773 if (!sbridge_dev->pdev) {
778 sbridge_dev->seg = seg;
779 sbridge_dev->bus = bus;
780 sbridge_dev->dom = dom;
781 sbridge_dev->n_devs = table->n_devs_per_imc;
782 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
787 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
789 list_del(&sbridge_dev->list);
790 kfree(sbridge_dev->pdev);
794 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
798 /* Address range is 32:28 */
799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
800 return GET_TOLM(reg);
803 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
808 return GET_TOHM(reg);
811 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
815 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
817 return GET_TOLM(reg);
820 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
824 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
826 return GET_TOHM(reg);
829 static u64 rir_limit(u32 reg)
831 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
834 static u64 sad_limit(u32 reg)
836 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
839 static u32 interleave_mode(u32 reg)
841 return GET_BITFIELD(reg, 1, 1);
844 static u32 dram_attr(u32 reg)
846 return GET_BITFIELD(reg, 2, 3);
849 static u64 knl_sad_limit(u32 reg)
851 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
854 static u32 knl_interleave_mode(u32 reg)
856 return GET_BITFIELD(reg, 1, 2);
859 static const char * const knl_intlv_mode[] = {
860 "[8:6]", "[10:8]", "[14:12]", "[32:30]"
863 static const char *get_intlv_mode_str(u32 reg, enum type t)
865 if (t == KNIGHTS_LANDING)
866 return knl_intlv_mode[knl_interleave_mode(reg)];
868 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
871 static u32 dram_attr_knl(u32 reg)
873 return GET_BITFIELD(reg, 3, 4);
877 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
882 if (pvt->pci_ddrio) {
883 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
885 if (GET_BITFIELD(reg, 11, 11))
886 /* FIXME: Can also be LRDIMM */
896 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
899 bool registered = false;
900 enum mem_type mtype = MEM_UNKNOWN;
905 pci_read_config_dword(pvt->pci_ddrio,
906 HASWELL_DDRCRCLKCONTROLS, ®);
908 if (GET_BITFIELD(reg, 16, 16))
911 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
912 if (GET_BITFIELD(reg, 14, 14)) {
928 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
930 /* for KNL value is fixed */
934 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
936 /* there's no way to figure out */
940 static enum dev_type __ibridge_get_width(u32 mtr)
942 enum dev_type type = DEV_UNKNOWN;
959 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
962 * ddr3_width on the documentation but also valid for DDR4 on
965 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
968 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
970 /* ddr3_width on the documentation but also valid for DDR4 */
971 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
974 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
976 /* DDR4 RDIMMS and LRDIMMS are supported */
980 static u8 get_node_id(struct sbridge_pvt *pvt)
983 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
984 return GET_BITFIELD(reg, 0, 2);
987 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
991 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
992 return GET_BITFIELD(reg, 0, 3);
995 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
999 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1000 return GET_BITFIELD(reg, 0, 2);
1004 * Use the reporting bank number to determine which memory
1005 * controller (also known as "ha" for "home agent"). Sandy
1006 * Bridge only has one memory controller per socket, so the
1007 * answer is always zero.
1009 static u8 sbridge_get_ha(u8 bank)
1015 * On Ivy Bridge, Haswell and Broadwell the error may be in a
1016 * home agent bank (7, 8), or one of the per-channel memory
1017 * controller banks (9 .. 16).
1019 static u8 ibridge_get_ha(u8 bank)
1025 return (bank - 9) / 4;
1031 /* Not used, but included for safety/symmetry */
1032 static u8 knl_get_ha(u8 bank)
1037 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1041 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1042 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1045 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1050 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1051 rc = GET_BITFIELD(reg, 26, 31);
1052 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1053 rc = ((reg << 6) | rc) << 26;
1055 return rc | 0x1ffffff;
1058 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1062 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
1063 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1066 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1071 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo);
1072 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi);
1073 rc = ((u64)reg_hi << 32) | reg_lo;
1074 return rc | 0x3ffffff;
1078 static u64 haswell_rir_limit(u32 reg)
1080 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
1083 static inline u8 sad_pkg_socket(u8 pkg)
1085 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1086 return ((pkg >> 3) << 2) | (pkg & 0x3);
1089 static inline u8 sad_pkg_ha(u8 pkg)
1091 return (pkg >> 2) & 0x1;
1094 static int haswell_chan_hash(int idx, u64 addr)
1099 * XOR even bits from 12:26 to bit0 of idx,
1100 * odd bits from 13:27 to bit1
1102 for (i = 12; i < 28; i += 2)
1103 idx ^= (addr >> i) & 3;
1108 /* Low bits of TAD limit, and some metadata. */
1109 static const u32 knl_tad_dram_limit_lo[] = {
1110 0x400, 0x500, 0x600, 0x700,
1111 0x800, 0x900, 0xa00, 0xb00,
1114 /* Low bits of TAD offset. */
1115 static const u32 knl_tad_dram_offset_lo[] = {
1116 0x404, 0x504, 0x604, 0x704,
1117 0x804, 0x904, 0xa04, 0xb04,
1120 /* High 16 bits of TAD limit and offset. */
1121 static const u32 knl_tad_dram_hi[] = {
1122 0x408, 0x508, 0x608, 0x708,
1123 0x808, 0x908, 0xa08, 0xb08,
1126 /* Number of ways a tad entry is interleaved. */
1127 static const u32 knl_tad_ways[] = {
1132 * Retrieve the n'th Target Address Decode table entry
1133 * from the memory controller's TAD table.
1135 * @pvt: driver private data
1136 * @entry: which entry you want to retrieve
1137 * @mc: which memory controller (0 or 1)
1138 * @offset: output tad range offset
1139 * @limit: output address of first byte above tad range
1140 * @ways: output number of interleave ways
1142 * The offset value has curious semantics. It's a sort of running total
1143 * of the sizes of all the memory regions that aren't mapped in this
1146 static int knl_get_tad(const struct sbridge_pvt *pvt,
1153 u32 reg_limit_lo, reg_offset_lo, reg_hi;
1154 struct pci_dev *pci_mc;
1159 pci_mc = pvt->knl.pci_mc0;
1162 pci_mc = pvt->knl.pci_mc1;
1169 pci_read_config_dword(pci_mc,
1170 knl_tad_dram_limit_lo[entry], ®_limit_lo);
1171 pci_read_config_dword(pci_mc,
1172 knl_tad_dram_offset_lo[entry], ®_offset_lo);
1173 pci_read_config_dword(pci_mc,
1174 knl_tad_dram_hi[entry], ®_hi);
1176 /* Is this TAD entry enabled? */
1177 if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1180 way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1182 if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1183 *ways = knl_tad_ways[way_id];
1186 sbridge_printk(KERN_ERR,
1187 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1193 * The least significant 6 bits of base and limit are truncated.
1194 * For limit, we fill the missing bits with 1s.
1196 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1197 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);
1198 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |
1199 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1204 /* Determine which memory controller is responsible for a given channel. */
1205 static int knl_channel_mc(int channel)
1207 WARN_ON(channel < 0 || channel >= 6);
1209 return channel < 3 ? 1 : 0;
1213 * Get the Nth entry from EDC_ROUTE_TABLE register.
1214 * (This is the per-tile mapping of logical interleave targets to
1215 * physical EDC modules.)
1227 static u32 knl_get_edc_route(int entry, u32 reg)
1229 WARN_ON(entry >= KNL_MAX_EDCS);
1230 return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1234 * Get the Nth entry from MC_ROUTE_TABLE register.
1235 * (This is the per-tile mapping of logical interleave targets to
1236 * physical DRAM channels modules.)
1238 * entry 0: mc 0:2 channel 18:19
1239 * 1: mc 3:5 channel 20:21
1240 * 2: mc 6:8 channel 22:23
1241 * 3: mc 9:11 channel 24:25
1242 * 4: mc 12:14 channel 26:27
1243 * 5: mc 15:17 channel 28:29
1246 * Though we have 3 bits to identify the MC, we should only see
1247 * the values 0 or 1.
1250 static u32 knl_get_mc_route(int entry, u32 reg)
1254 WARN_ON(entry >= KNL_MAX_CHANNELS);
1256 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1257 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1259 return knl_channel_remap(mc, chan);
1263 * Render the EDC_ROUTE register in human-readable form.
1264 * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1266 static void knl_show_edc_route(u32 reg, char *s)
1270 for (i = 0; i < KNL_MAX_EDCS; i++) {
1271 s[i*2] = knl_get_edc_route(i, reg) + '0';
1275 s[KNL_MAX_EDCS*2 - 1] = '\0';
1279 * Render the MC_ROUTE register in human-readable form.
1280 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1282 static void knl_show_mc_route(u32 reg, char *s)
1286 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1287 s[i*2] = knl_get_mc_route(i, reg) + '0';
1291 s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1294 #define KNL_EDC_ROUTE 0xb8
1295 #define KNL_MC_ROUTE 0xb4
1297 /* Is this dram rule backed by regular DRAM in flat mode? */
1298 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1300 /* Is this dram rule cached? */
1301 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1303 /* Is this rule backed by edc ? */
1304 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1306 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1307 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1309 /* Is this rule mod3? */
1310 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1313 * Figure out how big our RAM modules are.
1315 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1316 * have to figure this out from the SAD rules, interleave lists, route tables,
1319 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1320 * inspect the TAD rules to figure out how large the SAD regions really are.
1322 * When we know the real size of a SAD region and how many ways it's
1323 * interleaved, we know the individual contribution of each channel to
1326 * Finally, we have to check whether each channel participates in each SAD
1329 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1330 * much memory the channel uses, we know the DIMM is at least that large.
1331 * (The BIOS might possibly choose not to map all available memory, in which
1332 * case we will underreport the size of the DIMM.)
1334 * In theory, we could try to determine the EDC sizes as well, but that would
1335 * only work in flat mode, not in cache mode.
1337 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1340 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1342 u64 sad_base, sad_limit = 0;
1343 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1346 int intrlv_ways, tad_ways;
1349 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1350 u32 dram_rule, interleave_reg;
1351 u32 mc_route_reg[KNL_MAX_CHAS];
1352 u32 edc_route_reg[KNL_MAX_CHAS];
1354 char edc_route_string[KNL_MAX_EDCS*2];
1355 char mc_route_string[KNL_MAX_CHANNELS*2];
1359 int participants[KNL_MAX_CHANNELS];
1361 for (i = 0; i < KNL_MAX_CHANNELS; i++)
1364 /* Read the EDC route table in each CHA. */
1366 for (i = 0; i < KNL_MAX_CHAS; i++) {
1367 pci_read_config_dword(pvt->knl.pci_cha[i],
1368 KNL_EDC_ROUTE, &edc_route_reg[i]);
1370 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1371 knl_show_edc_route(edc_route_reg[i-1],
1373 if (cur_reg_start == i-1)
1374 edac_dbg(0, "edc route table for CHA %d: %s\n",
1375 cur_reg_start, edc_route_string);
1377 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1378 cur_reg_start, i-1, edc_route_string);
1382 knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1383 if (cur_reg_start == i-1)
1384 edac_dbg(0, "edc route table for CHA %d: %s\n",
1385 cur_reg_start, edc_route_string);
1387 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1388 cur_reg_start, i-1, edc_route_string);
1390 /* Read the MC route table in each CHA. */
1392 for (i = 0; i < KNL_MAX_CHAS; i++) {
1393 pci_read_config_dword(pvt->knl.pci_cha[i],
1394 KNL_MC_ROUTE, &mc_route_reg[i]);
1396 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1397 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1398 if (cur_reg_start == i-1)
1399 edac_dbg(0, "mc route table for CHA %d: %s\n",
1400 cur_reg_start, mc_route_string);
1402 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1403 cur_reg_start, i-1, mc_route_string);
1407 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1408 if (cur_reg_start == i-1)
1409 edac_dbg(0, "mc route table for CHA %d: %s\n",
1410 cur_reg_start, mc_route_string);
1412 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1413 cur_reg_start, i-1, mc_route_string);
1415 /* Process DRAM rules */
1416 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1417 /* previous limit becomes the new base */
1418 sad_base = sad_limit;
1420 pci_read_config_dword(pvt->pci_sad0,
1421 pvt->info.dram_rule[sad_rule], &dram_rule);
1423 if (!DRAM_RULE_ENABLE(dram_rule))
1426 edram_only = KNL_EDRAM_ONLY(dram_rule);
1428 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1430 pci_read_config_dword(pvt->pci_sad0,
1431 pvt->info.interleave_list[sad_rule], &interleave_reg);
1434 * Find out how many ways this dram rule is interleaved.
1435 * We stop when we see the first channel again.
1437 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1439 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1440 pkg = sad_pkg(pvt->info.interleave_pkg,
1441 interleave_reg, intrlv_ways);
1443 if ((pkg & 0x8) == 0) {
1445 * 0 bit means memory is non-local,
1446 * which KNL doesn't support
1448 edac_dbg(0, "Unexpected interleave target %d\n",
1453 if (pkg == first_pkg)
1456 if (KNL_MOD3(dram_rule))
1459 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1464 edram_only ? ", EDRAM" : "");
1467 * Find out how big the SAD region really is by iterating
1468 * over TAD tables (SAD regions may contain holes).
1469 * Each memory controller might have a different TAD table, so
1470 * we have to look at both.
1472 * Livespace is the memory that's mapped in this TAD table,
1473 * deadspace is the holes (this could be the MMIO hole, or it
1474 * could be memory that's mapped by the other TAD table but
1477 for (mc = 0; mc < 2; mc++) {
1478 sad_actual_size[mc] = 0;
1481 tad_rule < ARRAY_SIZE(
1482 knl_tad_dram_limit_lo);
1484 if (knl_get_tad(pvt,
1492 tad_size = (tad_limit+1) -
1493 (tad_livespace + tad_deadspace);
1494 tad_livespace += tad_size;
1495 tad_base = (tad_limit+1) - tad_size;
1497 if (tad_base < sad_base) {
1498 if (tad_limit > sad_base)
1499 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1500 } else if (tad_base < sad_limit) {
1501 if (tad_limit+1 > sad_limit) {
1502 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1504 /* TAD region is completely inside SAD region */
1505 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1507 tad_limit, tad_size,
1509 sad_actual_size[mc] += tad_size;
1515 for (mc = 0; mc < 2; mc++) {
1516 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1517 mc, sad_actual_size[mc], sad_actual_size[mc]);
1520 /* Ignore EDRAM rule */
1524 /* Figure out which channels participate in interleave. */
1525 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1526 participants[channel] = 0;
1528 /* For each channel, does at least one CHA have
1529 * this channel mapped to the given target?
1531 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1535 for (target = 0; target < KNL_MAX_CHANNELS; target++) {
1536 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1537 if (knl_get_mc_route(target,
1538 mc_route_reg[cha]) == channel
1539 && !participants[channel]) {
1540 participants[channel] = 1;
1547 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1548 mc = knl_channel_mc(channel);
1549 if (participants[channel]) {
1550 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1552 sad_actual_size[mc]/intrlv_ways,
1554 mc_sizes[channel] +=
1555 sad_actual_size[mc]/intrlv_ways;
1563 static void get_source_id(struct mem_ctl_info *mci)
1565 struct sbridge_pvt *pvt = mci->pvt_info;
1568 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1569 pvt->info.type == KNIGHTS_LANDING)
1570 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
1572 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
1574 if (pvt->info.type == KNIGHTS_LANDING)
1575 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1577 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1580 static int __populate_dimms(struct mem_ctl_info *mci,
1581 u64 knl_mc_sizes[KNL_MAX_CHANNELS],
1582 enum edac_type mode)
1584 struct sbridge_pvt *pvt = mci->pvt_info;
1585 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1587 unsigned int i, j, banks, ranks, rows, cols, npages;
1588 struct dimm_info *dimm;
1589 enum mem_type mtype;
1592 mtype = pvt->info.get_memory_type(pvt);
1593 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1594 edac_dbg(0, "Memory is registered\n");
1595 else if (mtype == MEM_UNKNOWN)
1596 edac_dbg(0, "Cannot determine memory type\n");
1598 edac_dbg(0, "Memory is unregistered\n");
1600 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1605 for (i = 0; i < channels; i++) {
1608 int max_dimms_per_channel;
1610 if (pvt->info.type == KNIGHTS_LANDING) {
1611 max_dimms_per_channel = 1;
1612 if (!pvt->knl.pci_channel[i])
1615 max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1616 if (!pvt->pci_tad[i])
1620 for (j = 0; j < max_dimms_per_channel; j++) {
1621 dimm = edac_get_dimm(mci, i, j, 0);
1622 if (pvt->info.type == KNIGHTS_LANDING) {
1623 pci_read_config_dword(pvt->knl.pci_channel[i],
1626 pci_read_config_dword(pvt->pci_tad[i],
1629 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
1630 if (IS_DIMM_PRESENT(mtr)) {
1631 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1632 sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
1633 pvt->sbridge_dev->source_id,
1634 pvt->sbridge_dev->dom, i);
1637 pvt->channel[i].dimms++;
1639 ranks = numrank(pvt->info.type, mtr);
1641 if (pvt->info.type == KNIGHTS_LANDING) {
1642 /* For DDR4, this is fixed. */
1644 rows = knl_mc_sizes[i] /
1645 ((u64) cols * ranks * banks * 8);
1651 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1652 npages = MiB_TO_PAGES(size);
1654 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1655 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1657 banks, ranks, rows, cols);
1659 dimm->nr_pages = npages;
1661 dimm->dtype = pvt->info.get_width(pvt, mtr);
1662 dimm->mtype = mtype;
1663 dimm->edac_mode = mode;
1664 snprintf(dimm->label, sizeof(dimm->label),
1665 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1666 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1674 static int get_dimm_config(struct mem_ctl_info *mci)
1676 struct sbridge_pvt *pvt = mci->pvt_info;
1677 u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1678 enum edac_type mode;
1681 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1682 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1683 pvt->sbridge_dev->mc,
1684 pvt->sbridge_dev->node_id,
1685 pvt->sbridge_dev->source_id);
1687 /* KNL doesn't support mirroring or lockstep,
1688 * and is always closed page
1690 if (pvt->info.type == KNIGHTS_LANDING) {
1691 mode = EDAC_S4ECD4ED;
1692 pvt->mirror_mode = NON_MIRRORING;
1693 pvt->is_cur_addr_mirrored = false;
1695 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1697 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1698 edac_dbg(0, "Failed to read KNL_MCMTR register\n");
1702 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1703 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
1704 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n");
1707 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1708 if (GET_BITFIELD(reg, 28, 28)) {
1709 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1710 edac_dbg(0, "Address range partial memory mirroring is enabled\n");
1714 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
1715 edac_dbg(0, "Failed to read RASENABLES register\n");
1718 if (IS_MIRROR_ENABLED(reg)) {
1719 pvt->mirror_mode = FULL_MIRRORING;
1720 edac_dbg(0, "Full memory mirroring is enabled\n");
1722 pvt->mirror_mode = NON_MIRRORING;
1723 edac_dbg(0, "Memory mirroring is disabled\n");
1727 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1728 edac_dbg(0, "Failed to read MCMTR register\n");
1731 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1732 edac_dbg(0, "Lockstep is enabled\n");
1733 mode = EDAC_S8ECD8ED;
1734 pvt->is_lockstep = true;
1736 edac_dbg(0, "Lockstep is disabled\n");
1737 mode = EDAC_S4ECD4ED;
1738 pvt->is_lockstep = false;
1740 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1741 edac_dbg(0, "address map is on closed page mode\n");
1742 pvt->is_close_pg = true;
1744 edac_dbg(0, "address map is on open page mode\n");
1745 pvt->is_close_pg = false;
1749 return __populate_dimms(mci, knl_mc_sizes, mode);
1752 static void get_memory_layout(const struct mem_ctl_info *mci)
1754 struct sbridge_pvt *pvt = mci->pvt_info;
1755 int i, j, k, n_sads, n_tads, sad_interl;
1763 * Step 1) Get TOLM/TOHM ranges
1766 pvt->tolm = pvt->info.get_tolm(pvt);
1767 tmp_mb = (1 + pvt->tolm) >> 20;
1769 gb = div_u64_rem(tmp_mb, 1024, &mb);
1770 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1771 gb, (mb*1000)/1024, (u64)pvt->tolm);
1773 /* Address range is already 45:25 */
1774 pvt->tohm = pvt->info.get_tohm(pvt);
1775 tmp_mb = (1 + pvt->tohm) >> 20;
1777 gb = div_u64_rem(tmp_mb, 1024, &mb);
1778 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1779 gb, (mb*1000)/1024, (u64)pvt->tohm);
1782 * Step 2) Get SAD range and SAD Interleave list
1783 * TAD registers contain the interleave wayness. However, it
1784 * seems simpler to just discover it indirectly, with the
1788 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1789 /* SAD_LIMIT Address range is 45:26 */
1790 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1792 limit = pvt->info.sad_limit(reg);
1794 if (!DRAM_RULE_ENABLE(reg))
1800 tmp_mb = (limit + 1) >> 20;
1801 gb = div_u64_rem(tmp_mb, 1024, &mb);
1802 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1804 show_dram_attr(pvt->info.dram_attr(reg)),
1806 ((u64)tmp_mb) << 20L,
1807 get_intlv_mode_str(reg, pvt->info.type),
1811 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1813 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1814 for (j = 0; j < 8; j++) {
1815 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1816 if (j > 0 && sad_interl == pkg)
1819 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1824 if (pvt->info.type == KNIGHTS_LANDING)
1828 * Step 3) Get TAD range
1831 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1832 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
1833 limit = TAD_LIMIT(reg);
1836 tmp_mb = (limit + 1) >> 20;
1838 gb = div_u64_rem(tmp_mb, 1024, &mb);
1839 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1840 n_tads, gb, (mb*1000)/1024,
1841 ((u64)tmp_mb) << 20L,
1842 (u32)(1 << TAD_SOCK(reg)),
1843 (u32)TAD_CH(reg) + 1,
1853 * Step 4) Get TAD offsets, per each channel
1855 for (i = 0; i < NUM_CHANNELS; i++) {
1856 if (!pvt->channel[i].dimms)
1858 for (j = 0; j < n_tads; j++) {
1859 pci_read_config_dword(pvt->pci_tad[i],
1860 tad_ch_nilv_offset[j],
1862 tmp_mb = TAD_OFFSET(reg) >> 20;
1863 gb = div_u64_rem(tmp_mb, 1024, &mb);
1864 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1867 ((u64)tmp_mb) << 20L,
1873 * Step 6) Get RIR Wayness/Limit, per each channel
1875 for (i = 0; i < NUM_CHANNELS; i++) {
1876 if (!pvt->channel[i].dimms)
1878 for (j = 0; j < MAX_RIR_RANGES; j++) {
1879 pci_read_config_dword(pvt->pci_tad[i],
1883 if (!IS_RIR_VALID(reg))
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1887 rir_way = 1 << RIR_WAY(reg);
1888 gb = div_u64_rem(tmp_mb, 1024, &mb);
1889 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1892 ((u64)tmp_mb) << 20L,
1896 for (k = 0; k < rir_way; k++) {
1897 pci_read_config_dword(pvt->pci_tad[i],
1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1902 gb = div_u64_rem(tmp_mb, 1024, &mb);
1903 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1906 ((u64)tmp_mb) << 20L,
1907 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1914 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
1916 struct sbridge_dev *sbridge_dev;
1918 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1919 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)
1920 return sbridge_dev->mci;
1925 static int get_memory_error_data(struct mem_ctl_info *mci,
1930 char **area_type, char *msg)
1932 struct mem_ctl_info *new_mci;
1933 struct sbridge_pvt *pvt = mci->pvt_info;
1934 struct pci_dev *pci_ha;
1935 int n_rir, n_sads, n_tads, sad_way, sck_xch;
1936 int sad_interl, idx, base_ch;
1937 int interleave_mode, shiftup = 0;
1938 unsigned int sad_interleave[MAX_INTERLEAVE];
1940 u8 ch_way, sck_way, pkg, sad_ha = 0;
1944 u64 ch_addr, offset, limit = 0, prv = 0;
1948 * Step 0) Check if the address is at special memory ranges
1949 * The check bellow is probably enough to fill all cases where
1950 * the error is not inside a memory, except for the legacy
1951 * range (e. g. VGA addresses). It is unlikely, however, that the
1952 * memory controller would generate an error on that range.
1954 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1955 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1958 if (addr >= (u64)pvt->tohm) {
1959 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1964 * Step 1) Get socket
1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1970 if (!DRAM_RULE_ENABLE(reg))
1973 limit = pvt->info.sad_limit(reg);
1975 sprintf(msg, "Can't discover the memory socket");
1982 if (n_sads == pvt->info.max_sad) {
1983 sprintf(msg, "Can't discover the memory socket");
1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 interleave_mode = pvt->info.interleave_mode(dram_rule);
1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1993 if (pvt->info.type == SANDY_BRIDGE) {
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1995 for (sad_way = 0; sad_way < 8; sad_way++) {
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1997 if (sad_way > 0 && sad_interl == pkg)
1999 sad_interleave[sad_way] = pkg;
2000 edac_dbg(0, "SAD interleave #%d: %d\n",
2001 sad_way, sad_interleave[sad_way]);
2003 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2004 pvt->sbridge_dev->mc,
2009 !interleave_mode ? "" : "XOR[18:16]");
2010 if (interleave_mode)
2011 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2013 idx = (addr >> 6) & 7;
2027 sprintf(msg, "Can't discover socket interleave");
2030 *socket = sad_interleave[idx];
2031 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2032 idx, sad_way, *socket);
2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2034 int bits, a7mode = A7MODE(dram_rule);
2037 /* A7 mode swaps P9 with P6 */
2038 bits = GET_BITFIELD(addr, 7, 8) << 1;
2039 bits |= GET_BITFIELD(addr, 9, 9);
2041 bits = GET_BITFIELD(addr, 6, 8);
2043 if (interleave_mode == 0) {
2044 /* interleave mode will XOR {8,7,6} with {18,17,16} */
2045 idx = GET_BITFIELD(addr, 16, 18);
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2051 *socket = sad_pkg_socket(pkg);
2052 sad_ha = sad_pkg_ha(pkg);
2055 /* MCChanShiftUpEnable */
2056 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
2057 shiftup = GET_BITFIELD(reg, 22, 22);
2060 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2061 idx, *socket, sad_ha, shiftup);
2063 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2064 idx = (addr >> 6) & 7;
2065 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2066 *socket = sad_pkg_socket(pkg);
2067 sad_ha = sad_pkg_ha(pkg);
2068 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2069 idx, *socket, sad_ha);
2075 * Move to the proper node structure, in order to access the
2076 * right PCI registers
2078 new_mci = get_mci_for_node_id(*socket, sad_ha);
2080 sprintf(msg, "Struct for socket #%u wasn't initialized",
2085 pvt = mci->pvt_info;
2088 * Step 2) Get memory channel
2091 pci_ha = pvt->pci_ha;
2092 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2093 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
2094 limit = TAD_LIMIT(reg);
2096 sprintf(msg, "Can't discover the memory channel");
2103 if (n_tads == MAX_TAD) {
2104 sprintf(msg, "Can't discover the memory channel");
2108 ch_way = TAD_CH(reg) + 1;
2109 sck_way = TAD_SOCK(reg);
2114 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2115 if (pvt->is_chan_hash)
2116 idx = haswell_chan_hash(idx, addr);
2121 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2125 base_ch = TAD_TGT0(reg);
2128 base_ch = TAD_TGT1(reg);
2131 base_ch = TAD_TGT2(reg);
2134 base_ch = TAD_TGT3(reg);
2137 sprintf(msg, "Can't discover the TAD target");
2140 *channel_mask = 1 << base_ch;
2142 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2144 if (pvt->mirror_mode == FULL_MIRRORING ||
2145 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2146 *channel_mask |= 1 << ((base_ch + 2) % 4);
2150 sck_xch = (1 << sck_way) * (ch_way >> 1);
2153 sprintf(msg, "Invalid mirror set. Can't decode addr");
2157 pvt->is_cur_addr_mirrored = true;
2159 sck_xch = (1 << sck_way) * ch_way;
2160 pvt->is_cur_addr_mirrored = false;
2163 if (pvt->is_lockstep)
2164 *channel_mask |= 1 << ((base_ch + 1) % 4);
2166 offset = TAD_OFFSET(tad_offset);
2168 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2179 /* Calculate channel address */
2180 /* Remove the TAD offset */
2182 if (offset > addr) {
2183 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2188 ch_addr = addr - offset;
2189 ch_addr >>= (6 + shiftup);
2191 ch_addr <<= (6 + shiftup);
2192 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2195 * Step 3) Decode rank
2197 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2198 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
2200 if (!IS_RIR_VALID(reg))
2203 limit = pvt->info.rir_limit(reg);
2204 gb = div_u64_rem(limit >> 20, 1024, &mb);
2205 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2210 if (ch_addr <= limit)
2213 if (n_rir == MAX_RIR_RANGES) {
2214 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2218 rir_way = RIR_WAY(reg);
2220 if (pvt->is_close_pg)
2221 idx = (ch_addr >> 6);
2223 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
2224 idx %= 1 << rir_way;
2226 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
2227 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2229 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2239 static int get_memory_error_data_from_mce(struct mem_ctl_info *mci,
2240 const struct mce *m, u8 *socket,
2241 u8 *ha, long *channel_mask,
2244 u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2245 struct mem_ctl_info *new_mci;
2246 struct sbridge_pvt *pvt;
2247 struct pci_dev *pci_ha;
2250 if (channel >= NUM_CHANNELS) {
2251 sprintf(msg, "Invalid channel 0x%x", channel);
2255 pvt = mci->pvt_info;
2256 if (!pvt->info.get_ha) {
2257 sprintf(msg, "No get_ha()");
2260 *ha = pvt->info.get_ha(m->bank);
2261 if (*ha != 0 && *ha != 1) {
2262 sprintf(msg, "Impossible bank %d", m->bank);
2266 *socket = m->socketid;
2267 new_mci = get_mci_for_node_id(*socket, *ha);
2269 strcpy(msg, "mci socket got corrupted!");
2273 pvt = new_mci->pvt_info;
2274 pci_ha = pvt->pci_ha;
2275 pci_read_config_dword(pci_ha, tad_dram_rule[0], ®);
2276 tad0 = m->addr <= TAD_LIMIT(reg);
2278 *channel_mask = 1 << channel;
2279 if (pvt->mirror_mode == FULL_MIRRORING ||
2280 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
2281 *channel_mask |= 1 << ((channel + 2) % 4);
2282 pvt->is_cur_addr_mirrored = true;
2284 pvt->is_cur_addr_mirrored = false;
2287 if (pvt->is_lockstep)
2288 *channel_mask |= 1 << ((channel + 1) % 4);
2293 /****************************************************************************
2294 Device initialization routines: put/get, init/exit
2295 ****************************************************************************/
2298 * sbridge_put_all_devices 'put' all the devices that we have
2299 * reserved via 'get'
2301 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2306 for (i = 0; i < sbridge_dev->n_devs; i++) {
2307 struct pci_dev *pdev = sbridge_dev->pdev[i];
2310 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2312 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2317 static void sbridge_put_all_devices(void)
2319 struct sbridge_dev *sbridge_dev, *tmp;
2321 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2322 sbridge_put_devices(sbridge_dev);
2323 free_sbridge_dev(sbridge_dev);
2327 static int sbridge_get_onedevice(struct pci_dev **prev,
2329 const struct pci_id_table *table,
2330 const unsigned devno,
2331 const int multi_bus)
2333 struct sbridge_dev *sbridge_dev = NULL;
2334 const struct pci_id_descr *dev_descr = &table->descr[devno];
2335 struct pci_dev *pdev = NULL;
2340 sbridge_printk(KERN_DEBUG,
2341 "Seeking for: PCI ID %04x:%04x\n",
2342 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2344 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2345 dev_descr->dev_id, *prev);
2353 if (dev_descr->optional)
2356 /* if the HA wasn't found */
2360 sbridge_printk(KERN_INFO,
2361 "Device not found: %04x:%04x\n",
2362 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2364 /* End of list, leave */
2367 seg = pci_domain_nr(pdev->bus);
2368 bus = pdev->bus->number;
2371 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom,
2372 multi_bus, sbridge_dev);
2374 /* If the HA1 wasn't found, don't create EDAC second memory controller */
2375 if (dev_descr->dom == IMC1 && devno != 1) {
2376 edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
2377 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2382 if (dev_descr->dom == SOCK)
2385 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table);
2393 if (sbridge_dev->pdev[sbridge_dev->i_devs]) {
2394 sbridge_printk(KERN_ERR,
2395 "Duplicated device for %04x:%04x\n",
2396 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2401 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev;
2403 /* pdev belongs to more than one IMC, do extra gets */
2407 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)
2411 /* Be sure that the device is enabled */
2412 if (unlikely(pci_enable_device(pdev) < 0)) {
2413 sbridge_printk(KERN_ERR,
2414 "Couldn't enable %04x:%04x\n",
2415 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2419 edac_dbg(0, "Detected %04x:%04x\n",
2420 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2423 * As stated on drivers/pci/search.c, the reference count for
2424 * @from is always decremented if it is not %NULL. So, as we need
2425 * to get all devices up to null, we need to do a get for the device
2435 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2436 * devices we want to reference for this driver.
2437 * @num_mc: pointer to the memory controllers count, to be incremented in case
2439 * @table: model specific table
2441 * returns 0 in case of success or error code
2443 static int sbridge_get_all_devices(u8 *num_mc,
2444 const struct pci_id_table *table)
2447 struct pci_dev *pdev = NULL;
2451 if (table->type == KNIGHTS_LANDING)
2452 allow_dups = multi_bus = 1;
2453 while (table && table->descr) {
2454 for (i = 0; i < table->n_devs_per_sock; i++) {
2455 if (!allow_dups || i == 0 ||
2456 table->descr[i].dev_id !=
2457 table->descr[i-1].dev_id) {
2461 rc = sbridge_get_onedevice(&pdev, num_mc,
2462 table, i, multi_bus);
2465 i = table->n_devs_per_sock;
2468 sbridge_put_all_devices();
2471 } while (pdev && !allow_dups);
2480 * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in
2481 * the format: XXXa. So we can convert from a device to the corresponding
2484 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2486 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2487 struct sbridge_dev *sbridge_dev)
2489 struct sbridge_pvt *pvt = mci->pvt_info;
2490 struct pci_dev *pdev;
2491 u8 saw_chan_mask = 0;
2494 for (i = 0; i < sbridge_dev->n_devs; i++) {
2495 pdev = sbridge_dev->pdev[i];
2499 switch (pdev->device) {
2500 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2501 pvt->pci_sad0 = pdev;
2503 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2504 pvt->pci_sad1 = pdev;
2506 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2507 pvt->pci_br0 = pdev;
2509 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2512 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2515 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2516 pvt->pci_ras = pdev;
2518 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2519 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2520 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2521 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2523 int id = TAD_DEV_TO_CHAN(pdev->device);
2524 pvt->pci_tad[id] = pdev;
2525 saw_chan_mask |= 1 << id;
2528 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2529 pvt->pci_ddrio = pdev;
2535 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2536 pdev->vendor, pdev->device,
2541 /* Check if everything were registered */
2542 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2543 !pvt->pci_ras || !pvt->pci_ta)
2546 if (saw_chan_mask != 0x0f)
2551 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2555 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2556 PCI_VENDOR_ID_INTEL, pdev->device);
2560 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2561 struct sbridge_dev *sbridge_dev)
2563 struct sbridge_pvt *pvt = mci->pvt_info;
2564 struct pci_dev *pdev;
2565 u8 saw_chan_mask = 0;
2568 for (i = 0; i < sbridge_dev->n_devs; i++) {
2569 pdev = sbridge_dev->pdev[i];
2573 switch (pdev->device) {
2574 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2575 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2578 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2579 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
2582 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2583 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
2584 pvt->pci_ras = pdev;
2586 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2587 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2588 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2589 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2590 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2591 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2592 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2593 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2595 int id = TAD_DEV_TO_CHAN(pdev->device);
2596 pvt->pci_tad[id] = pdev;
2597 saw_chan_mask |= 1 << id;
2600 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2601 pvt->pci_ddrio = pdev;
2603 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2604 pvt->pci_ddrio = pdev;
2606 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2607 pvt->pci_sad0 = pdev;
2609 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2610 pvt->pci_br0 = pdev;
2612 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2613 pvt->pci_br1 = pdev;
2619 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2621 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2625 /* Check if everything were registered */
2626 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2627 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2630 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2631 saw_chan_mask != 0x03) /* -EP */
2636 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2640 sbridge_printk(KERN_ERR,
2641 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2646 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2647 struct sbridge_dev *sbridge_dev)
2649 struct sbridge_pvt *pvt = mci->pvt_info;
2650 struct pci_dev *pdev;
2651 u8 saw_chan_mask = 0;
2654 /* there's only one device per system; not tied to any bus */
2655 if (pvt->info.pci_vtd == NULL)
2656 /* result will be checked later */
2657 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2658 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2661 for (i = 0; i < sbridge_dev->n_devs; i++) {
2662 pdev = sbridge_dev->pdev[i];
2666 switch (pdev->device) {
2667 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2668 pvt->pci_sad0 = pdev;
2670 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2671 pvt->pci_sad1 = pdev;
2673 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2674 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2677 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2678 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2681 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
2682 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:
2683 pvt->pci_ras = pdev;
2685 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2686 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2687 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2688 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2689 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2690 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2691 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2692 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2694 int id = TAD_DEV_TO_CHAN(pdev->device);
2695 pvt->pci_tad[id] = pdev;
2696 saw_chan_mask |= 1 << id;
2699 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2700 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2701 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2702 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2703 if (!pvt->pci_ddrio)
2704 pvt->pci_ddrio = pdev;
2710 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2712 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2716 /* Check if everything were registered */
2717 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2718 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2721 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2722 saw_chan_mask != 0x03) /* -EP */
2727 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2731 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2732 struct sbridge_dev *sbridge_dev)
2734 struct sbridge_pvt *pvt = mci->pvt_info;
2735 struct pci_dev *pdev;
2736 u8 saw_chan_mask = 0;
2739 /* there's only one device per system; not tied to any bus */
2740 if (pvt->info.pci_vtd == NULL)
2741 /* result will be checked later */
2742 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2743 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2746 for (i = 0; i < sbridge_dev->n_devs; i++) {
2747 pdev = sbridge_dev->pdev[i];
2751 switch (pdev->device) {
2752 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2753 pvt->pci_sad0 = pdev;
2755 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2756 pvt->pci_sad1 = pdev;
2758 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2759 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2762 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2763 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2766 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
2767 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:
2768 pvt->pci_ras = pdev;
2770 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2771 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2772 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2773 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2774 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2775 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2776 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2777 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2779 int id = TAD_DEV_TO_CHAN(pdev->device);
2780 pvt->pci_tad[id] = pdev;
2781 saw_chan_mask |= 1 << id;
2784 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2785 pvt->pci_ddrio = pdev;
2791 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2793 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2797 /* Check if everything were registered */
2798 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2799 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2802 if (saw_chan_mask != 0x0f && /* -EN/-EX */
2803 saw_chan_mask != 0x03) /* -EP */
2808 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2812 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2813 struct sbridge_dev *sbridge_dev)
2815 struct sbridge_pvt *pvt = mci->pvt_info;
2816 struct pci_dev *pdev;
2822 for (i = 0; i < sbridge_dev->n_devs; i++) {
2823 pdev = sbridge_dev->pdev[i];
2827 /* Extract PCI device and function. */
2828 dev = (pdev->devfn >> 3) & 0x1f;
2829 func = pdev->devfn & 0x7;
2831 switch (pdev->device) {
2832 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2834 pvt->knl.pci_mc0 = pdev;
2836 pvt->knl.pci_mc1 = pdev;
2838 sbridge_printk(KERN_ERR,
2839 "Memory controller in unexpected place! (dev %d, fn %d)\n",
2845 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2846 pvt->pci_sad0 = pdev;
2849 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2850 pvt->pci_sad1 = pdev;
2853 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2854 /* There are one of these per tile, and range from
2857 devidx = ((dev-14)*8)+func;
2859 if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2860 sbridge_printk(KERN_ERR,
2861 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2866 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2868 pvt->knl.pci_cha[devidx] = pdev;
2871 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
2875 * MC0 channels 0-2 are device 9 function 2-4,
2876 * MC1 channels 3-5 are device 8 function 2-4.
2882 devidx = 3 + (func-2);
2884 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2885 sbridge_printk(KERN_ERR,
2886 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2891 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2892 pvt->knl.pci_channel[devidx] = pdev;
2895 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2896 pvt->knl.pci_mc_info = pdev;
2899 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2904 sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2910 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
2911 !pvt->pci_sad0 || !pvt->pci_sad1 ||
2916 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2917 if (!pvt->knl.pci_channel[i]) {
2918 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2923 for (i = 0; i < KNL_MAX_CHAS; i++) {
2924 if (!pvt->knl.pci_cha[i]) {
2925 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2933 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2937 /****************************************************************************
2938 Error check routines
2939 ****************************************************************************/
2942 * While Sandy Bridge has error count registers, SMI BIOS read values from
2943 * and resets the counters. So, they are not reliable for the OS to read
2944 * from them. So, we have no option but to just trust on whatever MCE is
2945 * telling us about the errors.
2947 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2948 const struct mce *m)
2950 struct mem_ctl_info *new_mci;
2951 struct sbridge_pvt *pvt = mci->pvt_info;
2952 enum hw_event_mc_err_type tp_event;
2953 char *optype, msg[256];
2954 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2955 bool overflow = GET_BITFIELD(m->status, 62, 62);
2956 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2958 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2959 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2960 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2961 u32 channel = GET_BITFIELD(m->status, 0, 3);
2962 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2964 * Bits 5-0 of MCi_MISC give the least significant bit that is valid.
2965 * A value 6 is for cache line aligned address, a value 12 is for page
2966 * aligned address reported by patrol scrubber.
2968 u32 lsb = GET_BITFIELD(m->misc, 0, 5);
2969 long channel_mask, first_channel;
2970 u8 rank = 0xff, socket, ha;
2972 char *area_type = "DRAM";
2974 if (pvt->info.type != SANDY_BRIDGE)
2977 recoverable = GET_BITFIELD(m->status, 56, 56);
2979 if (uncorrected_error) {
2982 tp_event = HW_EVENT_ERR_UNCORRECTED;
2984 tp_event = HW_EVENT_ERR_FATAL;
2987 tp_event = HW_EVENT_ERR_CORRECTED;
2991 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2992 * memory errors should fit in this mask:
2993 * 000f 0000 1mmm cccc (binary)
2995 * f = Correction Report Filtering Bit. If 1, subsequent errors
2999 * If the mask doesn't match, report an error to the parsing logic
3001 switch (optypenum) {
3003 optype = "generic undef request error";
3006 optype = "memory read error";
3009 optype = "memory write error";
3012 optype = "addr/cmd error";
3015 optype = "memory scrubbing error";
3018 optype = "reserved";
3022 if (pvt->info.type == KNIGHTS_LANDING) {
3023 if (channel == 14) {
3024 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
3025 overflow ? " OVERFLOW" : "",
3026 (uncorrected_error && recoverable)
3027 ? " recoverable" : "",
3034 * Reported channel is in range 0-2, so we can't map it
3035 * back to mc. To figure out mc we check machine check
3036 * bank register that reported this error.
3037 * bank15 means mc0 and bank16 means mc1.
3039 channel = knl_channel_remap(m->bank == 16, channel);
3040 channel_mask = 1 << channel;
3042 snprintf(msg, sizeof(msg),
3043 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3044 overflow ? " OVERFLOW" : "",
3045 (uncorrected_error && recoverable)
3046 ? " recoverable" : " ",
3047 mscod, errcode, channel, A + channel);
3048 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3049 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3054 } else if (lsb < 12) {
3055 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3056 &channel_mask, &rank,
3059 rc = get_memory_error_data_from_mce(mci, m, &socket, &ha,
3060 &channel_mask, msg);
3065 new_mci = get_mci_for_node_id(socket, ha);
3067 strcpy(msg, "Error: socket got corrupted!");
3071 pvt = mci->pvt_info;
3073 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3085 * FIXME: On some memory configurations (mirror, lockstep), the
3086 * Memory Controller can't point the error to a single DIMM. The
3087 * EDAC core should be handling the channel mask, in order to point
3088 * to the group of dimm's where the error may be happening.
3090 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
3091 channel = first_channel;
3093 snprintf(msg, sizeof(msg),
3094 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3095 overflow ? " OVERFLOW" : "",
3096 (uncorrected_error && recoverable) ? " recoverable" : "",
3103 edac_dbg(0, "%s\n", msg);
3105 /* FIXME: need support for channel mask */
3107 if (channel == CHANNEL_UNSPECIFIED)
3110 /* Call the helper to output message */
3111 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3112 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3117 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3124 * Check that logging is enabled and that this is the right type
3125 * of error for us to handle.
3127 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3130 struct mce *mce = (struct mce *)data;
3131 struct mem_ctl_info *mci;
3134 if (mce->kflags & MCE_HANDLED_CEC)
3138 * Just let mcelog handle it if the error is
3139 * outside the memory controller. A memory error
3140 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3141 * bit 12 has an special meaning.
3143 if ((mce->status & 0xefff) >> 7 != 1)
3146 /* Check ADDRV bit in STATUS */
3147 if (!GET_BITFIELD(mce->status, 58, 58))
3150 /* Check MISCV bit in STATUS */
3151 if (!GET_BITFIELD(mce->status, 59, 59))
3154 /* Check address type in MISC (physical address only) */
3155 if (GET_BITFIELD(mce->misc, 6, 8) != 2)
3158 mci = get_mci_for_node_id(mce->socketid, IMC0);
3162 if (mce->mcgstatus & MCG_STATUS_MCIP)
3167 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3169 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3170 "Bank %d: %016Lx\n", mce->extcpu, type,
3171 mce->mcgstatus, mce->bank, mce->status);
3172 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3173 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3174 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3176 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3177 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3178 mce->time, mce->socketid, mce->apicid);
3180 sbridge_mce_output_error(mci, mce);
3182 /* Advice mcelog that the error were handled */
3183 mce->kflags |= MCE_HANDLED_EDAC;
3187 static struct notifier_block sbridge_mce_dec = {
3188 .notifier_call = sbridge_mce_check_error,
3189 .priority = MCE_PRIO_EDAC,
3192 /****************************************************************************
3193 EDAC register/unregister logic
3194 ****************************************************************************/
3196 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3198 struct mem_ctl_info *mci = sbridge_dev->mci;
3200 if (unlikely(!mci || !mci->pvt_info)) {
3201 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3203 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3207 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3208 mci, &sbridge_dev->pdev[0]->dev);
3210 /* Remove MC sysfs nodes */
3211 edac_mc_del_mc(mci->pdev);
3213 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3214 kfree(mci->ctl_name);
3216 sbridge_dev->mci = NULL;
3219 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3221 struct mem_ctl_info *mci;
3222 struct edac_mc_layer layers[2];
3223 struct sbridge_pvt *pvt;
3224 struct pci_dev *pdev = sbridge_dev->pdev[0];
3227 /* allocate a new MC control structure */
3228 layers[0].type = EDAC_MC_LAYER_CHANNEL;
3229 layers[0].size = type == KNIGHTS_LANDING ?
3230 KNL_MAX_CHANNELS : NUM_CHANNELS;
3231 layers[0].is_virt_csrow = false;
3232 layers[1].type = EDAC_MC_LAYER_SLOT;
3233 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3234 layers[1].is_virt_csrow = true;
3235 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3241 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3244 pvt = mci->pvt_info;
3245 memset(pvt, 0, sizeof(*pvt));
3247 /* Associate sbridge_dev and mci for future usage */
3248 pvt->sbridge_dev = sbridge_dev;
3249 sbridge_dev->mci = mci;
3251 mci->mtype_cap = type == KNIGHTS_LANDING ?
3252 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3253 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3254 mci->edac_cap = EDAC_FLAG_NONE;
3255 mci->mod_name = EDAC_MOD_STR;
3256 mci->dev_name = pci_name(pdev);
3257 mci->ctl_page_to_phys = NULL;
3259 pvt->info.type = type;
3262 pvt->info.rankcfgr = IB_RANK_CFG_A;
3263 pvt->info.get_tolm = ibridge_get_tolm;
3264 pvt->info.get_tohm = ibridge_get_tohm;
3265 pvt->info.dram_rule = ibridge_dram_rule;
3266 pvt->info.get_memory_type = get_memory_type;
3267 pvt->info.get_node_id = get_node_id;
3268 pvt->info.get_ha = ibridge_get_ha;
3269 pvt->info.rir_limit = rir_limit;
3270 pvt->info.sad_limit = sad_limit;
3271 pvt->info.interleave_mode = interleave_mode;
3272 pvt->info.dram_attr = dram_attr;
3273 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3274 pvt->info.interleave_list = ibridge_interleave_list;
3275 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3276 pvt->info.get_width = ibridge_get_width;
3278 /* Store pci devices at mci for faster access */
3279 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3280 if (unlikely(rc < 0))
3283 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d",
3284 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3287 pvt->info.rankcfgr = SB_RANK_CFG_A;
3288 pvt->info.get_tolm = sbridge_get_tolm;
3289 pvt->info.get_tohm = sbridge_get_tohm;
3290 pvt->info.dram_rule = sbridge_dram_rule;
3291 pvt->info.get_memory_type = get_memory_type;
3292 pvt->info.get_node_id = get_node_id;
3293 pvt->info.get_ha = sbridge_get_ha;
3294 pvt->info.rir_limit = rir_limit;
3295 pvt->info.sad_limit = sad_limit;
3296 pvt->info.interleave_mode = interleave_mode;
3297 pvt->info.dram_attr = dram_attr;
3298 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3299 pvt->info.interleave_list = sbridge_interleave_list;
3300 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3301 pvt->info.get_width = sbridge_get_width;
3303 /* Store pci devices at mci for faster access */
3304 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3305 if (unlikely(rc < 0))
3308 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d",
3309 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3312 /* rankcfgr isn't used */
3313 pvt->info.get_tolm = haswell_get_tolm;
3314 pvt->info.get_tohm = haswell_get_tohm;
3315 pvt->info.dram_rule = ibridge_dram_rule;
3316 pvt->info.get_memory_type = haswell_get_memory_type;
3317 pvt->info.get_node_id = haswell_get_node_id;
3318 pvt->info.get_ha = ibridge_get_ha;
3319 pvt->info.rir_limit = haswell_rir_limit;
3320 pvt->info.sad_limit = sad_limit;
3321 pvt->info.interleave_mode = interleave_mode;
3322 pvt->info.dram_attr = dram_attr;
3323 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3324 pvt->info.interleave_list = ibridge_interleave_list;
3325 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3326 pvt->info.get_width = ibridge_get_width;
3328 /* Store pci devices at mci for faster access */
3329 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3330 if (unlikely(rc < 0))
3333 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d",
3334 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3337 /* rankcfgr isn't used */
3338 pvt->info.get_tolm = haswell_get_tolm;
3339 pvt->info.get_tohm = haswell_get_tohm;
3340 pvt->info.dram_rule = ibridge_dram_rule;
3341 pvt->info.get_memory_type = haswell_get_memory_type;
3342 pvt->info.get_node_id = haswell_get_node_id;
3343 pvt->info.get_ha = ibridge_get_ha;
3344 pvt->info.rir_limit = haswell_rir_limit;
3345 pvt->info.sad_limit = sad_limit;
3346 pvt->info.interleave_mode = interleave_mode;
3347 pvt->info.dram_attr = dram_attr;
3348 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3349 pvt->info.interleave_list = ibridge_interleave_list;
3350 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3351 pvt->info.get_width = broadwell_get_width;
3353 /* Store pci devices at mci for faster access */
3354 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3355 if (unlikely(rc < 0))
3358 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d",
3359 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3361 case KNIGHTS_LANDING:
3362 /* pvt->info.rankcfgr == ??? */
3363 pvt->info.get_tolm = knl_get_tolm;
3364 pvt->info.get_tohm = knl_get_tohm;
3365 pvt->info.dram_rule = knl_dram_rule;
3366 pvt->info.get_memory_type = knl_get_memory_type;
3367 pvt->info.get_node_id = knl_get_node_id;
3368 pvt->info.get_ha = knl_get_ha;
3369 pvt->info.rir_limit = NULL;
3370 pvt->info.sad_limit = knl_sad_limit;
3371 pvt->info.interleave_mode = knl_interleave_mode;
3372 pvt->info.dram_attr = dram_attr_knl;
3373 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3374 pvt->info.interleave_list = knl_interleave_list;
3375 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3376 pvt->info.get_width = knl_get_width;
3378 rc = knl_mci_bind_devs(mci, sbridge_dev);
3379 if (unlikely(rc < 0))
3382 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d",
3383 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3387 if (!mci->ctl_name) {
3392 /* Get dimm basic config and the memory layout */
3393 rc = get_dimm_config(mci);
3395 edac_dbg(0, "MC: failed to get_dimm_config()\n");
3398 get_memory_layout(mci);
3400 /* record ptr to the generic device */
3401 mci->pdev = &pdev->dev;
3403 /* add this new MC control structure to EDAC's list of MCs */
3404 if (unlikely(edac_mc_add_mc(mci))) {
3405 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3413 kfree(mci->ctl_name);
3416 sbridge_dev->mci = NULL;
3420 static const struct x86_cpu_id sbridge_cpuids[] = {
3421 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &pci_dev_descr_sbridge_table),
3422 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &pci_dev_descr_ibridge_table),
3423 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &pci_dev_descr_haswell_table),
3424 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &pci_dev_descr_broadwell_table),
3425 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &pci_dev_descr_broadwell_table),
3426 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &pci_dev_descr_knl_table),
3427 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &pci_dev_descr_knl_table),
3430 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3433 * sbridge_probe Get all devices and register memory controllers
3436 * 0 for FOUND a device
3437 * < 0 for error code
3440 static int sbridge_probe(const struct x86_cpu_id *id)
3444 struct sbridge_dev *sbridge_dev;
3445 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3447 /* get the pci devices we want to reserve for our use */
3448 rc = sbridge_get_all_devices(&num_mc, ptable);
3450 if (unlikely(rc < 0)) {
3451 edac_dbg(0, "couldn't get all devices\n");
3457 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3458 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3459 mc, mc + 1, num_mc);
3461 sbridge_dev->mc = mc++;
3462 rc = sbridge_register_mci(sbridge_dev, ptable->type);
3463 if (unlikely(rc < 0))
3467 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3472 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3473 sbridge_unregister_mci(sbridge_dev);
3475 sbridge_put_all_devices();
3481 * sbridge_remove cleanup
3484 static void sbridge_remove(void)
3486 struct sbridge_dev *sbridge_dev;
3490 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3491 sbridge_unregister_mci(sbridge_dev);
3493 /* Release PCI resources */
3494 sbridge_put_all_devices();
3498 * sbridge_init Module entry function
3499 * Try to initialize this module for its devices
3501 static int __init sbridge_init(void)
3503 const struct x86_cpu_id *id;
3509 owner = edac_get_owner();
3510 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
3513 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
3516 id = x86_match_cpu(sbridge_cpuids);
3520 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3523 rc = sbridge_probe(id);
3526 mce_register_decode_chain(&sbridge_mce_dec);
3530 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3537 * sbridge_exit() Module exit function
3538 * Unregister the driver
3540 static void __exit sbridge_exit(void)
3544 mce_unregister_decode_chain(&sbridge_mce_dec);
3547 module_init(sbridge_init);
3548 module_exit(sbridge_exit);
3550 module_param(edac_op_state, int, 0444);
3551 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3553 MODULE_LICENSE("GPL");
3554 MODULE_AUTHOR("Mauro Carvalho Chehab");
3555 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
3556 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "