1 #include <linux/module.h>
2 #include <linux/slab.h>
8 static struct amd_decoder_ops *fam_ops;
10 static u8 xec_mask = 0xf;
12 static bool report_gart_errors;
13 static void (*decode_dram_ecc)(int node_id, struct mce *m);
15 void amd_report_gart_errors(bool v)
17 report_gart_errors = v;
19 EXPORT_SYMBOL_GPL(amd_report_gart_errors);
21 void amd_register_ecc_decoder(void (*f)(int, struct mce *))
25 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
27 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
29 if (decode_dram_ecc) {
30 WARN_ON(decode_dram_ecc != f);
32 decode_dram_ecc = NULL;
35 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
38 * string representation for the different MCA reported error types, see F3x48
42 /* transaction type */
43 static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
46 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
48 /* memory transaction type */
49 static const char * const rrrr_msgs[] = {
50 "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
53 /* participating processor */
54 const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
55 EXPORT_SYMBOL_GPL(pp_msgs);
58 static const char * const to_msgs[] = { "no timeout", "timed out" };
61 static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
63 /* internal error type */
64 static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
66 static const char * const f15h_mc1_mce_desc[] = {
67 "UC during a demand linefill from L2",
68 "Parity error during data load from IC",
69 "Parity error for IC valid bit",
70 "Main tag parity error",
71 "Parity error in prediction queue",
72 "PFB data/address parity error",
73 "Parity error in the branch status reg",
74 "PFB promotion address error",
75 "Tag error during probe/victimization",
76 "Parity error for IC probe tag valid bit",
77 "PFB non-cacheable bit parity error",
78 "PFB valid bit parity error", /* xec = 0xd */
79 "Microcode Patch Buffer", /* xec = 010 */
87 static const char * const f15h_mc2_mce_desc[] = {
88 "Fill ECC error on data fills", /* xec = 0x4 */
89 "Fill parity error on insn fills",
90 "Prefetcher request FIFO parity error",
91 "PRQ address parity error",
92 "PRQ data parity error",
95 "WCB Data parity error",
96 "VB Data ECC or parity error",
97 "L2 Tag ECC error", /* xec = 0x10 */
98 "Hard L2 Tag ECC error",
99 "Multiple hits on L2 tag",
101 "PRB address parity error"
104 static const char * const mc4_mce_desc[] = {
105 "DRAM ECC error detected on the NB",
106 "CRC error detected on HT link",
107 "Link-defined sync error packets detected on HT link",
110 "Invalid GART PTE entry during GART table walk",
111 "Unsupported atomic RMW received from an IO link",
112 "Watchdog timeout due to lack of progress",
113 "DRAM ECC error detected on the NB",
114 "SVM DMA Exclusion Vector error",
115 "HT data error detected on link",
116 "Protocol error (link, L3, probe filter)",
117 "NB internal arrays parity error",
118 "DRAM addr/ctl signals parity error",
119 "IO link transmission error",
120 "L3 data cache ECC error", /* xec = 0x1c */
121 "L3 cache tag error",
122 "L3 LRU parity bits error",
123 "ECC Error in the Probe Filter directory"
126 static const char * const mc5_mce_desc[] = {
127 "CPU Watchdog timer expire",
128 "Wakeup array dest tag",
132 "Retire dispatch queue",
133 "Mapper checkpoint array",
134 "Physical register file EX0 port",
135 "Physical register file EX1 port",
136 "Physical register file AG0 port",
137 "Physical register file AG1 port",
138 "Flag register file",
140 "Retire status queue"
143 static const char * const mc6_mce_desc[] = {
144 "Hardware Assertion",
146 "Physical Register File",
149 "Status Register File",
152 /* Scalable MCA error strings */
153 static const char * const smca_ls_mce_desc[] = {
155 "Store queue parity",
156 "Miss address buffer payload parity",
159 "DC tag error type 6",
160 "DC tag error type 1",
161 "Internal error type 1",
162 "Internal error type 2",
163 "Sys Read data error thread 0",
164 "Sys read data error thread 1",
165 "DC tag error type 2",
166 "DC data error type 1 (poison consumption)",
167 "DC data error type 2",
168 "DC data error type 3",
169 "DC tag error type 4",
172 "DC tag error type 3",
173 "DC tag error type 5",
174 "L2 fill data error",
177 static const char * const smca_if_mce_desc[] = {
178 "microtag probe port parity error",
179 "IC microtag or full tag multi-hit error",
180 "IC full tag parity",
181 "IC data array parity",
182 "Decoupling queue phys addr parity error",
183 "L0 ITLB parity error",
184 "L1 ITLB parity error",
185 "L2 ITLB parity error",
186 "BPQ snoop parity on Thread 0",
187 "BPQ snoop parity on Thread 1",
188 "L1 BTB multi-match error",
189 "L2 BTB multi-match error",
190 "L2 Cache Response Poison error",
191 "System Read Data error",
194 static const char * const smca_l2_mce_desc[] = {
195 "L2M tag multi-way-hit error",
197 "L2M data ECC error",
201 static const char * const smca_de_mce_desc[] = {
202 "uop cache tag parity error",
203 "uop cache data parity error",
204 "Insn buffer parity error",
205 "uop queue parity error",
206 "Insn dispatch queue parity error",
207 "Fetch address FIFO parity",
208 "Patch RAM data parity",
209 "Patch RAM sequencer parity",
213 static const char * const smca_ex_mce_desc[] = {
214 "Watchdog timeout error",
215 "Phy register file parity",
216 "Flag register file parity",
217 "Immediate displacement register file parity",
218 "Address generator payload parity",
220 "Checkpoint queue parity",
221 "Retire dispatch queue parity",
222 "Retire status queue parity error",
223 "Scheduling queue parity error",
224 "Branch buffer queue parity error",
227 static const char * const smca_fp_mce_desc[] = {
228 "Physical register file parity",
229 "Freelist parity error",
230 "Schedule queue parity",
232 "Retire queue parity",
233 "Status register file parity",
234 "Hardware assertion",
237 static const char * const smca_l3_mce_desc[] = {
238 "Shadow tag macro ECC error",
239 "Shadow tag macro multi-way-hit error",
241 "L3M tag multi-way-hit error",
242 "L3M data ECC error",
243 "XI parity, L3 fill done channel error",
244 "L3 victim queue parity",
248 static const char * const smca_cs_mce_desc[] = {
249 "Illegal request from transport layer",
251 "Security violation",
252 "Illegal response from transport layer",
253 "Unexpected response",
254 "Parity error on incoming request or probe response data",
255 "Parity error on incoming read response data",
256 "Atomic request parity",
257 "ECC error on probe filter access",
260 static const char * const smca_pie_mce_desc[] = {
262 "Internal PIE register security violation",
264 "Poison data written to internal PIE register",
267 static const char * const smca_umc_mce_desc[] = {
269 "Data poison error on DRAM",
271 "Advanced peripheral bus error",
272 "Command/address parity error",
273 "Write data CRC error",
276 static const char * const smca_pb_mce_desc[] = {
277 "Parameter Block RAM ECC error",
280 static const char * const smca_psp_mce_desc[] = {
281 "PSP RAM ECC or parity error",
284 static const char * const smca_smu_mce_desc[] = {
285 "SMU RAM ECC or parity error",
288 static const char * const smca_mp5_mce_desc[] = {
289 "High SRAM ECC or parity error",
290 "Low SRAM ECC or parity error",
291 "Data Cache Bank A ECC or parity error",
292 "Data Cache Bank B ECC or parity error",
293 "Data Tag Cache Bank A ECC or parity error",
294 "Data Tag Cache Bank B ECC or parity error",
295 "Instruction Cache Bank A ECC or parity error",
296 "Instruction Cache Bank B ECC or parity error",
297 "Instruction Tag Cache Bank A ECC or parity error",
298 "Instruction Tag Cache Bank B ECC or parity error",
301 static const char * const smca_nbio_mce_desc[] = {
302 "ECC or Parity error",
304 "SDP ErrEvent error",
305 "SDP Egress Poison Error",
306 "IOHC Internal Poison Error",
309 static const char * const smca_pcie_mce_desc[] = {
310 "CCIX PER Message logging",
311 "CCIX Read Response with Status: Non-Data Error",
312 "CCIX Write Response with Status: Non-Data Error",
313 "CCIX Read Response with Status: Data Error",
314 "CCIX Non-okay write response with data error",
317 struct smca_mce_desc {
318 const char * const *descs;
319 unsigned int num_descs;
322 static struct smca_mce_desc smca_mce_descs[] = {
323 [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) },
324 [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) },
325 [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) },
326 [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) },
327 [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) },
328 [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
329 [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
330 [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
331 [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
332 [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
333 [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
334 [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
335 [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
336 [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) },
337 [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) },
338 [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) },
341 static bool f12h_mc0_mce(u16 ec, u8 xec)
350 pr_cont("during L1 linefill from L2.\n");
351 else if (ll == LL_L1)
352 pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
359 static bool f10h_mc0_mce(u16 ec, u8 xec)
361 if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
362 pr_cont("during data scrub.\n");
365 return f12h_mc0_mce(ec, xec);
368 static bool k8_mc0_mce(u16 ec, u8 xec)
371 pr_cont("during system linefill.\n");
375 return f10h_mc0_mce(ec, xec);
378 static bool cat_mc0_mce(u16 ec, u8 xec)
385 if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
391 pr_cont("Data/Tag parity error due to %s.\n",
392 (r4 == R4_DRD ? "load/hw prf" : "store"));
395 pr_cont("Copyback parity error on a tag miss.\n");
398 pr_cont("Tag parity error during snoop.\n");
403 } else if (BUS_ERROR(ec)) {
405 if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
408 pr_cont("System read data error on a ");
412 pr_cont("TLB reload.\n");
430 static bool f15h_mc0_mce(u16 ec, u8 xec)
438 pr_cont("Data Array access error.\n");
442 pr_cont("UC error during a linefill from L2/NB.\n");
447 pr_cont("STQ access error.\n");
451 pr_cont("SCB access error.\n");
455 pr_cont("Tag error.\n");
459 pr_cont("LDQ access error.\n");
465 } else if (BUS_ERROR(ec)) {
468 pr_cont("System Read Data Error.\n");
470 pr_cont(" Internal error condition type %d.\n", xec);
471 } else if (INT_ERROR(ec)) {
473 pr_cont("Hardware Assert.\n");
483 static void decode_mc0_mce(struct mce *m)
485 u16 ec = EC(m->status);
486 u8 xec = XEC(m->status, xec_mask);
488 pr_emerg(HW_ERR "MC0 Error: ");
490 /* TLB error signatures are the same across families */
492 if (TT(ec) == TT_DATA) {
493 pr_cont("%s TLB %s.\n", LL_MSG(ec),
494 ((xec == 2) ? "locked miss"
495 : (xec ? "multimatch" : "parity")));
498 } else if (fam_ops->mc0_mce(ec, xec))
501 pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
504 static bool k8_mc1_mce(u16 ec, u8 xec)
513 pr_cont("during a linefill from L2.\n");
514 else if (ll == 0x1) {
517 pr_cont("Parity error during data load.\n");
521 pr_cont("Copyback Parity/Victim error.\n");
525 pr_cont("Tag Snoop error.\n");
538 static bool cat_mc1_mce(u16 ec, u8 xec)
546 if (TT(ec) != TT_INSTR)
550 pr_cont("Data/tag array parity error for a tag hit.\n");
551 else if (r4 == R4_SNOOP)
552 pr_cont("Tag error during snoop/victimization.\n");
554 pr_cont("Tag parity error from victim castout.\n");
556 pr_cont("Microcode patch RAM parity error.\n");
563 static bool f15h_mc1_mce(u16 ec, u8 xec)
572 pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
576 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
580 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
584 pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
593 static void decode_mc1_mce(struct mce *m)
595 u16 ec = EC(m->status);
596 u8 xec = XEC(m->status, xec_mask);
598 pr_emerg(HW_ERR "MC1 Error: ");
601 pr_cont("%s TLB %s.\n", LL_MSG(ec),
602 (xec ? "multimatch" : "parity error"));
603 else if (BUS_ERROR(ec)) {
604 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
606 pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
607 } else if (INT_ERROR(ec)) {
609 pr_cont("Hardware Assert.\n");
612 } else if (fam_ops->mc1_mce(ec, xec))
620 pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
623 static bool k8_mc2_mce(u16 ec, u8 xec)
628 pr_cont(" in the write data buffers.\n");
630 pr_cont(" in the victim data buffers.\n");
631 else if (xec == 0x2 && MEM_ERROR(ec))
632 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
633 else if (xec == 0x0) {
635 pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
637 else if (BUS_ERROR(ec))
638 pr_cont(": %s/ECC error in data read from NB: %s.\n",
639 R4_MSG(ec), PP_MSG(ec));
640 else if (MEM_ERROR(ec)) {
644 pr_cont(": %s error during data copyback.\n",
647 pr_cont(": %s parity/ECC error during data "
648 "access from L2.\n", R4_MSG(ec));
659 static bool f15h_mc2_mce(u16 ec, u8 xec)
665 pr_cont("Data parity TLB read error.\n");
667 pr_cont("Poison data provided for TLB fill.\n");
670 } else if (BUS_ERROR(ec)) {
674 pr_cont("Error during attempted NB data read.\n");
675 } else if (MEM_ERROR(ec)) {
678 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
682 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
688 } else if (INT_ERROR(ec)) {
690 pr_cont("Hardware Assert.\n");
698 static bool f16h_mc2_mce(u16 ec, u8 xec)
707 pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
712 pr_cont("ECC error in L2 tag (%s).\n",
713 ((r4 == R4_GEN) ? "BankReq" :
714 ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
719 pr_cont("ECC error in L2 data array (%s).\n",
720 (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
721 ((r4 == R4_GEN) ? "Attr" :
722 ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
727 pr_cont("Parity error in L2 attribute bits (%s).\n",
728 ((r4 == R4_RD) ? "Hit" :
729 ((r4 == R4_GEN) ? "Attr" : "Fill")));
739 static void decode_mc2_mce(struct mce *m)
741 u16 ec = EC(m->status);
742 u8 xec = XEC(m->status, xec_mask);
744 pr_emerg(HW_ERR "MC2 Error: ");
746 if (!fam_ops->mc2_mce(ec, xec))
747 pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
750 static void decode_mc3_mce(struct mce *m)
752 u16 ec = EC(m->status);
753 u8 xec = XEC(m->status, xec_mask);
755 if (boot_cpu_data.x86 >= 0x14) {
756 pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
757 " please report on LKML.\n");
761 pr_emerg(HW_ERR "MC3 Error");
766 if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
769 pr_cont(" during %s.\n", R4_MSG(ec));
776 pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
779 static void decode_mc4_mce(struct mce *m)
781 unsigned int fam = x86_family(m->cpuid);
782 int node_id = amd_get_nb_id(m->extcpu);
783 u16 ec = EC(m->status);
784 u8 xec = XEC(m->status, 0x1f);
787 pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
792 /* special handling for DRAM ECCs */
793 if (xec == 0x0 || xec == 0x8) {
794 /* no ECCs on F11h */
798 pr_cont("%s.\n", mc4_mce_desc[xec]);
801 decode_dram_ecc(node_id, m);
808 pr_cont("GART Table Walk data error.\n");
809 else if (BUS_ERROR(ec))
810 pr_cont("DMA Exclusion Vector Table Walk error.\n");
816 if (fam == 0x15 || fam == 0x16)
817 pr_cont("Compute Unit Data Error.\n");
830 pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
834 pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
837 static void decode_mc5_mce(struct mce *m)
839 unsigned int fam = x86_family(m->cpuid);
840 u16 ec = EC(m->status);
841 u8 xec = XEC(m->status, xec_mask);
843 if (fam == 0xf || fam == 0x11)
846 pr_emerg(HW_ERR "MC5 Error: ");
850 pr_cont("Hardware Assert.\n");
856 if (xec == 0x0 || xec == 0xc)
857 pr_cont("%s.\n", mc5_mce_desc[xec]);
859 pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
866 pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
869 static void decode_mc6_mce(struct mce *m)
871 u8 xec = XEC(m->status, xec_mask);
873 pr_emerg(HW_ERR "MC6 Error: ");
878 pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
882 pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
885 /* Decode errors according to Scalable MCA specification */
886 static void decode_smca_error(struct mce *m)
888 struct smca_hwid *hwid;
889 enum smca_bank_types bank_type;
891 u8 xec = XEC(m->status, xec_mask);
893 if (m->bank >= ARRAY_SIZE(smca_banks))
896 hwid = smca_banks[m->bank].hwid;
900 bank_type = hwid->bank_type;
902 if (bank_type == SMCA_RESERVED) {
903 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);
907 ip_name = smca_get_long_name(bank_type);
909 pr_emerg(HW_ERR "%s Extended Error Code: %d\n", ip_name, xec);
911 /* Only print the decode of valid error codes */
912 if (xec < smca_mce_descs[bank_type].num_descs &&
913 (hwid->xec_bitmap & BIT_ULL(xec))) {
914 pr_emerg(HW_ERR "%s Error: ", ip_name);
915 pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
918 if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
919 decode_dram_ecc(cpu_to_node(m->extcpu), m);
922 static inline void amd_decode_err_code(u16 ec)
925 pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
929 pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
932 pr_cont(", mem/io: %s", II_MSG(ec));
934 pr_cont(", tx: %s", TT_MSG(ec));
936 if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
937 pr_cont(", mem-tx: %s", R4_MSG(ec));
940 pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
947 * Filter out unwanted MCE signatures here.
949 static bool amd_filter_mce(struct mce *m)
952 * NB GART TLB error reporting is disabled by default.
954 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors)
960 static const char *decode_error_status(struct mce *m)
962 if (m->status & MCI_STATUS_UC) {
963 if (m->status & MCI_STATUS_PCC)
964 return "System Fatal error.";
965 if (m->mcgstatus & MCG_STATUS_RIPV)
966 return "Uncorrected, software restartable error.";
967 return "Uncorrected, software containable error.";
970 if (m->status & MCI_STATUS_DEFERRED)
971 return "Deferred error, no action required.";
973 return "Corrected error, no action required.";
977 amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
979 struct mce *m = (struct mce *)data;
980 unsigned int fam = x86_family(m->cpuid);
983 if (amd_filter_mce(m))
986 pr_emerg(HW_ERR "%s\n", decode_error_status(m));
988 pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
990 fam, x86_model(m->cpuid), x86_stepping(m->cpuid),
992 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
993 ((m->status & MCI_STATUS_UC) ? "UE" :
994 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
995 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
996 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
997 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
1000 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
1002 /* F15h, bank4, bit 43 is part of McaStatSubCache. */
1003 if (fam != 0x15 || m->bank != 4)
1004 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
1007 if (boot_cpu_has(X86_FEATURE_SMCA)) {
1009 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
1011 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
1013 if (!rdmsr_safe(addr, &low, &high) &&
1014 (low & MCI_CONFIG_MCAX))
1015 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
1018 /* do the two bits[14:13] together */
1019 ecc = (m->status >> 45) & 0x3;
1021 pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
1023 pr_cont("]: 0x%016llx\n", m->status);
1025 if (m->status & MCI_STATUS_ADDRV)
1026 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
1028 if (boot_cpu_has(X86_FEATURE_SMCA)) {
1029 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
1031 if (m->status & MCI_STATUS_SYNDV)
1032 pr_cont(", Syndrome: 0x%016llx", m->synd);
1036 decode_smca_error(m);
1041 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);
1080 amd_decode_err_code(m->status & 0xffff);
1085 static struct notifier_block amd_mce_dec_nb = {
1086 .notifier_call = amd_decode_mce,
1087 .priority = MCE_PRIO_EDAC,
1090 static int __init mce_amd_init(void)
1092 struct cpuinfo_x86 *c = &boot_cpu_data;
1094 if (c->x86_vendor != X86_VENDOR_AMD &&
1095 c->x86_vendor != X86_VENDOR_HYGON)
1098 fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
1104 fam_ops->mc0_mce = k8_mc0_mce;
1105 fam_ops->mc1_mce = k8_mc1_mce;
1106 fam_ops->mc2_mce = k8_mc2_mce;
1110 fam_ops->mc0_mce = f10h_mc0_mce;
1111 fam_ops->mc1_mce = k8_mc1_mce;
1112 fam_ops->mc2_mce = k8_mc2_mce;
1116 fam_ops->mc0_mce = k8_mc0_mce;
1117 fam_ops->mc1_mce = k8_mc1_mce;
1118 fam_ops->mc2_mce = k8_mc2_mce;
1122 fam_ops->mc0_mce = f12h_mc0_mce;
1123 fam_ops->mc1_mce = k8_mc1_mce;
1124 fam_ops->mc2_mce = k8_mc2_mce;
1128 fam_ops->mc0_mce = cat_mc0_mce;
1129 fam_ops->mc1_mce = cat_mc1_mce;
1130 fam_ops->mc2_mce = k8_mc2_mce;
1134 xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
1136 fam_ops->mc0_mce = f15h_mc0_mce;
1137 fam_ops->mc1_mce = f15h_mc1_mce;
1138 fam_ops->mc2_mce = f15h_mc2_mce;
1143 fam_ops->mc0_mce = cat_mc0_mce;
1144 fam_ops->mc1_mce = cat_mc1_mce;
1145 fam_ops->mc2_mce = f16h_mc2_mce;
1151 if (!boot_cpu_has(X86_FEATURE_SMCA)) {
1152 printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");
1158 printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
1162 pr_info("MCE: In-kernel MCE decoding enabled.\n");
1164 mce_register_decode_chain(&amd_mce_dec_nb);
1173 early_initcall(mce_amd_init);
1176 static void __exit mce_amd_exit(void)
1178 mce_unregister_decode_chain(&amd_mce_dec_nb);
1182 MODULE_DESCRIPTION("AMD MCE decoder");
1183 MODULE_ALIAS("edac-mce-amd");
1184 MODULE_LICENSE("GPL");
1185 module_exit(mce_amd_exit);