drivers/edac/i10nm_base.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Intel(R) 10nm server memory controller.
   4  * Copyright (c) 2019, Intel Corporation.
   5  *
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/io.h>
  10 #include <asm/cpu_device_id.h>
  11 #include <asm/intel-family.h>
  12 #include <asm/mce.h>
  13 #include "edac_module.h"
  14 #include "skx_common.h"
  15
  16 #define I10NM_REVISION  "v0.0.5"
  17 #define EDAC_MOD_STR    "i10nm_edac"
  18
  19 /* Debug macros */
  20 #define i10nm_printk(level, fmt, arg...)        \
  21         edac_printk(level, "i10nm", fmt, ##arg)
  22
  23 #define I10NM_GET_SCK_BAR(d, reg)       \
  24         pci_read_config_dword((d)->uracu, 0xd0, &(reg))
  25 #define I10NM_GET_IMC_BAR(d, i, reg)    \
  26         pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
  27 #define I10NM_GET_SAD(d, offset, i, reg)\
  28         pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
  29 #define I10NM_GET_HBM_IMC_BAR(d, reg)   \
  30         pci_read_config_dword((d)->uracu, 0xd4, &(reg))
  31 #define I10NM_GET_CAPID3_CFG(d, reg)    \
  32         pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
  33 #define I10NM_GET_DIMMMTR(m, i, j)      \
  34         readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
  35         (i) * (m)->chan_mmio_sz + (j) * 4)
  36 #define I10NM_GET_MCDDRTCFG(m, i)       \
  37         readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
  38         (i) * (m)->chan_mmio_sz)
  39 #define I10NM_GET_MCMTR(m, i)           \
  40         readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
  41         (i) * (m)->chan_mmio_sz)
  42 #define I10NM_GET_AMAP(m, i)            \
  43         readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
  44         (i) * (m)->chan_mmio_sz)
  45 #define I10NM_GET_REG32(m, i, offset)   \
  46         readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
  47 #define I10NM_GET_REG64(m, i, offset)   \
  48         readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
  49 #define I10NM_SET_REG32(m, i, offset, v)        \
  50         writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
  51
  52 #define I10NM_GET_SCK_MMIO_BASE(reg)    (GET_BITFIELD(reg, 0, 28) << 23)
  53 #define I10NM_GET_IMC_MMIO_OFFSET(reg)  (GET_BITFIELD(reg, 0, 10) << 12)
  54 #define I10NM_GET_IMC_MMIO_SIZE(reg)    ((GET_BITFIELD(reg, 13, 23) - \
  55                                          GET_BITFIELD(reg, 0, 10) + 1) << 12)
  56 #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg)      \
  57         ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
  58
  59 #define I10NM_HBM_IMC_MMIO_SIZE         0x9000
  60 #define I10NM_IS_HBM_PRESENT(reg)       GET_BITFIELD(reg, 27, 30)
  61 #define I10NM_IS_HBM_IMC(reg)           GET_BITFIELD(reg, 29, 29)
  62
  63 #define I10NM_MAX_SAD                   16
  64 #define I10NM_SAD_ENABLE(reg)           GET_BITFIELD(reg, 0, 0)
  65 #define I10NM_SAD_NM_CACHEABLE(reg)     GET_BITFIELD(reg, 5, 5)
  66
  67 #define RETRY_RD_ERR_LOG_UC             BIT(1)
  68 #define RETRY_RD_ERR_LOG_NOOVER         BIT(14)
  69 #define RETRY_RD_ERR_LOG_EN             BIT(15)
  70 #define RETRY_RD_ERR_LOG_NOOVER_UC      (BIT(14) | BIT(1))
  71 #define RETRY_RD_ERR_LOG_OVER_UC_V      (BIT(2) | BIT(1) | BIT(0))
  72
  73 static struct list_head *i10nm_edac_list;
  74
  75 static struct res_config *res_cfg;
  76 static int retry_rd_err_log;
  77
  78 static u32 offsets_scrub_icx[]  = {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8};
  79 static u32 offsets_scrub_spr[]  = {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8};
  80 static u32 offsets_demand_icx[] = {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0};
  81 static u32 offsets_demand_spr[] = {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0};
  82
  83 static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable)
  84 {
  85         u32 s, d;
  86
  87         if (!imc->mbase)
  88                 return;
  89
  90         s = I10NM_GET_REG32(imc, chan, res_cfg->offsets_scrub[0]);
  91         d = I10NM_GET_REG32(imc, chan, res_cfg->offsets_demand[0]);
  92
  93         if (enable) {
  94                 /* Save default configurations */
  95                 imc->chan[chan].retry_rd_err_log_s = s;
  96                 imc->chan[chan].retry_rd_err_log_d = d;
  97
  98                 s &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
  99                 s |=  RETRY_RD_ERR_LOG_EN;
 100                 d &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
 101                 d |=  RETRY_RD_ERR_LOG_EN;
 102         } else {
 103                 /* Restore default configurations */
 104                 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC)
 105                         s |=  RETRY_RD_ERR_LOG_UC;
 106                 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER)
 107                         s |=  RETRY_RD_ERR_LOG_NOOVER;
 108                 if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN))
 109                         s &= ~RETRY_RD_ERR_LOG_EN;
 110                 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC)
 111                         d |=  RETRY_RD_ERR_LOG_UC;
 112                 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER)
 113                         d |=  RETRY_RD_ERR_LOG_NOOVER;
 114                 if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN))
 115                         d &= ~RETRY_RD_ERR_LOG_EN;
 116         }
 117
 118         I10NM_SET_REG32(imc, chan, res_cfg->offsets_scrub[0], s);
 119         I10NM_SET_REG32(imc, chan, res_cfg->offsets_demand[0], d);
 120 }
 121
 122 static void enable_retry_rd_err_log(bool enable)
 123 {
 124         struct skx_dev *d;
 125         int i, j;
 126
 127         edac_dbg(2, "\n");
 128
 129         list_for_each_entry(d, i10nm_edac_list, list)
 130                 for (i = 0; i < I10NM_NUM_IMC; i++)
 131                         for (j = 0; j < I10NM_NUM_CHANNELS; j++)
 132                                 __enable_retry_rd_err_log(&d->imc[i], j, enable);
 133 }
 134
 135 static void show_retry_rd_err_log(struct decoded_addr *res, char *msg,
 136                                   int len, bool scrub_err)
 137 {
 138         struct skx_imc *imc = &res->dev->imc[res->imc];
 139         u32 log0, log1, log2, log3, log4;
 140         u32 corr0, corr1, corr2, corr3;
 141         u64 log2a, log5;
 142         u32 *offsets;
 143         int n;
 144
 145         if (!imc->mbase)
 146                 return;
 147
 148         offsets = scrub_err ? res_cfg->offsets_scrub : res_cfg->offsets_demand;
 149
 150         log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]);
 151         log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]);
 152         log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]);
 153         log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]);
 154         log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]);
 155
 156         if (res_cfg->type == SPR) {
 157                 log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]);
 158                 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.16llx %.8x %.8x %.16llx]",
 159                              log0, log1, log2a, log3, log4, log5);
 160         } else {
 161                 log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]);
 162                 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x %.16llx]",
 163                              log0, log1, log2, log3, log4, log5);
 164         }
 165
 166         corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18);
 167         corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c);
 168         corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20);
 169         corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24);
 170
 171         if (len - n > 0)
 172                 snprintf(msg + n, len - n,
 173                          " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
 174                          corr0 & 0xffff, corr0 >> 16,
 175                          corr1 & 0xffff, corr1 >> 16,
 176                          corr2 & 0xffff, corr2 >> 16,
 177                          corr3 & 0xffff, corr3 >> 16);
 178
 179         /* Clear status bits */
 180         if (retry_rd_err_log == 2 && (log0 & RETRY_RD_ERR_LOG_OVER_UC_V)) {
 181                 log0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V;
 182                 I10NM_SET_REG32(imc, res->channel, offsets[0], log0);
 183         }
 184 }
 185
 186 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
 187                                            unsigned int dev, unsigned int fun)
 188 {
 189         struct pci_dev *pdev;
 190
 191         pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
 192         if (!pdev) {
 193                 edac_dbg(2, "No device %02x:%02x.%x\n",
 194                          bus, dev, fun);
 195                 return NULL;
 196         }
 197
 198         if (unlikely(pci_enable_device(pdev) < 0)) {
 199                 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
 200                          bus, dev, fun);
 201                 pci_dev_put(pdev);
 202                 return NULL;
 203         }
 204
 205         return pdev;
 206 }
 207
 208 static bool i10nm_check_2lm(struct res_config *cfg)
 209 {
 210         struct skx_dev *d;
 211         u32 reg;
 212         int i;
 213
 214         list_for_each_entry(d, i10nm_edac_list, list) {
 215                 d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1],
 216                                                  PCI_SLOT(cfg->sad_all_devfn),
 217                                                  PCI_FUNC(cfg->sad_all_devfn));
 218                 if (!d->sad_all)
 219                         continue;
 220
 221                 for (i = 0; i < I10NM_MAX_SAD; i++) {
 222                         I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);
 223                         if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) {
 224                                 edac_dbg(2, "2-level memory configuration.\n");
 225                                 return true;
 226                         }
 227                 }
 228         }
 229
 230         return false;
 231 }
 232
 233 static int i10nm_get_ddr_munits(void)
 234 {
 235         struct pci_dev *mdev;
 236         void __iomem *mbase;
 237         unsigned long size;
 238         struct skx_dev *d;
 239         int i, j = 0;
 240         u32 reg, off;
 241         u64 base;
 242
 243         list_for_each_entry(d, i10nm_edac_list, list) {
 244                 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
 245                 if (!d->util_all)
 246                         return -ENODEV;
 247
 248                 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
 249                 if (!d->uracu)
 250                         return -ENODEV;
 251
 252                 if (I10NM_GET_SCK_BAR(d, reg)) {
 253                         i10nm_printk(KERN_ERR, "Failed to socket bar\n");
 254                         return -ENODEV;
 255                 }
 256
 257                 base = I10NM_GET_SCK_MMIO_BASE(reg);
 258                 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
 259                          j++, base, reg);
 260
 261                 for (i = 0; i < I10NM_NUM_DDR_IMC; i++) {
 262                         mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
 263                                                    12 + i, 0);
 264                         if (i == 0 && !mdev) {
 265                                 i10nm_printk(KERN_ERR, "No IMC found\n");
 266                                 return -ENODEV;
 267                         }
 268                         if (!mdev)
 269                                 continue;
 270
 271                         d->imc[i].mdev = mdev;
 272
 273                         if (I10NM_GET_IMC_BAR(d, i, reg)) {
 274                                 i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
 275                                 return -ENODEV;
 276                         }
 277
 278                         off  = I10NM_GET_IMC_MMIO_OFFSET(reg);
 279                         size = I10NM_GET_IMC_MMIO_SIZE(reg);
 280                         edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
 281                                  i, base + off, size, reg);
 282
 283                         mbase = ioremap(base + off, size);
 284                         if (!mbase) {
 285                                 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
 286                                              base + off);
 287                                 return -ENODEV;
 288                         }
 289
 290                         d->imc[i].mbase = mbase;
 291                 }
 292         }
 293
 294         return 0;
 295 }
 296
 297 static bool i10nm_check_hbm_imc(struct skx_dev *d)
 298 {
 299         u32 reg;
 300
 301         if (I10NM_GET_CAPID3_CFG(d, reg)) {
 302                 i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
 303                 return false;
 304         }
 305
 306         return I10NM_IS_HBM_PRESENT(reg) != 0;
 307 }
 308
 309 static int i10nm_get_hbm_munits(void)
 310 {
 311         struct pci_dev *mdev;
 312         void __iomem *mbase;
 313         u32 reg, off, mcmtr;
 314         struct skx_dev *d;
 315         int i, lmc;
 316         u64 base;
 317
 318         list_for_each_entry(d, i10nm_edac_list, list) {
 319                 d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3);
 320                 if (!d->pcu_cr3)
 321                         return -ENODEV;
 322
 323                 if (!i10nm_check_hbm_imc(d)) {
 324                         i10nm_printk(KERN_DEBUG, "No hbm memory\n");
 325                         return -ENODEV;
 326                 }
 327
 328                 if (I10NM_GET_SCK_BAR(d, reg)) {
 329                         i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
 330                         return -ENODEV;
 331                 }
 332                 base = I10NM_GET_SCK_MMIO_BASE(reg);
 333
 334                 if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
 335                         i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
 336                         return -ENODEV;
 337                 }
 338                 base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);
 339
 340                 lmc = I10NM_NUM_DDR_IMC;
 341
 342                 for (i = 0; i < I10NM_NUM_HBM_IMC; i++) {
 343                         mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
 344                                                    12 + i / 4, 1 + i % 4);
 345                         if (i == 0 && !mdev) {
 346                                 i10nm_printk(KERN_ERR, "No hbm mc found\n");
 347                                 return -ENODEV;
 348                         }
 349                         if (!mdev)
 350                                 continue;
 351
 352                         d->imc[lmc].mdev = mdev;
 353                         off = i * I10NM_HBM_IMC_MMIO_SIZE;
 354
 355                         edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
 356                                  lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);
 357
 358                         mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE);
 359                         if (!mbase) {
 360                                 pci_dev_put(d->imc[lmc].mdev);
 361                                 d->imc[lmc].mdev = NULL;
 362
 363                                 i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
 364                                              base + off);
 365                                 return -ENOMEM;
 366                         }
 367
 368                         d->imc[lmc].mbase = mbase;
 369                         d->imc[lmc].hbm_mc = true;
 370
 371                         mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
 372                         if (!I10NM_IS_HBM_IMC(mcmtr)) {
 373                                 iounmap(d->imc[lmc].mbase);
 374                                 d->imc[lmc].mbase = NULL;
 375                                 d->imc[lmc].hbm_mc = false;
 376                                 pci_dev_put(d->imc[lmc].mdev);
 377                                 d->imc[lmc].mdev = NULL;
 378
 379                                 i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
 380                                 return -ENODEV;
 381                         }
 382
 383                         lmc++;
 384                 }
 385         }
 386
 387         return 0;
 388 }
 389
 390 static struct res_config i10nm_cfg0 = {
 391         .type                   = I10NM,
 392         .decs_did               = 0x3452,
 393         .busno_cfg_offset       = 0xcc,
 394         .ddr_chan_mmio_sz       = 0x4000,
 395         .sad_all_devfn          = PCI_DEVFN(29, 0),
 396         .sad_all_offset         = 0x108,
 397         .offsets_scrub          = offsets_scrub_icx,
 398         .offsets_demand         = offsets_demand_icx,
 399 };
 400
 401 static struct res_config i10nm_cfg1 = {
 402         .type                   = I10NM,
 403         .decs_did               = 0x3452,
 404         .busno_cfg_offset       = 0xd0,
 405         .ddr_chan_mmio_sz       = 0x4000,
 406         .sad_all_devfn          = PCI_DEVFN(29, 0),
 407         .sad_all_offset         = 0x108,
 408         .offsets_scrub          = offsets_scrub_icx,
 409         .offsets_demand         = offsets_demand_icx,
 410 };
 411
 412 static struct res_config spr_cfg = {
 413         .type                   = SPR,
 414         .decs_did               = 0x3252,
 415         .busno_cfg_offset       = 0xd0,
 416         .ddr_chan_mmio_sz       = 0x8000,
 417         .hbm_chan_mmio_sz       = 0x4000,
 418         .support_ddr5           = true,
 419         .sad_all_devfn          = PCI_DEVFN(10, 0),
 420         .sad_all_offset         = 0x300,
 421         .offsets_scrub          = offsets_scrub_spr,
 422         .offsets_demand         = offsets_demand_spr,
 423 };
 424
 425 static const struct x86_cpu_id i10nm_cpuids[] = {
 426         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
 427         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
 428         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,         X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
 429         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,         X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
 430         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D,         X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
 431         X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X,  X86_STEPPINGS(0x0, 0xf), &spr_cfg),
 432         {}
 433 };
 434 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
 435
 436 static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
 437 {
 438         u32 mcmtr;
 439
 440         mcmtr = I10NM_GET_MCMTR(imc, chan);
 441         edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
 442
 443         return !!GET_BITFIELD(mcmtr, 2, 2);
 444 }
 445
 446 static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
 447                                  struct res_config *cfg)
 448 {
 449         struct skx_pvt *pvt = mci->pvt_info;
 450         struct skx_imc *imc = pvt->imc;
 451         u32 mtr, amap, mcddrtcfg;
 452         struct dimm_info *dimm;
 453         int i, j, ndimms;
 454
 455         for (i = 0; i < imc->num_channels; i++) {
 456                 if (!imc->mbase)
 457                         continue;
 458
 459                 ndimms = 0;
 460                 amap = I10NM_GET_AMAP(imc, i);
 461                 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
 462                 for (j = 0; j < imc->num_dimms; j++) {
 463                         dimm = edac_get_dimm(mci, i, j, 0);
 464                         mtr = I10NM_GET_DIMMMTR(imc, i, j);
 465                         edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
 466                                  mtr, mcddrtcfg, imc->mc, i, j);
 467
 468                         if (IS_DIMM_PRESENT(mtr))
 469                                 ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
 470                                                             imc, i, j, cfg);
 471                         else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
 472                                 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
 473                                                               EDAC_MOD_STR);
 474                 }
 475                 if (ndimms && !i10nm_check_ecc(imc, i)) {
 476                         i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
 477                                      imc->mc, i);
 478                         return -ENODEV;
 479                 }
 480         }
 481
 482         return 0;
 483 }
 484
 485 static struct notifier_block i10nm_mce_dec = {
 486         .notifier_call  = skx_mce_check_error,
 487         .priority       = MCE_PRIO_EDAC,
 488 };
 489
 490 #ifdef CONFIG_EDAC_DEBUG
 491 /*
 492  * Debug feature.
 493  * Exercise the address decode logic by writing an address to
 494  * /sys/kernel/debug/edac/i10nm_test/addr.
 495  */
 496 static struct dentry *i10nm_test;
 497
 498 static int debugfs_u64_set(void *data, u64 val)
 499 {
 500         struct mce m;
 501
 502         pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
 503
 504         memset(&m, 0, sizeof(m));
 505         /* ADDRV + MemRd + Unknown channel */
 506         m.status = MCI_STATUS_ADDRV + 0x90;
 507         /* One corrected error */
 508         m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
 509         m.addr = val;
 510         skx_mce_check_error(NULL, 0, &m);
 511
 512         return 0;
 513 }
 514 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
 515
 516 static void setup_i10nm_debug(void)
 517 {
 518         i10nm_test = edac_debugfs_create_dir("i10nm_test");
 519         if (!i10nm_test)
 520                 return;
 521
 522         if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
 523                                       NULL, &fops_u64_wo)) {
 524                 debugfs_remove(i10nm_test);
 525                 i10nm_test = NULL;
 526         }
 527 }
 528
 529 static void teardown_i10nm_debug(void)
 530 {
 531         debugfs_remove_recursive(i10nm_test);
 532 }
 533 #else
 534 static inline void setup_i10nm_debug(void) {}
 535 static inline void teardown_i10nm_debug(void) {}
 536 #endif /*CONFIG_EDAC_DEBUG*/
 537
 538 static int __init i10nm_init(void)
 539 {
 540         u8 mc = 0, src_id = 0, node_id = 0;
 541         const struct x86_cpu_id *id;
 542         struct res_config *cfg;
 543         const char *owner;
 544         struct skx_dev *d;
 545         int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
 546         u64 tolm, tohm;
 547
 548         edac_dbg(2, "\n");
 549
 550         owner = edac_get_owner();
 551         if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
 552                 return -EBUSY;
 553
 554         if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
 555                 return -ENODEV;
 556
 557         id = x86_match_cpu(i10nm_cpuids);
 558         if (!id)
 559                 return -ENODEV;
 560
 561         cfg = (struct res_config *)id->driver_data;
 562         res_cfg = cfg;
 563
 564         rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
 565         if (rc)
 566                 return rc;
 567
 568         rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
 569         if (rc < 0)
 570                 goto fail;
 571         if (rc == 0) {
 572                 i10nm_printk(KERN_ERR, "No memory controllers found\n");
 573                 return -ENODEV;
 574         }
 575
 576         skx_set_mem_cfg(i10nm_check_2lm(cfg));
 577
 578         rc = i10nm_get_ddr_munits();
 579
 580         if (i10nm_get_hbm_munits() && rc)
 581                 goto fail;
 582
 583         list_for_each_entry(d, i10nm_edac_list, list) {
 584                 rc = skx_get_src_id(d, 0xf8, &src_id);
 585                 if (rc < 0)
 586                         goto fail;
 587
 588                 rc = skx_get_node_id(d, &node_id);
 589                 if (rc < 0)
 590                         goto fail;
 591
 592                 edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
 593                 for (i = 0; i < I10NM_NUM_IMC; i++) {
 594                         if (!d->imc[i].mdev)
 595                                 continue;
 596
 597                         d->imc[i].mc  = mc++;
 598                         d->imc[i].lmc = i;
 599                         d->imc[i].src_id  = src_id;
 600                         d->imc[i].node_id = node_id;
 601                         if (d->imc[i].hbm_mc) {
 602                                 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
 603                                 d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS;
 604                                 d->imc[i].num_dimms    = I10NM_NUM_HBM_DIMMS;
 605                         } else {
 606                                 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
 607                                 d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS;
 608                                 d->imc[i].num_dimms    = I10NM_NUM_DDR_DIMMS;
 609                         }
 610
 611                         rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
 612                                               "Intel_10nm Socket", EDAC_MOD_STR,
 613                                               i10nm_get_dimm_config, cfg);
 614                         if (rc < 0)
 615                                 goto fail;
 616                 }
 617         }
 618
 619         rc = skx_adxl_get();
 620         if (rc)
 621                 goto fail;
 622
 623         opstate_init();
 624         mce_register_decode_chain(&i10nm_mce_dec);
 625         setup_i10nm_debug();
 626
 627         if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
 628                 skx_set_decode(NULL, show_retry_rd_err_log);
 629                 if (retry_rd_err_log == 2)
 630                         enable_retry_rd_err_log(true);
 631         }
 632
 633         i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
 634
 635         return 0;
 636 fail:
 637         skx_remove();
 638         return rc;
 639 }
 640
 641 static void __exit i10nm_exit(void)
 642 {
 643         edac_dbg(2, "\n");
 644
 645         if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
 646                 skx_set_decode(NULL, NULL);
 647                 if (retry_rd_err_log == 2)
 648                         enable_retry_rd_err_log(false);
 649         }
 650
 651         teardown_i10nm_debug();
 652         mce_unregister_decode_chain(&i10nm_mce_dec);
 653         skx_adxl_put();
 654         skx_remove();
 655 }
 656
 657 module_init(i10nm_init);
 658 module_exit(i10nm_exit);
 659
 660 module_param(retry_rd_err_log, int, 0444);
 661 MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)");
 662
 663 MODULE_LICENSE("GPL v2");
 664 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");