drivers/edac/ghes_edac.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GHES/EDAC Linux driver
   4  *
   5  * Copyright (c) 2013 by Mauro Carvalho Chehab
   6  *
   7  * Red Hat Inc. https://www.redhat.com
   8  */
   9
  10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11
  12 #include <acpi/ghes.h>
  13 #include <linux/edac.h>
  14 #include <linux/dmi.h>
  15 #include "edac_module.h"
  16 #include <ras/ras_event.h>
  17
  18 #define OTHER_DETAIL_LEN        400
  19
  20 struct ghes_pvt {
  21         struct mem_ctl_info *mci;
  22
  23         /* Buffers for the error handling routine */
  24         char other_detail[OTHER_DETAIL_LEN];
  25         char msg[80];
  26 };
  27
  28 static refcount_t ghes_refcount = REFCOUNT_INIT(0);
  29
  30 /*
  31  * Access to ghes_pvt must be protected by ghes_lock. The spinlock
  32  * also provides the necessary (implicit) memory barrier for the SMP
  33  * case to make the pointer visible on another CPU.
  34  */
  35 static struct ghes_pvt *ghes_pvt;
  36
  37 /*
  38  * This driver's representation of the system hardware, as collected
  39  * from DMI.
  40  */
  41 static struct ghes_hw_desc {
  42         int num_dimms;
  43         struct dimm_info *dimms;
  44 } ghes_hw;
  45
  46 /* GHES registration mutex */
  47 static DEFINE_MUTEX(ghes_reg_mutex);
  48
  49 /*
  50  * Sync with other, potentially concurrent callers of
  51  * ghes_edac_report_mem_error(). We don't know what the
  52  * "inventive" firmware would do.
  53  */
  54 static DEFINE_SPINLOCK(ghes_lock);
  55
  56 /* "ghes_edac.force_load=1" skips the platform check */
  57 static bool __read_mostly force_load;
  58 module_param(force_load, bool, 0);
  59
  60 static bool system_scanned;
  61
  62 /* Memory Device - Type 17 of SMBIOS spec */
  63 struct memdev_dmi_entry {
  64         u8 type;
  65         u8 length;
  66         u16 handle;
  67         u16 phys_mem_array_handle;
  68         u16 mem_err_info_handle;
  69         u16 total_width;
  70         u16 data_width;
  71         u16 size;
  72         u8 form_factor;
  73         u8 device_set;
  74         u8 device_locator;
  75         u8 bank_locator;
  76         u8 memory_type;
  77         u16 type_detail;
  78         u16 speed;
  79         u8 manufacturer;
  80         u8 serial_number;
  81         u8 asset_tag;
  82         u8 part_number;
  83         u8 attributes;
  84         u32 extended_size;
  85         u16 conf_mem_clk_speed;
  86 } __attribute__((__packed__));
  87
  88 static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
  89 {
  90         struct dimm_info *dimm;
  91
  92         mci_for_each_dimm(mci, dimm) {
  93                 if (dimm->smbios_handle == handle)
  94                         return dimm;
  95         }
  96
  97         return NULL;
  98 }
  99
 100 static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
 101 {
 102         const char *bank = NULL, *device = NULL;
 103
 104         dmi_memdev_name(handle, &bank, &device);
 105
 106         /*
 107          * Set to a NULL string when both bank and device are zero. In this case,
 108          * the label assigned by default will be preserved.
 109          */
 110         snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
 111                  (bank && *bank) ? bank : "",
 112                  (bank && *bank && device && *device) ? " " : "",
 113                  (device && *device) ? device : "");
 114 }
 115
 116 static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
 117 {
 118         u16 rdr_mask = BIT(7) | BIT(13);
 119
 120         if (entry->size == 0xffff) {
 121                 pr_info("Can't get DIMM%i size\n", dimm->idx);
 122                 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
 123         } else if (entry->size == 0x7fff) {
 124                 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
 125         } else {
 126                 if (entry->size & BIT(15))
 127                         dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
 128                 else
 129                         dimm->nr_pages = MiB_TO_PAGES(entry->size);
 130         }
 131
 132         switch (entry->memory_type) {
 133         case 0x12:
 134                 if (entry->type_detail & BIT(13))
 135                         dimm->mtype = MEM_RDDR;
 136                 else
 137                         dimm->mtype = MEM_DDR;
 138                 break;
 139         case 0x13:
 140                 if (entry->type_detail & BIT(13))
 141                         dimm->mtype = MEM_RDDR2;
 142                 else
 143                         dimm->mtype = MEM_DDR2;
 144                 break;
 145         case 0x14:
 146                 dimm->mtype = MEM_FB_DDR2;
 147                 break;
 148         case 0x18:
 149                 if (entry->type_detail & BIT(12))
 150                         dimm->mtype = MEM_NVDIMM;
 151                 else if (entry->type_detail & BIT(13))
 152                         dimm->mtype = MEM_RDDR3;
 153                 else
 154                         dimm->mtype = MEM_DDR3;
 155                 break;
 156         case 0x1a:
 157                 if (entry->type_detail & BIT(12))
 158                         dimm->mtype = MEM_NVDIMM;
 159                 else if (entry->type_detail & BIT(13))
 160                         dimm->mtype = MEM_RDDR4;
 161                 else
 162                         dimm->mtype = MEM_DDR4;
 163                 break;
 164         default:
 165                 if (entry->type_detail & BIT(6))
 166                         dimm->mtype = MEM_RMBS;
 167                 else if ((entry->type_detail & rdr_mask) == rdr_mask)
 168                         dimm->mtype = MEM_RDR;
 169                 else if (entry->type_detail & BIT(7))
 170                         dimm->mtype = MEM_SDR;
 171                 else if (entry->type_detail & BIT(9))
 172                         dimm->mtype = MEM_EDO;
 173                 else
 174                         dimm->mtype = MEM_UNKNOWN;
 175         }
 176
 177         /*
 178          * Actually, we can only detect if the memory has bits for
 179          * checksum or not
 180          */
 181         if (entry->total_width == entry->data_width)
 182                 dimm->edac_mode = EDAC_NONE;
 183         else
 184                 dimm->edac_mode = EDAC_SECDED;
 185
 186         dimm->dtype = DEV_UNKNOWN;
 187         dimm->grain = 128;              /* Likely, worse case */
 188
 189         dimm_setup_label(dimm, entry->handle);
 190
 191         if (dimm->nr_pages) {
 192                 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
 193                         dimm->idx, edac_mem_types[dimm->mtype],
 194                         PAGES_TO_MiB(dimm->nr_pages),
 195                         (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
 196                 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
 197                         entry->memory_type, entry->type_detail,
 198                         entry->total_width, entry->data_width);
 199         }
 200
 201         dimm->smbios_handle = entry->handle;
 202 }
 203
 204 static void enumerate_dimms(const struct dmi_header *dh, void *arg)
 205 {
 206         struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
 207         struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
 208         struct dimm_info *d;
 209
 210         if (dh->type != DMI_ENTRY_MEM_DEVICE)
 211                 return;
 212
 213         /* Enlarge the array with additional 16 */
 214         if (!hw->num_dimms || !(hw->num_dimms % 16)) {
 215                 struct dimm_info *new;
 216
 217                 new = krealloc_array(hw->dimms, hw->num_dimms + 16,
 218                                      sizeof(struct dimm_info), GFP_KERNEL);
 219                 if (!new) {
 220                         WARN_ON_ONCE(1);
 221                         return;
 222                 }
 223
 224                 hw->dimms = new;
 225         }
 226
 227         d = &hw->dimms[hw->num_dimms];
 228         d->idx = hw->num_dimms;
 229
 230         assign_dmi_dimm_info(d, entry);
 231
 232         hw->num_dimms++;
 233 }
 234
 235 static void ghes_scan_system(void)
 236 {
 237         if (system_scanned)
 238                 return;
 239
 240         dmi_walk(enumerate_dimms, &ghes_hw);
 241
 242         system_scanned = true;
 243 }
 244
 245 static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
 246                                         const char *location, unsigned int len)
 247 {
 248         u32 n;
 249
 250         if (!msg)
 251                 return 0;
 252
 253         n = 0;
 254         len -= 1;
 255
 256         n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
 257
 258         if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
 259                 goto out;
 260
 261         n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
 262         n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
 263
 264 out:
 265         msg[n] = '\0';
 266
 267         return n;
 268 }
 269
 270 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
 271 {
 272         struct cper_mem_err_compact cmem;
 273         struct edac_raw_error_desc *e;
 274         struct mem_ctl_info *mci;
 275         struct ghes_pvt *pvt;
 276         unsigned long flags;
 277         char *p;
 278
 279         /*
 280          * We can do the locking below because GHES defers error processing
 281          * from NMI to IRQ context. Whenever that changes, we'd at least
 282          * know.
 283          */
 284         if (WARN_ON_ONCE(in_nmi()))
 285                 return;
 286
 287         spin_lock_irqsave(&ghes_lock, flags);
 288
 289         pvt = ghes_pvt;
 290         if (!pvt)
 291                 goto unlock;
 292
 293         mci = pvt->mci;
 294         e = &mci->error_desc;
 295
 296         /* Cleans the error report buffer */
 297         memset(e, 0, sizeof (*e));
 298         e->error_count = 1;
 299         e->grain = 1;
 300         e->msg = pvt->msg;
 301         e->other_detail = pvt->other_detail;
 302         e->top_layer = -1;
 303         e->mid_layer = -1;
 304         e->low_layer = -1;
 305         *pvt->other_detail = '\0';
 306         *pvt->msg = '\0';
 307
 308         switch (sev) {
 309         case GHES_SEV_CORRECTED:
 310                 e->type = HW_EVENT_ERR_CORRECTED;
 311                 break;
 312         case GHES_SEV_RECOVERABLE:
 313                 e->type = HW_EVENT_ERR_UNCORRECTED;
 314                 break;
 315         case GHES_SEV_PANIC:
 316                 e->type = HW_EVENT_ERR_FATAL;
 317                 break;
 318         default:
 319         case GHES_SEV_NO:
 320                 e->type = HW_EVENT_ERR_INFO;
 321         }
 322
 323         edac_dbg(1, "error validation_bits: 0x%08llx\n",
 324                  (long long)mem_err->validation_bits);
 325
 326         /* Error type, mapped on e->msg */
 327         if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
 328                 u8 etype = mem_err->error_type;
 329
 330                 p = pvt->msg;
 331                 p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
 332         } else {
 333                 strcpy(pvt->msg, "unknown error");
 334         }
 335
 336         /* Error address */
 337         if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
 338                 e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
 339                 e->offset_in_page = offset_in_page(mem_err->physical_addr);
 340         }
 341
 342         /* Error grain */
 343         if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
 344                 e->grain = ~mem_err->physical_addr_mask + 1;
 345
 346         /* Memory error location, mapped on e->location */
 347         p = e->location;
 348         cper_mem_err_pack(mem_err, &cmem);
 349         p += cper_mem_err_location(&cmem, p);
 350
 351         if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
 352                 struct dimm_info *dimm;
 353
 354                 p += cper_dimm_err_location(&cmem, p);
 355                 dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
 356                 if (dimm) {
 357                         e->top_layer = dimm->idx;
 358                         strcpy(e->label, dimm->label);
 359                 }
 360         }
 361         if (p > e->location)
 362                 *(p - 1) = '\0';
 363
 364         if (!*e->label)
 365                 strcpy(e->label, "unknown memory");
 366
 367         /* All other fields are mapped on e->other_detail */
 368         p = pvt->other_detail;
 369         p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
 370         if (p > pvt->other_detail)
 371                 *(p - 1) = '\0';
 372
 373         edac_raw_mc_handle_error(e);
 374
 375 unlock:
 376         spin_unlock_irqrestore(&ghes_lock, flags);
 377 }
 378
 379 /*
 380  * Known systems that are safe to enable this module.
 381  */
 382 static struct acpi_platform_list plat_list[] = {
 383         {"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},
 384         { } /* End */
 385 };
 386
 387 int ghes_edac_register(struct ghes *ghes, struct device *dev)
 388 {
 389         bool fake = false;
 390         struct mem_ctl_info *mci;
 391         struct ghes_pvt *pvt;
 392         struct edac_mc_layer layers[1];
 393         unsigned long flags;
 394         int idx = -1;
 395         int rc = 0;
 396
 397         if (IS_ENABLED(CONFIG_X86)) {
 398                 /* Check if safe to enable on this system */
 399                 idx = acpi_match_platform_list(plat_list);
 400                 if (!force_load && idx < 0)
 401                         return -ENODEV;
 402         } else {
 403                 force_load = true;
 404                 idx = 0;
 405         }
 406
 407         /* finish another registration/unregistration instance first */
 408         mutex_lock(&ghes_reg_mutex);
 409
 410         /*
 411          * We have only one logical memory controller to which all DIMMs belong.
 412          */
 413         if (refcount_inc_not_zero(&ghes_refcount))
 414                 goto unlock;
 415
 416         ghes_scan_system();
 417
 418         /* Check if we've got a bogus BIOS */
 419         if (!ghes_hw.num_dimms) {
 420                 fake = true;
 421                 ghes_hw.num_dimms = 1;
 422         }
 423
 424         layers[0].type = EDAC_MC_LAYER_ALL_MEM;
 425         layers[0].size = ghes_hw.num_dimms;
 426         layers[0].is_virt_csrow = true;
 427
 428         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
 429         if (!mci) {
 430                 pr_info("Can't allocate memory for EDAC data\n");
 431                 rc = -ENOMEM;
 432                 goto unlock;
 433         }
 434
 435         pvt             = mci->pvt_info;
 436         pvt->mci        = mci;
 437
 438         mci->pdev = dev;
 439         mci->mtype_cap = MEM_FLAG_EMPTY;
 440         mci->edac_ctl_cap = EDAC_FLAG_NONE;
 441         mci->edac_cap = EDAC_FLAG_NONE;
 442         mci->mod_name = "ghes_edac.c";
 443         mci->ctl_name = "ghes_edac";
 444         mci->dev_name = "ghes";
 445
 446         if (fake) {
 447                 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
 448                 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
 449                 pr_info("work on such system. Use this driver with caution\n");
 450         } else if (idx < 0) {
 451                 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
 452                 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
 453                 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
 454                 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
 455                 pr_info("to correct its BIOS.\n");
 456                 pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
 457         }
 458
 459         if (!fake) {
 460                 struct dimm_info *src, *dst;
 461                 int i = 0;
 462
 463                 mci_for_each_dimm(mci, dst) {
 464                         src = &ghes_hw.dimms[i];
 465
 466                         dst->idx           = src->idx;
 467                         dst->smbios_handle = src->smbios_handle;
 468                         dst->nr_pages      = src->nr_pages;
 469                         dst->mtype         = src->mtype;
 470                         dst->edac_mode     = src->edac_mode;
 471                         dst->dtype         = src->dtype;
 472                         dst->grain         = src->grain;
 473
 474                         /*
 475                          * If no src->label, preserve default label assigned
 476                          * from EDAC core.
 477                          */
 478                         if (strlen(src->label))
 479                                 memcpy(dst->label, src->label, sizeof(src->label));
 480
 481                         i++;
 482                 }
 483
 484         } else {
 485                 struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
 486
 487                 dimm->nr_pages = 1;
 488                 dimm->grain = 128;
 489                 dimm->mtype = MEM_UNKNOWN;
 490                 dimm->dtype = DEV_UNKNOWN;
 491                 dimm->edac_mode = EDAC_SECDED;
 492         }
 493
 494         rc = edac_mc_add_mc(mci);
 495         if (rc < 0) {
 496                 pr_info("Can't register with the EDAC core\n");
 497                 edac_mc_free(mci);
 498                 rc = -ENODEV;
 499                 goto unlock;
 500         }
 501
 502         spin_lock_irqsave(&ghes_lock, flags);
 503         ghes_pvt = pvt;
 504         spin_unlock_irqrestore(&ghes_lock, flags);
 505
 506         /* only set on success */
 507         refcount_set(&ghes_refcount, 1);
 508
 509 unlock:
 510
 511         /* Not needed anymore */
 512         kfree(ghes_hw.dimms);
 513         ghes_hw.dimms = NULL;
 514
 515         mutex_unlock(&ghes_reg_mutex);
 516
 517         return rc;
 518 }
 519
 520 void ghes_edac_unregister(struct ghes *ghes)
 521 {
 522         struct mem_ctl_info *mci;
 523         unsigned long flags;
 524
 525         if (!force_load)
 526                 return;
 527
 528         mutex_lock(&ghes_reg_mutex);
 529
 530         system_scanned = false;
 531         memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
 532
 533         if (!refcount_dec_and_test(&ghes_refcount))
 534                 goto unlock;
 535
 536         /*
 537          * Wait for the irq handler being finished.
 538          */
 539         spin_lock_irqsave(&ghes_lock, flags);
 540         mci = ghes_pvt ? ghes_pvt->mci : NULL;
 541         ghes_pvt = NULL;
 542         spin_unlock_irqrestore(&ghes_lock, flags);
 543
 544         if (!mci)
 545                 goto unlock;
 546
 547         mci = edac_mc_del_mc(mci->pdev);
 548         if (mci)
 549                 edac_mc_free(mci);
 550
 551 unlock:
 552         mutex_unlock(&ghes_reg_mutex);
 553 }