1 #include "amd64_edac.h"
2 #include <asm/amd_nb.h>
4 static struct edac_pci_ctl_info *amd64_ctl_pci;
6 static int report_gart_errors;
7 module_param(report_gart_errors, int, 0644);
10 * Set by command line parameter. If BIOS has enabled the ECC, this override is
11 * cleared to prevent re-enabling the hardware by this driver.
13 static int ecc_enable_override;
14 module_param(ecc_enable_override, int, 0644);
16 static struct msr __percpu *msrs;
19 * count successfully initialized driver instances for setup_pci_device()
21 static atomic_t drv_instances = ATOMIC_INIT(0);
23 /* Per-node driver instances */
24 static struct mem_ctl_info **mcis;
25 static struct ecc_settings **ecc_stngs;
28 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
29 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
32 *FIXME: Produce a better mapping/linearisation.
34 static const struct scrubrate {
35 u32 scrubval; /* bit pattern for scrub rate */
36 u32 bandwidth; /* bandwidth consumed (bytes/sec) */
38 { 0x01, 1600000000UL},
60 { 0x00, 0UL}, /* scrubbing off */
63 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
64 u32 *val, const char *func)
68 err = pci_read_config_dword(pdev, offset, val);
70 amd64_warn("%s: error reading F%dx%03x.\n",
71 func, PCI_FUNC(pdev->devfn), offset);
76 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
77 u32 val, const char *func)
81 err = pci_write_config_dword(pdev, offset, val);
83 amd64_warn("%s: error writing to F%dx%03x.\n",
84 func, PCI_FUNC(pdev->devfn), offset);
91 * Depending on the family, F2 DCT reads need special handling:
93 * K8: has a single DCT only
95 * F10h: each DCT has its own set of regs
99 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
102 static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
108 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
111 static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
114 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
118 * Select DCT to which PCI cfg accesses are routed
120 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
124 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
127 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
130 static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
135 if (addr >= 0x140 && addr <= 0x1a0) {
140 f15h_select_dct(pvt, dct);
142 return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
146 * Memory scrubber control interface. For K8, memory scrubbing is handled by
147 * hardware and can involve L2 cache, dcache as well as the main memory. With
148 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
151 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
152 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
153 * bytes/sec for the setting.
155 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
156 * other archs, we might not have access to the caches directly.
160 * scan the scrub rate mapping table for a close or matching bandwidth value to
161 * issue. If requested is too big, then use last maximum value found.
163 static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
169 * map the configured rate (new_bw) to a value specific to the AMD64
170 * memory controller and apply to register. Search for the first
171 * bandwidth entry that is greater or equal than the setting requested
172 * and program that. If at last entry, turn off DRAM scrubbing.
174 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
175 * by falling back to the last element in scrubrates[].
177 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
179 * skip scrub rates which aren't recommended
180 * (see F10 BKDG, F3x58)
182 if (scrubrates[i].scrubval < min_rate)
185 if (scrubrates[i].bandwidth <= new_bw)
189 scrubval = scrubrates[i].scrubval;
191 pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
194 return scrubrates[i].bandwidth;
199 static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
201 struct amd64_pvt *pvt = mci->pvt_info;
202 u32 min_scrubrate = 0x5;
204 if (boot_cpu_data.x86 == 0xf)
207 /* F15h Erratum #505 */
208 if (boot_cpu_data.x86 == 0x15)
209 f15h_select_dct(pvt, 0);
211 return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
214 static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
216 struct amd64_pvt *pvt = mci->pvt_info;
218 int i, retval = -EINVAL;
220 /* F15h Erratum #505 */
221 if (boot_cpu_data.x86 == 0x15)
222 f15h_select_dct(pvt, 0);
224 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
226 scrubval = scrubval & 0x001F;
228 for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
229 if (scrubrates[i].scrubval == scrubval) {
230 retval = scrubrates[i].bandwidth;
238 * returns true if the SysAddr given by sys_addr matches the
239 * DRAM base/limit associated with node_id
241 static bool amd64_base_limit_match(struct amd64_pvt *pvt, u64 sys_addr,
246 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
247 * all ones if the most significant implemented address bit is 1.
248 * Here we discard bits 63-40. See section 3.4.2 of AMD publication
249 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
250 * Application Programming.
252 addr = sys_addr & 0x000000ffffffffffull;
254 return ((addr >= get_dram_base(pvt, nid)) &&
255 (addr <= get_dram_limit(pvt, nid)));
259 * Attempt to map a SysAddr to a node. On success, return a pointer to the
260 * mem_ctl_info structure for the node that the SysAddr maps to.
262 * On failure, return NULL.
264 static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
267 struct amd64_pvt *pvt;
272 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
273 * 3.4.4.2) registers to map the SysAddr to a node ID.
278 * The value of this field should be the same for all DRAM Base
279 * registers. Therefore we arbitrarily choose to read it from the
280 * register for node 0.
282 intlv_en = dram_intlv_en(pvt, 0);
285 for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
286 if (amd64_base_limit_match(pvt, sys_addr, node_id))
292 if (unlikely((intlv_en != 0x01) &&
293 (intlv_en != 0x03) &&
294 (intlv_en != 0x07))) {
295 amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
299 bits = (((u32) sys_addr) >> 12) & intlv_en;
301 for (node_id = 0; ; ) {
302 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
303 break; /* intlv_sel field matches */
305 if (++node_id >= DRAM_RANGES)
309 /* sanity test for sys_addr */
310 if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
311 amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
312 "range for node %d with node interleaving enabled.\n",
313 __func__, sys_addr, node_id);
318 return edac_mc_find((int)node_id);
321 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
322 (unsigned long)sys_addr);
328 * compute the CS base address of the @csrow on the DRAM controller @dct.
329 * For details see F2x[5C:40] in the processor's BKDG
331 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
332 u64 *base, u64 *mask)
334 u64 csbase, csmask, base_bits, mask_bits;
337 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
338 csbase = pvt->csels[dct].csbases[csrow];
339 csmask = pvt->csels[dct].csmasks[csrow];
340 base_bits = GENMASK(21, 31) | GENMASK(9, 15);
341 mask_bits = GENMASK(21, 29) | GENMASK(9, 15);
344 csbase = pvt->csels[dct].csbases[csrow];
345 csmask = pvt->csels[dct].csmasks[csrow >> 1];
348 if (boot_cpu_data.x86 == 0x15)
349 base_bits = mask_bits = GENMASK(19,30) | GENMASK(5,13);
351 base_bits = mask_bits = GENMASK(19,28) | GENMASK(5,13);
354 *base = (csbase & base_bits) << addr_shift;
357 /* poke holes for the csmask */
358 *mask &= ~(mask_bits << addr_shift);
360 *mask |= (csmask & mask_bits) << addr_shift;
363 #define for_each_chip_select(i, dct, pvt) \
364 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
366 #define chip_select_base(i, dct, pvt) \
367 pvt->csels[dct].csbases[i]
369 #define for_each_chip_select_mask(i, dct, pvt) \
370 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
373 * @input_addr is an InputAddr associated with the node given by mci. Return the
374 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
376 static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
378 struct amd64_pvt *pvt;
384 for_each_chip_select(csrow, 0, pvt) {
385 if (!csrow_enabled(csrow, 0, pvt))
388 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
392 if ((input_addr & mask) == (base & mask)) {
393 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
394 (unsigned long)input_addr, csrow,
400 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
401 (unsigned long)input_addr, pvt->mc_node_id);
407 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
408 * for the node represented by mci. Info is passed back in *hole_base,
409 * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
410 * info is invalid. Info may be invalid for either of the following reasons:
412 * - The revision of the node is not E or greater. In this case, the DRAM Hole
413 * Address Register does not exist.
415 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
416 * indicating that its contents are not valid.
418 * The values passed back in *hole_base, *hole_offset, and *hole_size are
419 * complete 32-bit values despite the fact that the bitfields in the DHAR
420 * only represent bits 31-24 of the base and offset values.
422 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
423 u64 *hole_offset, u64 *hole_size)
425 struct amd64_pvt *pvt = mci->pvt_info;
427 /* only revE and later have the DRAM Hole Address Register */
428 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {
429 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
430 pvt->ext_model, pvt->mc_node_id);
434 /* valid for Fam10h and above */
435 if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
436 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
440 if (!dhar_valid(pvt)) {
441 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
446 /* This node has Memory Hoisting */
448 /* +------------------+--------------------+--------------------+-----
449 * | memory | DRAM hole | relocated |
450 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
452 * | | | [0x100000000, |
453 * | | | (0x100000000+ |
454 * | | | (0xffffffff-x))] |
455 * +------------------+--------------------+--------------------+-----
457 * Above is a diagram of physical memory showing the DRAM hole and the
458 * relocated addresses from the DRAM hole. As shown, the DRAM hole
459 * starts at address x (the base address) and extends through address
460 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
461 * addresses in the hole so that they start at 0x100000000.
464 *hole_base = dhar_base(pvt);
465 *hole_size = (1ULL << 32) - *hole_base;
467 if (boot_cpu_data.x86 > 0xf)
468 *hole_offset = f10_dhar_offset(pvt);
470 *hole_offset = k8_dhar_offset(pvt);
472 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
473 pvt->mc_node_id, (unsigned long)*hole_base,
474 (unsigned long)*hole_offset, (unsigned long)*hole_size);
478 EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);
481 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
482 * assumed that sys_addr maps to the node given by mci.
484 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
485 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
486 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
487 * then it is also involved in translating a SysAddr to a DramAddr. Sections
488 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
489 * These parts of the documentation are unclear. I interpret them as follows:
491 * When node n receives a SysAddr, it processes the SysAddr as follows:
493 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
494 * Limit registers for node n. If the SysAddr is not within the range
495 * specified by the base and limit values, then node n ignores the Sysaddr
496 * (since it does not map to node n). Otherwise continue to step 2 below.
498 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
499 * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
500 * the range of relocated addresses (starting at 0x100000000) from the DRAM
501 * hole. If not, skip to step 3 below. Else get the value of the
502 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
503 * offset defined by this value from the SysAddr.
505 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
506 * Base register for node n. To obtain the DramAddr, subtract the base
507 * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
509 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
511 struct amd64_pvt *pvt = mci->pvt_info;
512 u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
515 dram_base = get_dram_base(pvt, pvt->mc_node_id);
517 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
520 if ((sys_addr >= (1ULL << 32)) &&
521 (sys_addr < ((1ULL << 32) + hole_size))) {
522 /* use DHAR to translate SysAddr to DramAddr */
523 dram_addr = sys_addr - hole_offset;
525 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
526 (unsigned long)sys_addr,
527 (unsigned long)dram_addr);
534 * Translate the SysAddr to a DramAddr as shown near the start of
535 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
536 * only deals with 40-bit values. Therefore we discard bits 63-40 of
537 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
538 * discard are all 1s. Otherwise the bits we discard are all 0s. See
539 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
540 * Programmer's Manual Volume 1 Application Programming.
542 dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;
544 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
545 (unsigned long)sys_addr, (unsigned long)dram_addr);
550 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
551 * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
552 * for node interleaving.
554 static int num_node_interleave_bits(unsigned intlv_en)
556 static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
559 BUG_ON(intlv_en > 7);
560 n = intlv_shift_table[intlv_en];
564 /* Translate the DramAddr given by @dram_addr to an InputAddr. */
565 static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
567 struct amd64_pvt *pvt;
574 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
575 * concerning translating a DramAddr to an InputAddr.
577 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
578 input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
581 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
582 intlv_shift, (unsigned long)dram_addr,
583 (unsigned long)input_addr);
589 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
590 * assumed that @sys_addr maps to the node given by mci.
592 static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
597 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
599 edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
600 (unsigned long)sys_addr, (unsigned long)input_addr);
607 * @input_addr is an InputAddr associated with the node represented by mci.
608 * Translate @input_addr to a DramAddr and return the result.
610 static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
612 struct amd64_pvt *pvt;
613 unsigned node_id, intlv_shift;
618 * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
619 * shows how to translate a DramAddr to an InputAddr. Here we reverse
620 * this procedure. When translating from a DramAddr to an InputAddr, the
621 * bits used for node interleaving are discarded. Here we recover these
622 * bits from the IntlvSel field of the DRAM Limit register (section
623 * 3.4.4.2) for the node that input_addr is associated with.
626 node_id = pvt->mc_node_id;
630 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
631 if (intlv_shift == 0) {
632 edac_dbg(1, " InputAddr 0x%lx translates to DramAddr of same value\n",
633 (unsigned long)input_addr);
638 bits = ((input_addr & GENMASK(12, 35)) << intlv_shift) +
639 (input_addr & 0xfff);
641 intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);
642 dram_addr = bits + (intlv_sel << 12);
644 edac_dbg(1, "InputAddr 0x%lx translates to DramAddr 0x%lx (%d node interleave bits)\n",
645 (unsigned long)input_addr,
646 (unsigned long)dram_addr, intlv_shift);
652 * @dram_addr is a DramAddr that maps to the node represented by mci. Convert
653 * @dram_addr to a SysAddr.
655 static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
657 struct amd64_pvt *pvt = mci->pvt_info;
658 u64 hole_base, hole_offset, hole_size, base, sys_addr;
661 ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
664 if ((dram_addr >= hole_base) &&
665 (dram_addr < (hole_base + hole_size))) {
666 sys_addr = dram_addr + hole_offset;
668 edac_dbg(1, "using DHAR to translate DramAddr 0x%lx to SysAddr 0x%lx\n",
669 (unsigned long)dram_addr,
670 (unsigned long)sys_addr);
676 base = get_dram_base(pvt, pvt->mc_node_id);
677 sys_addr = dram_addr + base;
680 * The sys_addr we have computed up to this point is a 40-bit value
681 * because the k8 deals with 40-bit values. However, the value we are
682 * supposed to return is a full 64-bit physical address. The AMD
683 * x86-64 architecture specifies that the most significant implemented
684 * address bit through bit 63 of a physical address must be either all
685 * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a
686 * 64-bit value below. See section 3.4.2 of AMD publication 24592:
687 * AMD x86-64 Architecture Programmer's Manual Volume 1 Application
690 sys_addr |= ~((sys_addr & (1ull << 39)) - 1);
692 edac_dbg(1, " Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
693 pvt->mc_node_id, (unsigned long)dram_addr,
694 (unsigned long)sys_addr);
700 * @input_addr is an InputAddr associated with the node given by mci. Translate
701 * @input_addr to a SysAddr.
703 static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci,
706 return dram_addr_to_sys_addr(mci,
707 input_addr_to_dram_addr(mci, input_addr));
710 /* Map the Error address to a PAGE and PAGE OFFSET. */
711 static inline void error_address_to_page_and_offset(u64 error_address,
712 struct err_info *err)
714 err->page = (u32) (error_address >> PAGE_SHIFT);
715 err->offset = ((u32) error_address) & ~PAGE_MASK;
719 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
720 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
721 * of a node that detected an ECC memory error. mci represents the node that
722 * the error address maps to (possibly different from the node that detected
723 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
726 static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
730 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
733 amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
734 "address 0x%lx\n", (unsigned long)sys_addr);
738 static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
741 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
744 static unsigned long amd64_determine_edac_cap(struct amd64_pvt *pvt)
747 unsigned long edac_cap = EDAC_FLAG_NONE;
749 bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F)
753 if (pvt->dclr0 & BIT(bit))
754 edac_cap = EDAC_FLAG_SECDED;
759 static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
761 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
763 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
765 edac_dbg(1, " DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
766 (dclr & BIT(16)) ? "un" : "",
767 (dclr & BIT(19)) ? "yes" : "no");
769 edac_dbg(1, " PAR/ERR parity: %s\n",
770 (dclr & BIT(8)) ? "enabled" : "disabled");
772 if (boot_cpu_data.x86 == 0x10)
773 edac_dbg(1, " DCT 128bit mode width: %s\n",
774 (dclr & BIT(11)) ? "128b" : "64b");
776 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
777 (dclr & BIT(12)) ? "yes" : "no",
778 (dclr & BIT(13)) ? "yes" : "no",
779 (dclr & BIT(14)) ? "yes" : "no",
780 (dclr & BIT(15)) ? "yes" : "no");
783 /* Display and decode various NB registers for debug purposes. */
784 static void dump_misc_regs(struct amd64_pvt *pvt)
786 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
788 edac_dbg(1, " NB two channel DRAM capable: %s\n",
789 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
791 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
792 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
793 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
795 amd64_dump_dramcfg_low(pvt->dclr0, 0);
797 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
799 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
800 pvt->dhar, dhar_base(pvt),
801 (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
802 : f10_dhar_offset(pvt));
804 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
806 amd64_debug_display_dimm_sizes(pvt, 0);
808 /* everything below this point is Fam10h and above */
809 if (boot_cpu_data.x86 == 0xf)
812 amd64_debug_display_dimm_sizes(pvt, 1);
814 amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
816 /* Only if NOT ganged does dclr1 have valid info */
817 if (!dct_ganging_enabled(pvt))
818 amd64_dump_dramcfg_low(pvt->dclr1, 1);
822 * see BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
824 static void prep_chip_selects(struct amd64_pvt *pvt)
826 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) {
827 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
828 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
830 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
831 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
836 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
838 static void read_dct_base_mask(struct amd64_pvt *pvt)
842 prep_chip_selects(pvt);
844 for_each_chip_select(cs, 0, pvt) {
845 int reg0 = DCSB0 + (cs * 4);
846 int reg1 = DCSB1 + (cs * 4);
847 u32 *base0 = &pvt->csels[0].csbases[cs];
848 u32 *base1 = &pvt->csels[1].csbases[cs];
850 if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
851 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
854 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
857 if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
858 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
862 for_each_chip_select_mask(cs, 0, pvt) {
863 int reg0 = DCSM0 + (cs * 4);
864 int reg1 = DCSM1 + (cs * 4);
865 u32 *mask0 = &pvt->csels[0].csmasks[cs];
866 u32 *mask1 = &pvt->csels[1].csmasks[cs];
868 if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
869 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
872 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
875 if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
876 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
881 static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt, int cs)
885 /* F15h supports only DDR3 */
886 if (boot_cpu_data.x86 >= 0x15)
887 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
888 else if (boot_cpu_data.x86 == 0x10 || pvt->ext_model >= K8_REV_F) {
889 if (pvt->dchr0 & DDR3_MODE)
890 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
892 type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
894 type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
897 amd64_info("CS%d: %s\n", cs, edac_mem_types[type]);
902 /* Get the number of DCT channels the memory controller is using. */
903 static int k8_early_channel_count(struct amd64_pvt *pvt)
907 if (pvt->ext_model >= K8_REV_F)
908 /* RevF (NPT) and later */
909 flag = pvt->dclr0 & WIDTH_128;
911 /* RevE and earlier */
912 flag = pvt->dclr0 & REVE_WIDTH_128;
917 return (flag) ? 2 : 1;
920 /* On F10h and later ErrAddr is MC4_ADDR[47:1] */
921 static u64 get_error_address(struct mce *m)
923 struct cpuinfo_x86 *c = &boot_cpu_data;
933 addr = m->addr & GENMASK(start_bit, end_bit);
936 * Erratum 637 workaround
938 if (c->x86 == 0x15) {
939 struct amd64_pvt *pvt;
940 u64 cc6_base, tmp_addr;
945 if ((addr & GENMASK(24, 47)) >> 24 != 0x00fdf7)
948 mce_nid = amd_get_nb_id(m->extcpu);
949 pvt = mcis[mce_nid]->pvt_info;
951 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
952 intlv_en = tmp >> 21 & 0x7;
954 /* add [47:27] + 3 trailing bits */
955 cc6_base = (tmp & GENMASK(0, 20)) << 3;
957 /* reverse and add DramIntlvEn */
958 cc6_base |= intlv_en ^ 0x7;
964 return cc6_base | (addr & GENMASK(0, 23));
966 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
969 tmp_addr = (addr & GENMASK(12, 23)) << __fls(intlv_en + 1);
971 /* OR DramIntlvSel into bits [14:12] */
972 tmp_addr |= (tmp & GENMASK(21, 23)) >> 9;
974 /* add remaining [11:0] bits from original MC4_ADDR */
975 tmp_addr |= addr & GENMASK(0, 11);
977 return cc6_base | tmp_addr;
983 static struct pci_dev *pci_get_related_function(unsigned int vendor,
985 struct pci_dev *related)
987 struct pci_dev *dev = NULL;
989 while ((dev = pci_get_device(vendor, device, dev))) {
990 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
991 (dev->bus->number == related->bus->number) &&
992 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
999 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1001 struct amd_northbridge *nb;
1002 struct pci_dev *misc, *f1 = NULL;
1003 struct cpuinfo_x86 *c = &boot_cpu_data;
1004 int off = range << 3;
1007 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
1008 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1013 if (!dram_rw(pvt, range))
1016 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
1017 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1019 /* F15h: factor in CC6 save area by reading dst node's limit reg */
1023 nb = node_to_amd_nb(dram_dst_node(pvt, range));
1028 f1 = pci_get_related_function(misc->vendor, PCI_DEVICE_ID_AMD_15H_NB_F1, misc);
1032 amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1034 pvt->ranges[range].lim.lo &= GENMASK(0, 15);
1036 /* {[39:27],111b} */
1037 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1039 pvt->ranges[range].lim.hi &= GENMASK(0, 7);
1042 pvt->ranges[range].lim.hi |= llim >> 13;
1047 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1048 struct err_info *err)
1050 struct amd64_pvt *pvt = mci->pvt_info;
1052 error_address_to_page_and_offset(sys_addr, err);
1055 * Find out which node the error address belongs to. This may be
1056 * different from the node that detected the error.
1058 err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
1059 if (!err->src_mci) {
1060 amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
1061 (unsigned long)sys_addr);
1062 err->err_code = ERR_NODE;
1066 /* Now map the sys_addr to a CSROW */
1067 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
1068 if (err->csrow < 0) {
1069 err->err_code = ERR_CSROW;
1073 /* CHIPKILL enabled */
1074 if (pvt->nbcfg & NBCFG_CHIPKILL) {
1075 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
1076 if (err->channel < 0) {
1078 * Syndrome didn't map, so we don't know which of the
1079 * 2 DIMMs is in error. So we need to ID 'both' of them
1082 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1083 "possible error reporting race\n",
1085 err->err_code = ERR_CHANNEL;
1090 * non-chipkill ecc mode
1092 * The k8 documentation is unclear about how to determine the
1093 * channel number when using non-chipkill memory. This method
1094 * was obtained from email communication with someone at AMD.
1095 * (Wish the email was placed in this comment - norsk)
1097 err->channel = ((sys_addr & BIT(3)) != 0);
1101 static int ddr2_cs_size(unsigned i, bool dct_width)
1107 else if (!(i & 0x1))
1110 shift = (i + 1) >> 1;
1112 return 128 << (shift + !!dct_width);
1115 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1118 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1120 if (pvt->ext_model >= K8_REV_F) {
1121 WARN_ON(cs_mode > 11);
1122 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1124 else if (pvt->ext_model >= K8_REV_D) {
1126 WARN_ON(cs_mode > 10);
1129 * the below calculation, besides trying to win an obfuscated C
1130 * contest, maps cs_mode values to DIMM chip select sizes. The
1133 * cs_mode CS size (mb)
1134 * ======= ============
1147 * Basically, it calculates a value with which to shift the
1148 * smallest CS size of 32MB.
1150 * ddr[23]_cs_size have a similar purpose.
1152 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
1154 return 32 << (cs_mode - diff);
1157 WARN_ON(cs_mode > 6);
1158 return 32 << cs_mode;
1163 * Get the number of DCT channels in use.
1166 * number of Memory Channels in operation
1168 * contents of the DCL0_LOW register
1170 static int f1x_early_channel_count(struct amd64_pvt *pvt)
1172 int i, j, channels = 0;
1174 /* On F10h, if we are in 128 bit mode, then we are using 2 channels */
1175 if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & WIDTH_128))
1179 * Need to check if in unganged mode: In such, there are 2 channels,
1180 * but they are not in 128 bit mode and thus the above 'dclr0' status
1183 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1184 * their CSEnable bit on. If so, then SINGLE DIMM case.
1186 edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1189 * Check DRAM Bank Address Mapping values for each DIMM to see if there
1190 * is more than just one DIMM present in unganged mode. Need to check
1191 * both controllers since DIMMs can be placed in either one.
1193 for (i = 0; i < 2; i++) {
1194 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
1196 for (j = 0; j < 4; j++) {
1197 if (DBAM_DIMM(j, dbam) > 0) {
1207 amd64_info("MCT channel count: %d\n", channels);
1212 static int ddr3_cs_size(unsigned i, bool dct_width)
1217 if (i == 0 || i == 3 || i == 4)
1223 else if (!(i & 0x1))
1226 shift = (i + 1) >> 1;
1229 cs_size = (128 * (1 << !!dct_width)) << shift;
1234 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1237 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
1239 WARN_ON(cs_mode > 11);
1241 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
1242 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
1244 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
1248 * F15h supports only 64bit DCT interfaces
1250 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1253 WARN_ON(cs_mode > 12);
1255 return ddr3_cs_size(cs_mode, false);
1258 static void read_dram_ctl_register(struct amd64_pvt *pvt)
1261 if (boot_cpu_data.x86 == 0xf)
1264 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1265 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
1266 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1268 edac_dbg(0, " DCTs operate in %s mode\n",
1269 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1271 if (!dct_ganging_enabled(pvt))
1272 edac_dbg(0, " Address range split per DCT: %s\n",
1273 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1275 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
1276 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
1277 (dct_memory_cleared(pvt) ? "yes" : "no"));
1279 edac_dbg(0, " channel interleave: %s, "
1280 "interleave bits selector: 0x%x\n",
1281 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
1282 dct_sel_interleave_addr(pvt));
1285 amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
1289 * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
1290 * Interleaving Modes.
1292 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
1293 bool hi_range_sel, u8 intlv_en)
1295 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
1297 if (dct_ganging_enabled(pvt))
1301 return dct_sel_high;
1304 * see F2x110[DctSelIntLvAddr] - channel interleave mode
1306 if (dct_interleave_enabled(pvt)) {
1307 u8 intlv_addr = dct_sel_interleave_addr(pvt);
1309 /* return DCT select function: 0=DCT0, 1=DCT1 */
1311 return sys_addr >> 6 & 1;
1313 if (intlv_addr & 0x2) {
1314 u8 shift = intlv_addr & 0x1 ? 9 : 6;
1315 u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
1317 return ((sys_addr >> shift) & 1) ^ temp;
1320 return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
1323 if (dct_high_range_enabled(pvt))
1324 return ~dct_sel_high & 1;
1329 /* Convert the sys_addr to the normalized DCT address */
1330 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
1331 u64 sys_addr, bool hi_rng,
1332 u32 dct_sel_base_addr)
1335 u64 dram_base = get_dram_base(pvt, range);
1336 u64 hole_off = f10_dhar_offset(pvt);
1337 u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
1342 * base address of high range is below 4Gb
1343 * (bits [47:27] at [31:11])
1344 * DRAM address space on this DCT is hoisted above 4Gb &&
1347 * remove hole offset from sys_addr
1349 * remove high range offset from sys_addr
1351 if ((!(dct_sel_base_addr >> 16) ||
1352 dct_sel_base_addr < dhar_base(pvt)) &&
1354 (sys_addr >= BIT_64(32)))
1355 chan_off = hole_off;
1357 chan_off = dct_sel_base_off;
1361 * we have a valid hole &&
1366 * remove dram base to normalize to DCT address
1368 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
1369 chan_off = hole_off;
1371 chan_off = dram_base;
1374 return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47));
1378 * checks if the csrow passed in is marked as SPARED, if so returns the new
1381 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
1385 if (online_spare_swap_done(pvt, dct) &&
1386 csrow == online_spare_bad_dramcs(pvt, dct)) {
1388 for_each_chip_select(tmp_cs, dct, pvt) {
1389 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
1399 * Iterate over the DRAM DCT "base" and "mask" registers looking for a
1400 * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
1403 * -EINVAL: NOT FOUND
1404 * 0..csrow = Chip-Select Row
1406 static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
1408 struct mem_ctl_info *mci;
1409 struct amd64_pvt *pvt;
1410 u64 cs_base, cs_mask;
1411 int cs_found = -EINVAL;
1418 pvt = mci->pvt_info;
1420 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1422 for_each_chip_select(csrow, dct, pvt) {
1423 if (!csrow_enabled(csrow, dct, pvt))
1426 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1428 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
1429 csrow, cs_base, cs_mask);
1433 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
1434 (in_addr & cs_mask), (cs_base & cs_mask));
1436 if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1437 cs_found = f10_process_possible_spare(pvt, dct, csrow);
1439 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1447 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
1448 * swapped with a region located at the bottom of memory so that the GPU can use
1449 * the interleaved region and thus two channels.
1451 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
1453 u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
1455 if (boot_cpu_data.x86 == 0x10) {
1456 /* only revC3 and revE have that feature */
1457 if (boot_cpu_data.x86_model < 4 ||
1458 (boot_cpu_data.x86_model < 0xa &&
1459 boot_cpu_data.x86_mask < 3))
1463 amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg);
1465 if (!(swap_reg & 0x1))
1468 swap_base = (swap_reg >> 3) & 0x7f;
1469 swap_limit = (swap_reg >> 11) & 0x7f;
1470 rgn_size = (swap_reg >> 20) & 0x7f;
1471 tmp_addr = sys_addr >> 27;
1473 if (!(sys_addr >> 34) &&
1474 (((tmp_addr >= swap_base) &&
1475 (tmp_addr <= swap_limit)) ||
1476 (tmp_addr < rgn_size)))
1477 return sys_addr ^ (u64)swap_base << 27;
1482 /* For a given @dram_range, check if @sys_addr falls within it. */
1483 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1484 u64 sys_addr, int *chan_sel)
1486 int cs_found = -EINVAL;
1490 bool high_range = false;
1492 u8 node_id = dram_dst_node(pvt, range);
1493 u8 intlv_en = dram_intlv_en(pvt, range);
1494 u32 intlv_sel = dram_intlv_sel(pvt, range);
1496 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
1497 range, sys_addr, get_dram_limit(pvt, range));
1499 if (dhar_valid(pvt) &&
1500 dhar_base(pvt) <= sys_addr &&
1501 sys_addr < BIT_64(32)) {
1502 amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
1507 if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
1510 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
1512 dct_sel_base = dct_sel_baseaddr(pvt);
1515 * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
1516 * select between DCT0 and DCT1.
1518 if (dct_high_range_enabled(pvt) &&
1519 !dct_ganging_enabled(pvt) &&
1520 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
1523 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
1525 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
1526 high_range, dct_sel_base);
1528 /* Remove node interleaving, see F1x120 */
1530 chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
1531 (chan_addr & 0xfff);
1533 /* remove channel interleave */
1534 if (dct_interleave_enabled(pvt) &&
1535 !dct_high_range_enabled(pvt) &&
1536 !dct_ganging_enabled(pvt)) {
1538 if (dct_sel_interleave_addr(pvt) != 1) {
1539 if (dct_sel_interleave_addr(pvt) == 0x3)
1541 chan_addr = ((chan_addr >> 10) << 9) |
1542 (chan_addr & 0x1ff);
1544 /* A[6] or hash 6 */
1545 chan_addr = ((chan_addr >> 7) << 6) |
1549 chan_addr = ((chan_addr >> 13) << 12) |
1550 (chan_addr & 0xfff);
1553 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
1555 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1558 *chan_sel = channel;
1563 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
1566 int cs_found = -EINVAL;
1569 for (range = 0; range < DRAM_RANGES; range++) {
1571 if (!dram_rw(pvt, range))
1574 if ((get_dram_base(pvt, range) <= sys_addr) &&
1575 (get_dram_limit(pvt, range) >= sys_addr)) {
1577 cs_found = f1x_match_to_this_node(pvt, range,
1578 sys_addr, chan_sel);
1587 * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
1588 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
1590 * The @sys_addr is usually an error address received from the hardware
1593 static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1594 struct err_info *err)
1596 struct amd64_pvt *pvt = mci->pvt_info;
1598 error_address_to_page_and_offset(sys_addr, err);
1600 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
1601 if (err->csrow < 0) {
1602 err->err_code = ERR_CSROW;
1607 * We need the syndromes for channel detection only when we're
1608 * ganged. Otherwise @chan should already contain the channel at
1611 if (dct_ganging_enabled(pvt))
1612 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
1616 * debug routine to display the memory sizes of all logical DIMMs and its
1619 static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1621 int dimm, size0, size1;
1622 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
1623 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1625 if (boot_cpu_data.x86 == 0xf) {
1626 /* K8 families < revF not supported yet */
1627 if (pvt->ext_model < K8_REV_F)
1633 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0;
1634 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
1635 : pvt->csels[0].csbases;
1637 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1640 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1642 /* Dump memory sizes for DIMM and its CSROWs */
1643 for (dimm = 0; dimm < 4; dimm++) {
1646 if (dcsb[dimm*2] & DCSB_CS_ENABLE)
1647 size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
1648 DBAM_DIMM(dimm, dbam));
1651 if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
1652 size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
1653 DBAM_DIMM(dimm, dbam));
1655 amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
1657 dimm * 2 + 1, size1);
1661 static struct amd64_family_type amd64_family_types[] = {
1664 .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
1665 .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC,
1667 .early_channel_count = k8_early_channel_count,
1668 .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
1669 .dbam_to_cs = k8_dbam_to_chip_select,
1670 .read_dct_pci_cfg = k8_read_dct_pci_cfg,
1675 .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
1676 .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC,
1678 .early_channel_count = f1x_early_channel_count,
1679 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
1680 .dbam_to_cs = f10_dbam_to_chip_select,
1681 .read_dct_pci_cfg = f10_read_dct_pci_cfg,
1686 .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
1687 .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3,
1689 .early_channel_count = f1x_early_channel_count,
1690 .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
1691 .dbam_to_cs = f15_dbam_to_chip_select,
1692 .read_dct_pci_cfg = f15_read_dct_pci_cfg,
1698 * These are tables of eigenvectors (one per line) which can be used for the
1699 * construction of the syndrome tables. The modified syndrome search algorithm
1700 * uses those to find the symbol in error and thus the DIMM.
1702 * Algorithm courtesy of Ross LaFetra from AMD.
1704 static const u16 x4_vectors[] = {
1705 0x2f57, 0x1afe, 0x66cc, 0xdd88,
1706 0x11eb, 0x3396, 0x7f4c, 0xeac8,
1707 0x0001, 0x0002, 0x0004, 0x0008,
1708 0x1013, 0x3032, 0x4044, 0x8088,
1709 0x106b, 0x30d6, 0x70fc, 0xe0a8,
1710 0x4857, 0xc4fe, 0x13cc, 0x3288,
1711 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
1712 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
1713 0x15c1, 0x2a42, 0x89ac, 0x4758,
1714 0x2b03, 0x1602, 0x4f0c, 0xca08,
1715 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
1716 0x8ba7, 0x465e, 0x244c, 0x1cc8,
1717 0x2b87, 0x164e, 0x642c, 0xdc18,
1718 0x40b9, 0x80de, 0x1094, 0x20e8,
1719 0x27db, 0x1eb6, 0x9dac, 0x7b58,
1720 0x11c1, 0x2242, 0x84ac, 0x4c58,
1721 0x1be5, 0x2d7a, 0x5e34, 0xa718,
1722 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
1723 0x4c97, 0xc87e, 0x11fc, 0x33a8,
1724 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
1725 0x16b3, 0x3d62, 0x4f34, 0x8518,
1726 0x1e2f, 0x391a, 0x5cac, 0xf858,
1727 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
1728 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
1729 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
1730 0x4397, 0xc27e, 0x17fc, 0x3ea8,
1731 0x1617, 0x3d3e, 0x6464, 0xb8b8,
1732 0x23ff, 0x12aa, 0xab6c, 0x56d8,
1733 0x2dfb, 0x1ba6, 0x913c, 0x7328,
1734 0x185d, 0x2ca6, 0x7914, 0x9e28,
1735 0x171b, 0x3e36, 0x7d7c, 0xebe8,
1736 0x4199, 0x82ee, 0x19f4, 0x2e58,
1737 0x4807, 0xc40e, 0x130c, 0x3208,
1738 0x1905, 0x2e0a, 0x5804, 0xac08,
1739 0x213f, 0x132a, 0xadfc, 0x5ba8,
1740 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
1743 static const u16 x8_vectors[] = {
1744 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
1745 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
1746 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
1747 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
1748 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
1749 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
1750 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
1751 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
1752 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
1753 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
1754 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
1755 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
1756 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
1757 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
1758 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
1759 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
1760 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
1761 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
1762 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
1765 static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
1768 unsigned int i, err_sym;
1770 for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
1772 unsigned v_idx = err_sym * v_dim;
1773 unsigned v_end = (err_sym + 1) * v_dim;
1775 /* walk over all 16 bits of the syndrome */
1776 for (i = 1; i < (1U << 16); i <<= 1) {
1778 /* if bit is set in that eigenvector... */
1779 if (v_idx < v_end && vectors[v_idx] & i) {
1780 u16 ev_comp = vectors[v_idx++];
1782 /* ... and bit set in the modified syndrome, */
1792 /* can't get to zero, move to next symbol */
1797 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
1801 static int map_err_sym_to_channel(int err_sym, int sym_size)
1814 return err_sym >> 4;
1820 /* imaginary bits not in a DIMM */
1822 WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
1834 return err_sym >> 3;
1840 static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
1842 struct amd64_pvt *pvt = mci->pvt_info;
1845 if (pvt->ecc_sym_sz == 8)
1846 err_sym = decode_syndrome(syndrome, x8_vectors,
1847 ARRAY_SIZE(x8_vectors),
1849 else if (pvt->ecc_sym_sz == 4)
1850 err_sym = decode_syndrome(syndrome, x4_vectors,
1851 ARRAY_SIZE(x4_vectors),
1854 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
1858 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
1861 static void __log_bus_error(struct mem_ctl_info *mci, struct err_info *err,
1864 enum hw_event_mc_err_type err_type;
1868 err_type = HW_EVENT_ERR_CORRECTED;
1869 else if (ecc_type == 1)
1870 err_type = HW_EVENT_ERR_UNCORRECTED;
1872 WARN(1, "Something is rotten in the state of Denmark.\n");
1876 switch (err->err_code) {
1881 string = "Failed to map error addr to a node";
1884 string = "Failed to map error addr to a csrow";
1887 string = "unknown syndrome - possible error reporting race";
1890 string = "WTF error";
1894 edac_mc_handle_error(err_type, mci, 1,
1895 err->page, err->offset, err->syndrome,
1896 err->csrow, err->channel, -1,
1900 static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
1903 struct amd64_pvt *pvt = mci->pvt_info;
1904 u8 ecc_type = (m->status >> 45) & 0x3;
1905 u8 xec = XEC(m->status, 0x1f);
1906 u16 ec = EC(m->status);
1908 struct err_info err;
1910 /* Bail out early if this was an 'observed' error */
1911 if (PP(ec) == NBSL_PP_OBS)
1914 /* Do only ECC errors */
1915 if (xec && xec != F10_NBSL_EXT_ERR_ECC)
1918 memset(&err, 0, sizeof(err));
1920 sys_addr = get_error_address(m);
1923 err.syndrome = extract_syndrome(m->status);
1925 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
1927 __log_bus_error(mci, &err, ecc_type);
1930 void amd64_decode_bus_error(int node_id, struct mce *m)
1932 __amd64_decode_bus_error(mcis[node_id], m);
1936 * Use pvt->F2 which contains the F2 CPU PCI device to get the related
1937 * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error.
1939 static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
1941 /* Reserve the ADDRESS MAP Device */
1942 pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2);
1944 amd64_err("error address map device not found: "
1945 "vendor %x device 0x%x (broken BIOS?)\n",
1946 PCI_VENDOR_ID_AMD, f1_id);
1950 /* Reserve the MISC Device */
1951 pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2);
1953 pci_dev_put(pvt->F1);
1956 amd64_err("error F3 device not found: "
1957 "vendor %x device 0x%x (broken BIOS?)\n",
1958 PCI_VENDOR_ID_AMD, f3_id);
1962 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
1963 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
1964 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
1969 static void free_mc_sibling_devs(struct amd64_pvt *pvt)
1971 pci_dev_put(pvt->F1);
1972 pci_dev_put(pvt->F3);
1976 * Retrieve the hardware registers of the memory controller (this includes the
1977 * 'Address Map' and 'Misc' device regs)
1979 static void read_mc_regs(struct amd64_pvt *pvt)
1981 struct cpuinfo_x86 *c = &boot_cpu_data;
1987 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
1988 * those are Read-As-Zero
1990 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
1991 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
1993 /* check first whether TOP_MEM2 is enabled */
1994 rdmsrl(MSR_K8_SYSCFG, msr_val);
1995 if (msr_val & (1U << 21)) {
1996 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
1997 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
1999 edac_dbg(0, " TOP_MEM2 disabled\n");
2001 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2003 read_dram_ctl_register(pvt);
2005 for (range = 0; range < DRAM_RANGES; range++) {
2008 /* read settings for this DRAM range */
2009 read_dram_base_limit_regs(pvt, range);
2011 rw = dram_rw(pvt, range);
2015 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
2017 get_dram_base(pvt, range),
2018 get_dram_limit(pvt, range));
2020 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
2021 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
2022 (rw & 0x1) ? "R" : "-",
2023 (rw & 0x2) ? "W" : "-",
2024 dram_intlv_sel(pvt, range),
2025 dram_dst_node(pvt, range));
2028 read_dct_base_mask(pvt);
2030 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
2031 amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0);
2033 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
2035 amd64_read_dct_pci_cfg(pvt, DCLR0, &pvt->dclr0);
2036 amd64_read_dct_pci_cfg(pvt, DCHR0, &pvt->dchr0);
2038 if (!dct_ganging_enabled(pvt)) {
2039 amd64_read_dct_pci_cfg(pvt, DCLR1, &pvt->dclr1);
2040 amd64_read_dct_pci_cfg(pvt, DCHR1, &pvt->dchr1);
2043 pvt->ecc_sym_sz = 4;
2045 if (c->x86 >= 0x10) {
2046 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
2047 amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
2049 /* F10h, revD and later can do x8 ECC too */
2050 if ((c->x86 > 0x10 || c->x86_model > 7) && tmp & BIT(25))
2051 pvt->ecc_sym_sz = 8;
2053 dump_misc_regs(pvt);
2057 * NOTE: CPU Revision Dependent code
2060 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2061 * k8 private pointer to -->
2062 * DRAM Bank Address mapping register
2064 * DCL register where dual_channel_active is
2066 * The DBAM register consists of 4 sets of 4 bits each definitions:
2069 * 0-3 CSROWs 0 and 1
2070 * 4-7 CSROWs 2 and 3
2071 * 8-11 CSROWs 4 and 5
2072 * 12-15 CSROWs 6 and 7
2074 * Values range from: 0 to 15
2075 * The meaning of the values depends on CPU revision and dual-channel state,
2076 * see relevant BKDG more info.
2078 * The memory controller provides for total of only 8 CSROWs in its current
2079 * architecture. Each "pair" of CSROWs normally represents just one DIMM in
2080 * single channel or two (2) DIMMs in dual channel mode.
2082 * The following code logic collapses the various tables for CSROW based on CPU
2086 * The number of PAGE_SIZE pages on the specified CSROW number it
2090 static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
2092 u32 cs_mode, nr_pages;
2093 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
2097 * The math on this doesn't look right on the surface because x/2*4 can
2098 * be simplified to x*2 but this expression makes use of the fact that
2099 * it is integral math where 1/2=0. This intermediate value becomes the
2100 * number of bits to shift the DBAM register to extract the proper CSROW
2103 cs_mode = DBAM_DIMM(csrow_nr / 2, dbam);
2105 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
2107 edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
2108 csrow_nr, dct, cs_mode);
2109 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
2115 * Initialize the array of csrow attribute instances, based on the values
2116 * from pci config hardware registers.
2118 static int init_csrows(struct mem_ctl_info *mci)
2120 struct amd64_pvt *pvt = mci->pvt_info;
2121 struct csrow_info *csrow;
2122 struct dimm_info *dimm;
2123 enum edac_type edac_mode;
2124 enum mem_type mtype;
2125 int i, j, empty = 1;
2129 amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
2133 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
2134 pvt->mc_node_id, val,
2135 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
2138 * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
2140 for_each_chip_select(i, 0, pvt) {
2141 bool row_dct0 = !!csrow_enabled(i, 0, pvt);
2142 bool row_dct1 = false;
2144 if (boot_cpu_data.x86 != 0xf)
2145 row_dct1 = !!csrow_enabled(i, 1, pvt);
2147 if (!row_dct0 && !row_dct1)
2150 csrow = mci->csrows[i];
2153 edac_dbg(1, "MC node: %d, csrow: %d\n",
2154 pvt->mc_node_id, i);
2157 nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
2159 /* K8 has only one DCT */
2160 if (boot_cpu_data.x86 != 0xf && row_dct1)
2161 nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
2163 mtype = amd64_determine_memory_type(pvt, i);
2165 edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
2168 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
2170 if (pvt->nbcfg & NBCFG_ECC_ENABLE)
2171 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ?
2172 EDAC_S4ECD4ED : EDAC_SECDED;
2174 edac_mode = EDAC_NONE;
2176 for (j = 0; j < pvt->channel_count; j++) {
2177 dimm = csrow->channels[j]->dimm;
2178 dimm->mtype = mtype;
2179 dimm->edac_mode = edac_mode;
2180 dimm->nr_pages = nr_pages;
2182 csrow->nr_pages = nr_pages;
2188 /* get all cores on this DCT */
2189 static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
2193 for_each_online_cpu(cpu)
2194 if (amd_get_nb_id(cpu) == nid)
2195 cpumask_set_cpu(cpu, mask);
2198 /* check MCG_CTL on all the cpus on this node */
2199 static bool amd64_nb_mce_bank_enabled_on_node(u16 nid)
2205 if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
2206 amd64_warn("%s: Error allocating mask\n", __func__);
2210 get_cpus_on_this_dct_cpumask(mask, nid);
2212 rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
2214 for_each_cpu(cpu, mask) {
2215 struct msr *reg = per_cpu_ptr(msrs, cpu);
2216 nbe = reg->l & MSR_MCGCTL_NBE;
2218 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2220 (nbe ? "enabled" : "disabled"));
2228 free_cpumask_var(mask);
2232 static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
2234 cpumask_var_t cmask;
2237 if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
2238 amd64_warn("%s: error allocating mask\n", __func__);
2242 get_cpus_on_this_dct_cpumask(cmask, nid);
2244 rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2246 for_each_cpu(cpu, cmask) {
2248 struct msr *reg = per_cpu_ptr(msrs, cpu);
2251 if (reg->l & MSR_MCGCTL_NBE)
2252 s->flags.nb_mce_enable = 1;
2254 reg->l |= MSR_MCGCTL_NBE;
2257 * Turn off NB MCE reporting only when it was off before
2259 if (!s->flags.nb_mce_enable)
2260 reg->l &= ~MSR_MCGCTL_NBE;
2263 wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
2265 free_cpumask_var(cmask);
2270 static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2274 u32 value, mask = 0x3; /* UECC/CECC enable */
2276 if (toggle_ecc_err_reporting(s, nid, ON)) {
2277 amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
2281 amd64_read_pci_cfg(F3, NBCTL, &value);
2283 s->old_nbctl = value & mask;
2284 s->nbctl_valid = true;
2287 amd64_write_pci_cfg(F3, NBCTL, value);
2289 amd64_read_pci_cfg(F3, NBCFG, &value);
2291 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2292 nid, value, !!(value & NBCFG_ECC_ENABLE));
2294 if (!(value & NBCFG_ECC_ENABLE)) {
2295 amd64_warn("DRAM ECC disabled on this node, enabling...\n");
2297 s->flags.nb_ecc_prev = 0;
2299 /* Attempt to turn on DRAM ECC Enable */
2300 value |= NBCFG_ECC_ENABLE;
2301 amd64_write_pci_cfg(F3, NBCFG, value);
2303 amd64_read_pci_cfg(F3, NBCFG, &value);
2305 if (!(value & NBCFG_ECC_ENABLE)) {
2306 amd64_warn("Hardware rejected DRAM ECC enable,"
2307 "check memory DIMM configuration.\n");
2310 amd64_info("Hardware accepted DRAM ECC Enable\n");
2313 s->flags.nb_ecc_prev = 1;
2316 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2317 nid, value, !!(value & NBCFG_ECC_ENABLE));
2322 static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
2325 u32 value, mask = 0x3; /* UECC/CECC enable */
2328 if (!s->nbctl_valid)
2331 amd64_read_pci_cfg(F3, NBCTL, &value);
2333 value |= s->old_nbctl;
2335 amd64_write_pci_cfg(F3, NBCTL, value);
2337 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
2338 if (!s->flags.nb_ecc_prev) {
2339 amd64_read_pci_cfg(F3, NBCFG, &value);
2340 value &= ~NBCFG_ECC_ENABLE;
2341 amd64_write_pci_cfg(F3, NBCFG, value);
2344 /* restore the NB Enable MCGCTL bit */
2345 if (toggle_ecc_err_reporting(s, nid, OFF))
2346 amd64_warn("Error restoring NB MCGCTL settings!\n");
2350 * EDAC requires that the BIOS have ECC enabled before
2351 * taking over the processing of ECC errors. A command line
2352 * option allows to force-enable hardware ECC later in
2353 * enable_ecc_error_reporting().
2355 static const char *ecc_msg =
2356 "ECC disabled in the BIOS or no ECC capability, module will not load.\n"
2357 " Either enable ECC checking or force module loading by setting "
2358 "'ecc_enable_override'.\n"
2359 " (Note that use of the override may cause unknown side effects.)\n";
2361 static bool ecc_enabled(struct pci_dev *F3, u16 nid)
2365 bool nb_mce_en = false;
2367 amd64_read_pci_cfg(F3, NBCFG, &value);
2369 ecc_en = !!(value & NBCFG_ECC_ENABLE);
2370 amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
2372 nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
2374 amd64_notice("NB MCE bank disabled, set MSR "
2375 "0x%08x[4] on node %d to enable.\n",
2376 MSR_IA32_MCG_CTL, nid);
2378 if (!ecc_en || !nb_mce_en) {
2379 amd64_notice("%s", ecc_msg);
2385 static int set_mc_sysfs_attrs(struct mem_ctl_info *mci)
2389 rc = amd64_create_sysfs_dbg_files(mci);
2393 if (boot_cpu_data.x86 >= 0x10) {
2394 rc = amd64_create_sysfs_inject_files(mci);
2402 static void del_mc_sysfs_attrs(struct mem_ctl_info *mci)
2404 amd64_remove_sysfs_dbg_files(mci);
2406 if (boot_cpu_data.x86 >= 0x10)
2407 amd64_remove_sysfs_inject_files(mci);
2410 static void setup_mci_misc_attrs(struct mem_ctl_info *mci,
2411 struct amd64_family_type *fam)
2413 struct amd64_pvt *pvt = mci->pvt_info;
2415 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
2416 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2418 if (pvt->nbcap & NBCAP_SECDED)
2419 mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
2421 if (pvt->nbcap & NBCAP_CHIPKILL)
2422 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
2424 mci->edac_cap = amd64_determine_edac_cap(pvt);
2425 mci->mod_name = EDAC_MOD_STR;
2426 mci->mod_ver = EDAC_AMD64_VERSION;
2427 mci->ctl_name = fam->ctl_name;
2428 mci->dev_name = pci_name(pvt->F2);
2429 mci->ctl_page_to_phys = NULL;
2431 /* memory scrubber interface */
2432 mci->set_sdram_scrub_rate = amd64_set_scrub_rate;
2433 mci->get_sdram_scrub_rate = amd64_get_scrub_rate;
2437 * returns a pointer to the family descriptor on success, NULL otherwise.
2439 static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
2441 u8 fam = boot_cpu_data.x86;
2442 struct amd64_family_type *fam_type = NULL;
2446 fam_type = &amd64_family_types[K8_CPUS];
2447 pvt->ops = &amd64_family_types[K8_CPUS].ops;
2451 fam_type = &amd64_family_types[F10_CPUS];
2452 pvt->ops = &amd64_family_types[F10_CPUS].ops;
2456 fam_type = &amd64_family_types[F15_CPUS];
2457 pvt->ops = &amd64_family_types[F15_CPUS].ops;
2461 amd64_err("Unsupported family!\n");
2465 pvt->ext_model = boot_cpu_data.x86_model >> 4;
2467 amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
2469 (pvt->ext_model >= K8_REV_F ? "revF or later "
2470 : "revE or earlier ")
2471 : ""), pvt->mc_node_id);
2475 static int amd64_init_one_instance(struct pci_dev *F2)
2477 struct amd64_pvt *pvt = NULL;
2478 struct amd64_family_type *fam_type = NULL;
2479 struct mem_ctl_info *mci = NULL;
2480 struct edac_mc_layer layers[2];
2482 u16 nid = amd_get_node_id(F2);
2485 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
2489 pvt->mc_node_id = nid;
2493 fam_type = amd64_per_family_init(pvt);
2498 err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id);
2505 * We need to determine how many memory channels there are. Then use
2506 * that information for calculating the size of the dynamic instance
2507 * tables in the 'mci' structure.
2510 pvt->channel_count = pvt->ops->early_channel_count(pvt);
2511 if (pvt->channel_count < 0)
2515 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
2516 layers[0].size = pvt->csels[0].b_cnt;
2517 layers[0].is_virt_csrow = true;
2518 layers[1].type = EDAC_MC_LAYER_CHANNEL;
2519 layers[1].size = pvt->channel_count;
2520 layers[1].is_virt_csrow = false;
2521 mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
2525 mci->pvt_info = pvt;
2526 mci->pdev = &pvt->F2->dev;
2529 setup_mci_misc_attrs(mci, fam_type);
2531 if (init_csrows(mci))
2532 mci->edac_cap = EDAC_FLAG_NONE;
2535 if (edac_mc_add_mc(mci)) {
2536 edac_dbg(1, "failed edac_mc_add_mc()\n");
2539 if (set_mc_sysfs_attrs(mci)) {
2540 edac_dbg(1, "failed edac_mc_add_mc()\n");
2544 /* register stuff with EDAC MCE */
2545 if (report_gart_errors)
2546 amd_report_gart_errors(true);
2548 amd_register_ecc_decoder(amd64_decode_bus_error);
2552 atomic_inc(&drv_instances);
2557 edac_mc_del_mc(mci->pdev);
2562 free_mc_sibling_devs(pvt);
2571 static int amd64_probe_one_instance(struct pci_dev *pdev,
2572 const struct pci_device_id *mc_type)
2574 u16 nid = amd_get_node_id(pdev);
2575 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
2576 struct ecc_settings *s;
2579 ret = pci_enable_device(pdev);
2581 edac_dbg(0, "ret=%d\n", ret);
2586 s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
2592 if (!ecc_enabled(F3, nid)) {
2595 if (!ecc_enable_override)
2598 amd64_warn("Forcing ECC on!\n");
2600 if (!enable_ecc_error_reporting(s, nid, F3))
2604 ret = amd64_init_one_instance(pdev);
2606 amd64_err("Error probing instance: %d\n", nid);
2607 restore_ecc_error_reporting(s, nid, F3);
2614 ecc_stngs[nid] = NULL;
2620 static void amd64_remove_one_instance(struct pci_dev *pdev)
2622 struct mem_ctl_info *mci;
2623 struct amd64_pvt *pvt;
2624 u16 nid = amd_get_node_id(pdev);
2625 struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
2626 struct ecc_settings *s = ecc_stngs[nid];
2628 mci = find_mci_by_dev(&pdev->dev);
2629 del_mc_sysfs_attrs(mci);
2630 /* Remove from EDAC CORE tracking list */
2631 mci = edac_mc_del_mc(&pdev->dev);
2635 pvt = mci->pvt_info;
2637 restore_ecc_error_reporting(s, nid, F3);
2639 free_mc_sibling_devs(pvt);
2641 /* unregister from EDAC MCE */
2642 amd_report_gart_errors(false);
2643 amd_unregister_ecc_decoder(amd64_decode_bus_error);
2645 kfree(ecc_stngs[nid]);
2646 ecc_stngs[nid] = NULL;
2648 /* Free the EDAC CORE resources */
2649 mci->pvt_info = NULL;
2657 * This table is part of the interface for loading drivers for PCI devices. The
2658 * PCI core identifies what devices are on a system during boot, and then
2659 * inquiry this table to see if this driver is for a given device found.
2661 static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {
2663 .vendor = PCI_VENDOR_ID_AMD,
2664 .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
2665 .subvendor = PCI_ANY_ID,
2666 .subdevice = PCI_ANY_ID,
2671 .vendor = PCI_VENDOR_ID_AMD,
2672 .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
2673 .subvendor = PCI_ANY_ID,
2674 .subdevice = PCI_ANY_ID,
2679 .vendor = PCI_VENDOR_ID_AMD,
2680 .device = PCI_DEVICE_ID_AMD_15H_NB_F2,
2681 .subvendor = PCI_ANY_ID,
2682 .subdevice = PCI_ANY_ID,
2689 MODULE_DEVICE_TABLE(pci, amd64_pci_table);
2691 static struct pci_driver amd64_pci_driver = {
2692 .name = EDAC_MOD_STR,
2693 .probe = amd64_probe_one_instance,
2694 .remove = amd64_remove_one_instance,
2695 .id_table = amd64_pci_table,
2698 static void setup_pci_device(void)
2700 struct mem_ctl_info *mci;
2701 struct amd64_pvt *pvt;
2709 pvt = mci->pvt_info;
2711 edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
2713 if (!amd64_ctl_pci) {
2714 pr_warning("%s(): Unable to create PCI control\n",
2717 pr_warning("%s(): PCI error report via EDAC not set\n",
2723 static int __init amd64_edac_init(void)
2727 printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);
2731 if (amd_cache_northbridges() < 0)
2735 mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL);
2736 ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL);
2737 if (!(mcis && ecc_stngs))
2740 msrs = msrs_alloc();
2744 err = pci_register_driver(&amd64_pci_driver);
2749 if (!atomic_read(&drv_instances))
2750 goto err_no_instances;
2756 pci_unregister_driver(&amd64_pci_driver);
2773 static void __exit amd64_edac_exit(void)
2776 edac_pci_release_generic_ctl(amd64_ctl_pci);
2778 pci_unregister_driver(&amd64_pci_driver);
2790 module_init(amd64_edac_init);
2791 module_exit(amd64_edac_exit);
2793 MODULE_LICENSE("GPL");
2794 MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
2795 "Dave Peterson, Thayne Harbaugh");
2796 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
2797 EDAC_AMD64_VERSION);
2799 module_param(edac_op_state, int, 0444);
2800 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");